SAB-C167CR-LM

Manufacturer Part NumberSAB-C167CR-LM
Description16-bit microcontroller with 2x2 KByte RAM
ManufacturerInfineon Technologies AG
SAB-C167CR-LM datasheet
 


1
2
3
4
5
6
7
8
9
10
11
Page 11
12
Page 12
13
Page 13
14
Page 14
15
Page 15
16
Page 16
17
Page 17
18
Page 18
19
Page 19
20
Page 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Page 13/74

Download datasheet (2Mb)Embed
PrevNext
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Input
Num.
Outp.
P4
IO
P4.0
85
O
P4.1
86
O
P4.2
87
O
P4.3
88
O
P4.4
89
O
P4.5
90
O
I
P4.6
91
O
O
P4.7
92
O
RD
95
O
WR/
96
O
WRL
READY 97
I
ALE
98
O
EA
99
I
Data Sheet
Function
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
Port 4 can be used to output the segment address lines and
for serial bus interfaces:
A16
Least Significant Segment Address Line
A17
Segment Address Line
A18
Segment Address Line
A19
Segment Address Line
A20
Segment Address Line
A21
Segment Address Line,
CAN1_RxD CAN 1 Receive Data Input
A22
Segment Address Line,
CAN1_TxD CAN 1 Transmit Data Output
A23
Most Significant Segment Address Line
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
Ready Input. When the Ready function is enabled, a high
level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.
An internal pullup device will hold this pin high when nothing
is driving it.
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
External Access Enable pin. A low level at this pin during and
after Reset forces the C167CR to begin instruction execution
out of external memory. A high level forces execution out of
the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.
9
C167CR
C167SR
V3.2, 2001-07