CXL5005P Sony, CXL5005P Datasheet

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CXL5005P

Manufacturer Part Number
CXL5005P
Description
CMOS-CCD 1H Delay Line for NTSC with PLL
Manufacturer
Sony
Datasheet
For the availability of this product, please contact the sales office.
Description
line ICs which provide 1H delay time of NTSC.
Features
• Low power consumption 90mW (Typ.)
• Small size package (14-pin SOP, DIP)
• Low differential gain DG = 3% (Typ.)
• Input signal ampiitude 180 IRE (= 1.28Vp-p, max.)
• Low input clock amplitude operation 200mVp-p (Min.)
• Built-in triple PLL circuit
• Built-in peripheral circuits (clock driver, timing
Functions
• 680-bit CCD register
• Clock drivers
• Autobias circuit
• Sync tip clamp circuit
• Sample-and-hold circuit
• PLL (triple)
Structure
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
• Supply voltage
• Operating temperature
• Storage temperature
• Allowable power dissipation P
Recommended Operating Conditions
Recommended Clock Conditions
• Input clock amplitude
• Clock frequency
The CXL5005M/P are general-purpose CCD delay
generator, auto-bias and output circuits)
CMOS-CCD
Supply voltage
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CMOS-CCD 1H Delay Line for NTSC with PLL
V
V
CXL5005M 400 mW
CXL5005P
V
V
f
Topr –10 to +60
Tstg –55 to +150 °C
V
CLK
DD
CL
D
DD
CL
CLK
200mVp-p to 1.0Vp-p
(300mVp-p typ.)
3.579545MHz
9 ± 5%
5 ± 5%
11
6
800 mW
°C
V
V
V
V
– 1 –
14 pin SOP (Plastic)
CXL5005M/P
CXL5005M
14 pin DIP (Plastic)
CXL5005P
E88Z40A79-PS

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CXL5005P Summary of contents

Page 1

... Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXL5005M/P 14 pin SOP (Plastic Topr –10 to +60 °C Tstg –55 to +150 °C D CXL5005M 400 mW CXL5005P 800 ± ± 200mVp-p to 1.0Vp-p CLK (300mVp-p typ.) f 3.579545MHz CLK – 1 – CXL5005M CXL5005P 14 pin DIP (Plastic) E88Z40A79-PS ...

Page 2

Blook Diagram and Pin configuration 14 Clamp circuit 1 Pin Description Pin No. Symbol 1 V GND power supply CL 3 VCO VCO input power supply DD 5 Phase comparator output PC ...

Page 3

Electrical Characteristics (Ta = 25°C, V Item Symbol I DD 250kHz, 1.28Vp-p, Supply current sine wave input I CL 250kHz, 1.28Vp-p, sine wave input Insertion gain log (Output voltage [Vp-p] / 1.28 [Vp-p]) Dissipation at 3.58MHz ...

Page 4

CXL5005M/P ...

Page 5

Note 1) Frequency response test condition V (Output signal voltage [Vp-p] at 3.58MHz input) 3.58MHz V (Output signal voltage [Vp-p] at 250kHz input) 250kHz Set Pin 14 (IN) voltage [ 3.58MHz, 300mVp-p sine wave 250kHz, 300mVp-p sine wave ...

Page 6

... Composite video signal input 1M Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Example of Representative Characteristics Frequency response vs ...

Page 7

Insertion gain vs. Supply voltage Input = 1.28Vp-p 1 250kHz, sine wave 0 –1 –2 –3 4.7 5.0 5.3 V – Supply voltage [V] CL Differential gain vs. Ambient temperature – ...

Page 8

... Package Outline Unit: mm CXL5005M SONY CODE EIAJ CODE JEDEC CODE CXL5005P 14 1.2 ± 0.15 SONY CODE EIAJ CODE JEDEC CODE 14PIN SOP (PLASTIC) + 0.4 9.9 – 0 0.45 ± 0.1 1.27 M 0.24 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT SOP-14P-L01 SOP014-P-0300 LEAD MATERIAL ...

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