P-80C31 Philips Semiconductors, P-80C31 Datasheet
P-80C31
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P-80C31 Summary of contents
Page 1
... OTP/ROM/ROMless low voltage (2.7V–5.5V), low power, high speed (33 MHz) Product specification Supersedes data of 1999 Apr 01 IC28 Data Handbook INTEGRATED CIRCUITS 2000 Jan 20 ...
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... I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the device is a low power static design which offers a wide range of operating frequencies down to zero. Two software selectable modes of power reduction—idle mode and power-down mode are available ...
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... Plastic Quad Flat Pack –40 to +85, Plastic Leaded Chip Carrier 40 to +85 Plastic Leaded Chip Carrier –40 to +85, Plastic Dual In-line Package 40 to +85 Plastic Dual In line Package –40 to +85, Plastic Quad Flat Pack 40 to +85 Plastic Quad Flat Pack TEMPERATURE RANGE ( MHz ...
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... Philips Semiconductors www.DataSheet4U.com 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz) BLOCK DIAGRAM RAM ADDR REGISTER B REGISTER PSEN ALE/PROG TIMING AND EAV PP CONTROL RST PD OSCILLATOR XTAL1 XTAL2 2000 Jan 20 P0.0–P0.7 P2.0–P2.7 PORT 0 ...
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... DUAL RxD/P3.0 10 IN-LINE PACKAGE TxD/P3.1 11 INT0/P3 INT1/P3.3 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 SU01063 2000 Jan 20 PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS ADDRESS AND DATA BUS T2 T2EX Pin Function 1 NIC* 2 P1.0/T2 3 P1.1/T2EX 4 P1.2 5 P1.3 ADDRESS BUS 6 P1.4 7 P1.5 8 P1.6 9 P1.7 10 RST ...
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... XTAL2 NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V 2000 Jan 20 TYPE NAME AND FUNCTION I Ground: 0V reference. I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. I/O Port 0: Port open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs ...
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... SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. – Reserved bits. 1. Reset value depends on reset source. 2. LPEP – Low Power EPROM operation (OTP/EPROM only) 3. Not available on 80C31. 2000 Jan 20 DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION ADDRESS ...
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... For lowest power consumption the Power Down mode is suggested. Idle Mode In idle mode (see Table 2), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated ...
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... RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2 ...
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... TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 T2CON.2 Start/stop control for Timer 2 ...
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... User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate ...
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... C/ C/ PIN NOTE: OSC. Freq. is divided by 2, not 12. OSC Pin Transition Detector T2EX Pin Note availability of additional external interrupt. 2000 Jan 20 (DOWN COUNTING RELOAD VALUE) FFH FFH OVERFLOW TL2 TH2 CONTROL TR2 RCAP2L RCAP2H (UP COUNTING RELOAD VALUE) Figure 5. Timer 2 Auto Reload Mode (DCEN = 1) ...
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... Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. See Table 5 for set-up of Timer timer. Also see Table 6 for set-up of Timer counter. 13 ...
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... Auto-Reload NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode. Enhanced UART The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers ...
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... In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Tl Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Rl Receive interrupt flag ...
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... WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 9. UART Multiprocessor Communication, Automatic Address Recognition 2000 Jan DATA BYTE SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL SM1 SM2 REN TB8 RB8 SMOD0 – POF ...
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... Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables it. BIT SYMBOL FUNCTION IE.7 EA Global disable bit all interrupts are disabled each interrupt can be individually enabled or disabled by setting or clearing its enable bit. IE.6 — Not implemented. Reserved for future use. IE.5 ET2 Timer 2 interrupt enable bit. ...
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... OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz (0B8H) — Priority Bit = 1 assigns higher priority Priority Bit = 0 assigns lower priority BIT SYMBOL FUNCTION IP.7 — Not implemented, reserved for future use. IP.6 — ...
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... The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. 2000 Jan 20 Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC DPTR insstruction without affecting the WOPD or LPEP bits. DPS 2 ...
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... Power dissipation (based on package heat transfer limitations, not device power consumption) NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied ...
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... Capacitive loading on ports 0 and 2 may cause the V address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from The transition current reaches its maximum value when V is approximately 2V. ...
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... Capacitive loading on ports 0 and 2 may cause the V address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from The transition current reaches its maximum value when V is approximately 2V. ...
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... Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 8XC51 and 80C31 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. ...
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... Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 8XC51 and 80C31 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. ...
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... MHz) EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – ...
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... Philips Semiconductors www.DataSheet4U.com 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz) ALE PSEN WR t LLAX t AVLL A0–A7 PORT 0 FROM RI OR DPL t AVWL PORT 2 INSTRUCTION 0 1 ALE CLOCK t QVXH OUTPUT DATA 0 WRITE TO SBUF t XHDV INPUT DATA ...
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... Valid only within frequency specifications of the device under test 2000 Jan LOAD V NOTE: For timing purposes, a port is no longer floating when a 100mV change from max for a logic ‘0’. load voltage occurs, and begins to float when a 100mV change from the loaded level occurs. I ...
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... Philips Semiconductors www.DataSheet4U.com 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz RST (NC) XTAL2 CLOCK SIGNAL XTAL1 V SS Figure 22. I Test Condition, Active Mode CC All other pins are disconnected Figure 24. Clock Signal Waveform for I 2000 Jan 20 ...
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... The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 28. The other pins are held at the ‘Verify Code Data’ levels indicated in Table 8. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation ...
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... 10% during programming and verification ALE/PROG receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while V 12.75V. Each programming pulse is low for 100 and high for a minimum Table 9. Program Security Bits for EPROM Devices 1, 2 PROGRAM LOCK BITS ...
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... Philips Semiconductors www.DataSheet4U.com 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz) A0–A7 4–6MHz ALE/PROG: SEE EXPLODED VIEW BELOW 1 0 ALE/PROG: A0–A7 4–6MHz 2000 Jan RST EA P3.7 ALE/PROG EPROM/OTP PSEN XTAL2 P2.7 P2.6 XTAL1 P2.0– ...
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... SEE TABLE 8. 2000 Jan (See Figure 29) SS PARAMETER PP * PROGRAMMING ADDRESS DATA IN t GHDX t GHAX t GHGL t GHSL LOGIC 1 LOGIC 0 t ELQV Figure 29. EPROM Programming and Verification 32 Product specification 80C51/87C51/80C31 MIN MAX UNIT 12.5 13 MHz 48t CLCL 48t CLCL 48t CLCL 48t CLCL ...
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... NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled. If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: ...
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... Philips Semiconductors www.DataSheet4U.com 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz) DIP40: plastic dual in-line package; 40 leads (600 mil) 2000 Jan 20 80C51/87C51/80C31 34 Product specification SOT129-1 ...
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... Philips Semiconductors www.DataSheet4U.com 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz) PLCC44: plastic leaded chip carrier; 44 leads 2000 Jan 20 80C51/87C51/80C31 35 Product specification SOT187-2 ...
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... Philips Semiconductors www.DataSheet4U.com 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz) QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 1.75 mm 2000 Jan 20 80C51/87C51/80C31 36 Product specification SOT307-2 ...
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... Philips Semiconductors www.DataSheet4U.com 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz) 2000 Jan 20 80C51/87C51/80C31 NOTES 37 Product specification ...
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... Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified ...