LC7218

Manufacturer Part NumberLC7218
DescriptionPLL frequency synthesizer for electronic tuning in AV system
ManufacturerSanyo Semiconductor Corporation
LC7218 datasheet
 


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The LC7218 control data consists of 36 bits. All 36 bits must be input after power is applied to set up the LC7218 initial
state. This is because the last two bits, while being unrelated to user functions, are data that switches the LSI test modes.
Once the LC7218 has been initialized, the contents of the first 24 bits (D
the contents of the last 12 bits (R0 to T1) by inputting data to DI in serial data input mode.
No.
Control block/data
• This data sets up the programmable divider.
D
to D
0
The position of the LSB is changed by DV and SP as listed in the table below.
DV
Programmable divider
data
(1)
1
D
to D
0
15
0
0
* don’t care
When D
• Data that determines the states of the output ports OUT0 to OUT6. O
OUT0 pin output. However, note that when O
is 1, OUT0 will output a low level. O
• These can be used for a wide range of purposes, including, for example, band switching
Output port data
(2)
signals.
O
to O
0
6
• When the TB bit is set to 1, the O
time base signal.
• Since the output port states are undefined when power is first applied, transfer the control data
quickly.
• Data that determines the operation of the general-purpose counter. When CTEN is 0, the 20-bit
binary counter (the general-purpose counter) is reset and the HCTR and LCTR pins are pulled
General-purpose counter
down to ground. When CTEN is set to 1, the general-purpose counter reset state is cleared and
(3)
initial data
the counter operates according to the SC bit (the general-purpose selection data). In this state,
CTEN
the general-purpose counter will count either the HCTR or LCTR input signal.
• Since the general-purpose counter is reset by setting CTEN to 0, the result of a count operation
must be sent to the controller while CTEN is still 1.
• Data that selects one of the ten LC7218 reference frequencies or sets the LC7218 to
backup mode in which PLL operation is disabled.
R
0
0
0
0
0
0
0
0
Reference frequency
data
(4)
0
R
to R
0
3
1
1
1
1
1
1
1
1
Note: * PLL inhibit (backup mode)
LC7218, 7218M, 7218JM
Description
is a binary value with D
as the MSB.
15
15
SP
LSB
Divisor setting
Actual divisor
*
D0
256 to 65536
Twice the set value
1
D0
256 to 65536
The set value
0
D4
4 to 4096
The set value
is the LSB, bits D
to D
are ignored.
4
0
3
is 0, OUT0 will output a high level, and when O
0
to O
function in the same manner.
1
6
data is ignored and the OUT0 pin outputs an 8 Hz clock
0
R
R
R
Reference frequency (kHz)
1
2
3
0
0
0
100
0
0
1
50
0
1
0
25
0
1
1
25
1
0
0
12.5
1
0
1
6.25
1
1
0
3.125
1
1
1
3.125
0
0
0
10
0
0
1
9
0
1
0
5
0
1
1
1
1
0
0
1
0
1
PLL inhibit state*
1
1
0
1
1
1
The programmable divider block is turned off, both the FMIN and AMIN pins are pulled
down to ground, and the charge pump outputs go to the floating state.
to CTEN) can be changed without changing
0
Related data
determines the
0
0
Continued on next page.
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DV
SP
TB
SC
SF
GT