ISL8118IRZ Intersil, ISL8118IRZ Datasheet
ISL8118IRZ
Specifications of ISL8118IRZ
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ISL8118IRZ Summary of contents
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... PGND NUMBER (Note) 17 BGATE ISL8118CRZ* ISL8118CRZ PVCC 16 ISL8118IRZ* ISL8118IRZ EXDRV 15 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 14 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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Block Diagram REFIN REFOUT MARGIN OFSP VOLTAGE MARGINING OFSN OTA SS FB COMP VCC 800mV PGOOD COMP VSENSP VSENSN UNITY GAIN DIFF AMP VDIFF PGDLY PGOOD EN VCC POWER-ON REFERENCE RESET (POR 0.591V REF SOFT-START ...
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Typical Application I (Internal Linear Regulator with Remote Sense) +3.3V to +20V C F1 VIN INTERNAL 5.6V BIAS LINEAR REGULATOR VFF C F3 VCC EN REFIN REFOUT PGOOD C PGDLY PGDLY R FSET FSET MARGIN R OFSP OFSP R MARG ...
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Typical Application II (External Linear Regulator without Remote Sense) +3.3V to +20V DRV EXDRV VIN C F3 VFF REFOUT VCC REFIN EN PGOOD C PGDLY PGDLY R FSET FSET MARGIN R OFSP OFSP R MARG ...
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Typical Application III (Dual Data Rate I or II) VDDQ 1.8V or 2.5V 5V VIN R EN1 VFF EN2 F4 1K REFIN REFOUT 15nF DIMM 1K PGOOD C PGDLY PGDLY R FSET FSET MARGIN R OFSP OFSP ...
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... Thermal Information Thermal Resistance (Notes 1, 2) QFN Package . . . . . . . . . . . . . . . . . . Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150° 0.3V Pb-Free Reflow Profile .see link below BOOT http://www.intersil.com/pbfree/Pb-FreeReflow.asp - .<6V LX TEST CONDITIONS I VIN = VCC = PVCC = 5V 600kHz, VIN TGATE and BGATE Open ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL VCC Hysteresis POR Rising PVCC ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL TGATE Source Saturation Current I ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL Margining Transfer Ratio N Positive ...
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A 10µA current source to GND is active while the part is disabled, and is inactive when the part is enabled. This provides functionality for programmable hysteresis when the EN pin is used for voltage monitoring. VFF (Pin ...
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OV/UV/PGOOD comparators. The VDIFF pin should be connected to the FB pin by a standard feedback network. In the event that the remote sense buffer is disabled, the VDIFF pin should be connected to VOUT by a resistor divider along ...
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VDIFF GOOD OV UV FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW 1.5V ⋅ -------------- - = PGDLY PGDLY 30μA Undervoltage and Overvoltage Protection The Undervoltage (UV) and Overvoltage (OV) protection circuitry compares the voltage on the VDIFF pin with the reference ...
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... High Speed MOSFET Gate Driver The integrated driver has similar drive capability and features to Intersil's ISL6605 stand alone gate driver. The PWM tri-state feature helps prevent a negative transient on the output voltage when the output is being shut down. This ...
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A 1Ω to 2Ω resistor is recommended series with the bootstrap diode when using VCCs above 5.0V to prevent the bootstrap capacitor from overcharging due to the negative swing of the trailing edge of the LX node. ...
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VOUT (LOCAL) GND (LOCAL) VCC 800mV FIGURE 6. SIMPLIFIED UNITY GAIN DIFFERENITAL SENSING IMPLEMENTATION As the VDIFF pin is connected internally to the OV/UV/PGOOD comparator, an external resistor divider must then be connected to VDIFF to provide correct voltage information ...
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Figure 8 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS pin and locate the capacitor, CSS close to the SS ...
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A small capacitor Figure 10, can be added to SEN filter out noise, typically C is chosen so the SEN corresponding time constant does not reduce the overall phase margin of the design, typically this ...
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Component Selection Guidelines Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L28.5x5 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/07 5.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 4. 65 TYP ) ( 3. 10) TYPICAL RECOMMENDED LAND PATTERN 20 ISL8118 A B ...