CDP1881CE

Manufacturer Part NumberCDP1881CE
DescriptionCMOS 6-Bit Latch and Decoder Memory Interfaces
ManufacturerIntersil Corporation
CDP1881CE datasheet
 


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March 1997
Features
• Performs Memory Address Latch and Decoder
Functions Multiplexed or Non-Multiplexed
• Decodes Up to 16K Bytes of Memory
• Interfaces Directly with CDP1800-Series Microproces-
sors at Maximum Clock Frequency
• Can Replace CDP1866 and CDP1867 (Upward Speed
and Function Capability)
Ordering Information
PACKAGE
5V
10V
PDIP
CDP1881CE
-
PDIP
CDP1882CE
-
PDIP
CDP1882CEX
-
Burn-In
SBDIP
-
CDP1882D
Pinouts
CDP1881C
(PDIP)
TOP VIEW
1
CLOCK
MA5
2
3
MA4
MA3
4
MA2
5
MA1
6
MA0
7
MRD
8
MWR
9
V
10
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
|
http://www.intersil.com or 407-727-9207
Copyright
CDP1882, CDP1882C
and Decoder Memory Interfaces
Description
The CDP1881C, CDP1882 and CDP1882C are CMOS 6-bit
memory latch and decoder circuits intended for use in
CDP1800 series microprocessor systems. They can inter-
face directly with the multiplexed address bus of this system
at maximum clock frequency, and up to four 4K x 8-bit mem-
ories to provide a 16K byte memory system. With four 2K x
8-bit memories an 8K byte system can be decoded.
The devices are also compatible with non-multiplexed
address bus microprocessors. By connecting the clock input
to V
, the latches are in the data-following mode and the
DD
decoded outputs can be used in general purpose memory-
system applications.
TEMP.
RANGE
PKG.
The CDP1881C, CDP1882 and CDP1882C are intended for
o
(
C)
NO.
use with 2K or 4K byte RAMs and are identical except that in
-40 to +85
E20.3
the CDP1882 MWR and MRD are excluded.
-40 to +85
E18.3
The CDP1882 is functionally identical to the CDP1882C. It
differs in that the CDP1882 has recommended operating
-40 to +85
E18.3
voltage range of 4V to 10.5V and the C version has a recom-
mended operating voltage range of 4V to 6.5V.
-40 to +85
D18.3
The CDP1881C, CDP1882 and CDP1882C are supplied in
20 lead and 18 lead packages, respectively. The
CDP1881C is supplied only in a dual-in-line plastic pack-
age (E suffix). The CDP1882 is supplied in dual-in-line,
hermetic side-brazed ceramic (D suffix) and in plastic (E
suffix) packages.
20
V
DD
19
A8
18
A9
17
A10
16
A11
15
CS0
14
CS1
13
CS2
12
CS3
11
CE
©
Intersil Corporation 1999
4-1
CDP1881C,
CMOS 6-Bit Latch
CDP1882, CDP1882C
(PDIP, CERDIP)
TOP VIEW
18
CLOCK
V
1
DD
17
MA5
A8
2
16
MA4
A9
3
15
MA3
A10
4
14
A11
MA2
5
13
MA1
CS0
6
12
CS1
MA0
7
11
CS2
CE
8
V
9
10
CS3
SS
File Number
1367.2

CDP1881CE Summary of contents