MP7651AN Exar Corporation, MP7651AN Datasheet
MP7651AN
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MP7651AN Summary of contents
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FEATURES 8 Independent 2-Quadrant Multiplying 8-Bit DACs Serial Digital Input Data and Address Port (3-Wire Standard) plus Internal Chip Address Decoder Dual Supplies (+5 V typ.) High Speed: – 12.5 MHz Digital Clock Rate – Settling Time: ...
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... CC 8 8-Bit Latch DAC 0 8 8-Bit Latch DAC 1 8 8-Bit Latch DAC 4-8 DEC COMP 4 4-Bit CH 4-Bit CS DB0 to DB7 Address Address 16-Bit Shift Register GND V EE INL Part No. (LSB) MP7651AS +1 MP7651AN + CS0P to CS3P 4 4 SDO 3-State Buffer DNL Gain Error (LSB) (% FSR) +0 ...
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PIN CONFIGURATIONS See Packaging Section for Package Dimensions VR1 1 28 VO1 2 27 VO2 3 26 VR2 4 25 VR3 5 24 VO3 GND 9 20 VO4 19 10 ...
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MP7651 ELECTRICAL CHARACTERISTICS TABLE Unless Otherwise Noted Output Load = Open Parameter Symbol DC CHARACTERISTICS Resolution (All Grades) N Differential Non-Linearity DNL Integral Non-Linearity INL Monotonicity Gain Error GE Zero Scale Offset Z OFS ...
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ELECTRICAL CHARACTERISTICS TABLE Description Symbol DIGITAL TIMING 2, 4 SPECIFICATIONS Input Clock Pulse Width Data Setup Time t Data Hold Time t CLK to SDO Propagation Delay t DAC Register Load Pulse Width Reset Pulse Width ...
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MP7651 SDI 1 CS3S CS2S CS1S CS0S (Data In CLK OUT Figure 1. Serial Data Timing and Loading SDI 0 1 SDO 0 1 CSOP-CS3P CLK ...
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THEORY OF OPERATION MP7651 is equipped with a serial data 3-wire standard - processor logic interface to reduce pin count, package size (28 pin), and board wire (space). This interface consists of LD which controls the transfer of data to ...
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MP7651 LAT SDI LAT CLK Figure 4. Internal Chip Address Decoder Plus Logic Interface Rev. 2.00 8 ENABLE DAC NOT USED Decoder D4 D5 ...
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A0 to A23 AS CS VMA MC68000 VPA VDS DB0 to DB15 Figure 5. MC68000 Interface (Simplified Diagram A15 MC6800 02 R/W DB0 to DB7 NOTES: 1. Execute consecutive memory write instructions while manipulating the data between WRITEs ...
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MP7651 APPLICATION NOTES PC DATA CS0P-CS3P LD CLK PC DATA OUT DATA 4 CS0P-CS3P CLK Rev. 2.00 VRI1 VOI1 VRI2 VOI2 MP7651 MP7651 IC (1) IC (2) CS1P CS1P SDI LD SDO SDI ...
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SDO0 SDO1 ROW ADDRESS WR n ADDRESS DECODER 7651 4 0 SDO LD SDI 7651 4 0 SDO LD SDI 7651 4 0 SDO LD SDI Rev. 2.00 SDOE 7651 7651 ...
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MP7651 8085 ALE WR SOD NOTES: 1. Clock generated by WR and decoding address 8000 2. Data is clocked into the DAC shift register by executing memory write instructions. The clock input is generated by decoding address 8000 and WR. ...
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PERFORMANCE CHARACTERISTICS Channel-to-Channel Crosstalk (Gain vs. Frequency; All DACs set to full scale; V Output DACs shown below are: DAC and 4 dB DAC 0 Driven MHz Graph 1. Output DACs shown below are: ...
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MP7651 Digital Input Code Graph 9. Linearity Error vs. Digital Input Code DACs Graph 11. Preset Voltage vs. Temperature V = 500 mV p-p R Phase Gain Graph 13. Gain & Phase vs. Frequency Rev. 2.00 Digital ...
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Graph 15. Gain ( vs. Frequency O R Open Loop/Unloaded Output* Graph 17. I vs. Temperature +1.5% FSR VRR Positive VRR Negative – V Graph 19. Reference Input Voltage Range vs. Supply Voltages * A ...
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MP7651 LD (5 V/DIV Digital Code = 255 0 255 V/DIV) 2 s/DIV Graph 21. Digital Settling V/DIV V/DIV) 2 s/DIV Graph 23. 128 kHz Sawtooth ...
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LEAD PLASTIC DUAL-IN-LINE Seating Plane L B SYMBOL ( Note: (1) The minimum limit for dimensions B1 may ...
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MP7651 28 1 Seating Plane e Rev. 2.00 28 LEAD SMALL OUTLINE (335 MIL EIAJ SOIC) R28 MILLIMETERS INCHES SYMBOL MIN MAX MIN A 2.60 2.80 0.102 A 0.2 (typ.) 0.008 ...
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Rev. 2.00 Notes 19 MP7651 ...
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... While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized ...