A6812SA

Manufacturer Part NumberA6812SA
DescriptionDABic-IV,20-Bit serial-input,latched source driver
ManufacturerAllegro Micro Systems, Inc.
A6812SA datasheet
 
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Features and Benefits
▪ Controlled output slew rate
▪ High-speed data storage
▪ 60 V minimum output break down
▪ High data-input rate
▪ PNP active pull-downs
▪ Low output-saturation voltages
▪ Low-power CMOS logic and latches
▪ Improved replacements for TL5812x, UCN5812x, and
UCQ5812x
Package:
28-pin SOICW
(Package LW)
Not to scale
26182.126D
DABiC-IV 20-Bit Serial-Input
Description
The A6812 device combines a 20-bit CMOS shift register,
ac com pa ny ing data latches and control cir cuit ry with bipolar
sourcing out puts ,and PNP active pull-downs. De signed
pri mar ily to drive vacuum-flu o res cent displays, the 60 V and
-40 mA output ratings also allow these devices to be used in
many other peripheral power driver applications. The A6812
features an increased data-input rate (com pared with the older
UCN/UCQ5812-F) and a controlled output slew rate.
The CMOS shift register and latches allow direct interfacing
with mi cro pro ces sor-based systems. With a 3.3 or 5 V logic
supply, they operate to at least 10 MHz.
A CMOS serial data output permits cascaded con nec tions in
ap pli ca tions re quir ing additional drive lines. Similar devices
are avail able as the A6810 (10-bit) and A6818 (32-bit).
The A6812 output source drivers are NPN Dar ling tons,
capable of sourcing up to 40 mA. The controlled output slew
rate reduces elec tro mag net ic noise, which is an important
consideration in systems that include telecommunications
and/or microprocessors and to meet government emis sions
28-pin PLCC
(EP package)
Continued on the next page…
Functional Block Diagram
A6812
Latched Source Driver

A6812SA Summary of contents