A6812SA Allegro Micro Systems, Inc., A6812SA Datasheet

no-image

A6812SA

Manufacturer Part Number
A6812SA
Description
DABic-IV,20-Bit serial-input,latched source driver
Manufacturer
Allegro Micro Systems, Inc.
Datasheet
Features and Benefits
▪ Controlled output slew rate
▪ High-speed data storage
▪ 60 V minimum output break down
▪ High data-input rate
▪ PNP active pull-downs
▪ Low output-saturation voltages
▪ Low-power CMOS logic and latches
▪ Improved replacements for TL5812x, UCN5812x, and
Package:
26182.126D
UCQ5812x
28-pin SOICW
(Package LW)
Not to scale
28-pin PLCC
(EP package)
Functional Block Diagram
DABiC-IV 20-Bit Serial-Input
Description
The A6812 device combines a 20-bit CMOS shift register,
ac com pa ny ing data latches and control cir cuit ry with bipolar
sourcing out puts ,and PNP active pull-downs. De signed
pri mar ily to drive vacuum-flu o res cent displays, the 60 V and
-40 mA output ratings also allow these devices to be used in
many other peripheral power driver applications. The A6812
features an increased data-input rate (com pared with the older
UCN/UCQ5812-F) and a controlled output slew rate.
The CMOS shift register and latches allow direct interfacing
with mi cro pro ces sor-based systems. With a 3.3 or 5 V logic
supply, they operate to at least 10 MHz.
A CMOS serial data output permits cascaded con nec tions in
ap pli ca tions re quir ing additional drive lines. Similar devices
are avail able as the A6810 (10-bit) and A6818 (32-bit).
The A6812 output source drivers are NPN Dar ling tons,
capable of sourcing up to 40 mA. The controlled output slew
rate reduces elec tro mag net ic noise, which is an important
consideration in systems that include telecommunications
and/or microprocessors and to meet government emis sions
Continued on the next page…
Latched Source Driver
A6812

Related parts for A6812SA

A6812SA Summary of contents

Page 1

Features and Benefits ▪ Controlled output slew rate ▪ High-speed data storage ▪ minimum output break down ▪ High data-input rate ▪ PNP active pull-downs ▪ Low output-saturation voltages ▪ Low-power CMOS logic and latches ▪ Improved replacements ...

Page 2

A6812 Description (continued) regulations. For inter-digit blanking, all output drivers can be dis abled and all sink drivers turned on with a BLANK ING input high. The PNP active pull-downs sink at least 2.5 mA. Three temperature ranges are available ...

Page 3

A6812 Absolute Maximum Ratings* Characteristic Logic Supply Voltage Driver Supply Voltage Input Voltage Range Continuous Output Current Range Operating Ambient Temperature Maximum Junction Temperature Storage Temperature *Caution: These CMOS devices have input static protection (Class 2) but are still susceptible ...

Page 4

A6812 EP Package OUT OUT 12 TYPICAL INPUT CIRCUIT IN DABiC-IV 20-Bit Serial-Input SUPPLY SERIAL DATA OUT 25 OUT OUT 8 BLANKING GROUND Dwg. PP-059-1 ...

Page 5

A6812 Serial Shift Register Contents Data Clock Input Input ... N ... N ... N ...

Page 6

A6812 ELECTRICAL CHARACTERISTICS at T A6812K-), less otherwise noted BB Characteristic Symbol Output Leakage Current I Output Voltage V OUT(1) V OUT(0) Output Pull-Down Current I OUT(0) Input Voltage V V Input Current I I ...

Page 7

A6812 TIMING REQUIREMENTS and SPECIFICATIONS CLOCK SERIAL DATA IN SERIAL DATA OUT STROBE BLANKING OUT N BLANKING OUT N A. Data Active Time Before Clock Pulse (Data Set-Up Time), t ........................................ 25 ns su(D) B. Data Active Time After Clock ...

Page 8

A6812 12.45±0.13 28X DABiC-IV 20-Bit Serial-Input EP Package, 28-Pin PLCC 12.45±0.13 11.51±0. 11.51±0.08 0.74±0.08 0.10 C 0.43±0.10 5.21±0.36 5.21±0.36 For Reference Only (reference JEDEC MS-018 AB) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, ...

Page 9

A6812 17.90±0. 28X 0.1 C 0.41 ±0.10 For Reference Only (Reference JEDEC MS-013 AE) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown Copyright ...

Related keywords