SAK-C167CR-4RM

Manufacturer Part NumberSAK-C167CR-4RM
Description16 Bit Single-Chip Microcontroller
ManufacturerInfineon Technologies AG
SAK-C167CR-4RM datasheet
 


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Page 61/74:

AC Characteristics

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AC Characteristics

Table 14
CLKOUT Reference Signal
Parameter
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
1)
The CLKOUT cycle time is influenced by the PLL jitter.
For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for
For longer periods the relative deviation decreases (see PLL deviation formula).
tc
CLKOUT
Figure 14
CLKOUT Signal Timing
Variable Memory Cycles
The bus timing shown below is programmable via the BUSCONx registers. The duration
of ALE and two types of waitstates can be selected. This table summarizes the possible
bus cycle durations.
Table 15
Variable Memory Cycles
Bus Cycle Type
Demultiplexed bus cycle
with normal ALE
Demultiplexed bus cycle
with extended ALE
Multiplexed bus cycle with
normal ALE
Multiplexed bus cycle with
extended ALE
Data Sheet
tc
7
tc
5
6
Bus Cycle Duration
4 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
6 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
6 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
8 + 2 × (15 - <MCTC>)
+ 2 × (1 - <MTTC>)
57
C167CR
C167SR
Symbol
Limits
min.
max.
1)
tc
CC
30
5
tc
CC 8
6
tc
CC 6
7
tc
CC –
4
8
tc
CC –
4
9
f
> 25 MHz).
CPU
tc
9
tc
8
MCT04415
Unit 25/33 MHz, 0 Waitstates
TCL 80 ns
/ 60.6 ns
TCL 120 ns / 90.9 ns
TCL 120 ns / 90.9 ns
TCL 160 ns / 121.2 ns
V3.2, 2001-07
Unit
ns
ns
ns
ns
ns