HEF4024BDB Philips Semiconductors, HEF4024BDB Datasheet
HEF4024BDB
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HEF4024BDB Summary of contents
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DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4024B MSI 7-stage binary counter Product specification File under Integrated Circuits, IC04 ...
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... Philips Semiconductors 7-stage binary counter DESCRIPTION The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs ( The counter advances on the HIGH to LOW 0 6 transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP ...
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Acrobat reader. white to force landscape pages to be ... Fig.3 Logic diagram. ...
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... Philips Semiconductors 7-stage binary counter AC CHARACTERISTICS pF; input transition times SS amb Propagation delays HIGH to LOW LOW to HIGH HIGH to LOW LOW to HIGH HIGH to LOW 10 15 Output transition times 5 HIGH to LOW LOW to HIGH 10 15 Minimum clock 5 pulse width; HIGH 10 15 Minimum MR 5 pulse width; HIGH ...
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... Philips Semiconductors 7-stage binary counter Dynamic power dissipation per package (P) Fig.4 Waveforms showing propagation delays for and recovery time for MR. January 1995 V DD TYPICAL FORMULA FOR 500 2100 5200 and Product specification where input freq. (MHz output freq. (MHz load cap. (pF) ...