HEF4027BD Philips Semiconductors, HEF4027BD Datasheet
HEF4027BD
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HEF4027BD Summary of contents
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DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4027B flip-flops Dual JK flip-flop Product specification File under Integrated Circuits, IC04 ...
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... PINNING J,K synchronous inputs CP clock input ( edge-triggered) S asynchronous set-direct input (active HIGH asynchronous clear-direct input (active HIGH true output O complement output HEF4027BP(N): HEF4027BD(F): HEF4027BT(D Package Designator North America FAMILY DATA, I See Family Specifications 2 Product specification HEF4027B flip-flops INPUTS OUTPUTS ...
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... Philips Semiconductors Dual JK flip-flop AC CHARACTERISTICS pF; input transition times SS amb Propagation delays HIGH to LOW 10 15 LOW to HIGH LOW to HIGH HIGH to LOW HIGH to LOW 10 15 January 1995 Fig.3 Logic diagram (one flip-flop SYMBOL MIN. TYP. 5 105 t 40 PHL PLH PLH 25 5 120 ...
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... Philips Semiconductors Dual JK flip-fl LOW to HIGH 10 15 Output transition times HIGH to LOW 10 15 LOW to HIGH 10 15 Set-up time J Hold time J Minimum clock pulse width; LOW 10 15 Minimum pulse width; HIGH 10 15 Recovery time for Maximum clock pulse frequency HIGH Dynamic power ...
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... Philips Semiconductors Dual JK flip-flop Fig.4 Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are shown as positive values but may be specified as negative values. Fig.5 Waveforms showing recovery times for S APPLICATION INFORMATION Some examples of applications for the HEF4027B are: ...