UDA1338H Philips Semiconductors, UDA1338H Datasheet
UDA1338H
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UDA1338H Summary of contents
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... DATA SHEET UDA1338H Multichannel audio coder-decoder Preliminary specification Supersedes data of 2002 May 23 INTEGRATED CIRCUITS 2002 Nov 21 ...
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... C-bus 2 Preliminary specification UDA1338H REGISTER MAPPING Address mapping Register mapping System settings Audio ADC and DAC subsystem settings Voice ADC system settings Status output register (read only) DAC channel selection DAC features settings DAC channel settings DAC mixing channel settings ...
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... Excellently suitable for multichannel home audio-video application. 3 GENERAL DESCRIPTION 2 S-bus, The UDA1338H is a single-chip consisting of 4 plus 1 analog-to-digital converters and 6 digital-to-analog converters with signal processing features employing bitstream conversion techniques. The multichannel configuration makes the device eminently suitable for use in digital audio equipment which incorporates surround feature ...
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... A-weighted code = 0; A-weighted at 0 dBFS digital input at 0 dBFS at 60 dBFS; A-weighted code = 0; A-weighted at 0 dBFS digital input at 0 dBFS at 60 dBFS; A-weighted code = 0; A-weighted 4 Preliminary specification UDA1338H ); unless SS MIN. TYP. MAX. UNIT 2.7 3.3 3.6 V 2.7 3.3 3 ...
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... I S-BUS INTERFACE 2 L3-BUS C-BUS CONTROL INTERFACE VOLUME, MUTE, DE-EMPHASIS INTERPOLATION FILTER UDA1338H NOISE SHAPER DAC 1 DAC 3 DAC DDA(DA) V SSA(DA) Fig.1 Block diagram. 5 Preliminary specification UDA1338H V ADCP V ADCN V ref ADC 1R PGA VINR1 8 ADC 2R PGA VINR2 11 TEST TEST 19 CLOCK SYSCLK 13 DATAAD1 12 ...
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... AIO C-bus DAC mute DGND DI DID 2 C-bus SCL input DIO DIS 2 C-bus SDA DO DS IIC 6 Preliminary specification UDA1338H (1) PIN TYPE DESCRIPTION 29 DS digital supply voltage 30 DI selection input for L3-bus C-bus control 31 AIO DAC 1 positive output 32 AIO DAC 1 negative output 33 ...
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... V ref 1 VINL1 2 V SSA(AD) 3 VINR1 4 V DDA(AD) 5 VINL2 6 V ADCN 7 VINR2 8 V ADCP 9 VVOICE 10 TEST 11 2002 Nov 21 UDA1338H Fig.2 Pin configuration. 7 Preliminary specification UDA1338H 33 VOUT2P 32 VOUT1N 31 VOUT1P 30 I2C_L3 29 V DDD 28 V SSD 27 DATADA3 26 DATADA2 25 DATADA1 24 BCKDA 23 WSDA MGU583 ...
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... FUNCTIONAL DESCRIPTION 8.1 System clock The UDA1338H operates in slave mode only; this means that in all applications the system must provide either the system clock (the bit clock for the voice ADC) or the word clock. The audio ADC part, the voice ADC part and the DAC part ...
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... Philips Semiconductors Multichannel audio coder-decoder 8.2 Audio analog-to-digital converter (audio ADC) The audio analog-to-digital front-end of the UDA1338H consists of 4-channel single-ended Adds with programmable gain stage (from with 3 dB steps), controlled via the microcontroller interface. Using the PGA feature possible to accept an input signal of 900 mV (RMS ...
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... Philips Semiconductors Multichannel audio coder-decoder 8.8 Digital mixer The UDA1338H has 6 digital mixers inside the interpolator (see Fig.4). The ADC signals can be mixed with the I input signals. The mixing of the ADC signals can be selected by the bits MIX[1:0]. MIX [ 1:0 ] handbook, full pagewidth ...
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... S-bus format with data word length bits. The left and the right channels contain the same data. Mono channel format with data word length bits. The formats are illustrated in Fig. MGU586 11 Preliminary specification UDA1338H Audio digital interface Voice digital interface ...
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Acrobat reader. white to force landscape pages to be ... LEFT BCK DATA MSB B2 MSB 2 ...
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Acrobat reader. white to force landscape pages to be ... BCK DATA MSB LSB MSB LSB CH1 CH3 ...
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... BCK DATA MSB B2 8.13 DSD mode The UDA1338H can receive 2.8224 MHz DSD signals and generate 88.2 kHz multibit PCM signals as well as analog signal outputs. The configuration of the UDA1338H in the DSD mode is shown in Fig.10. DATADA2 left channel 2.8224 MHz DSD DATADA3 ...
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... The device address consists of one byte with: SDA Data Operating Mode (DOM) bits 0 and 1 representing QMUTE the type of data transfer (see Table 8) Address bits representing a 6-bit device address. The address of the UDA1338H is 01 0100 (bits 2 to 7). Table 10 Selection of data transfer DOM BIT ...
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Acrobat reader. white to force landscape pages to be ... L3CLOCK L3MODE device address L3DATA 0 1 DOM bits L3CLOCK L3MODE device address register ...
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... D15 being the MSB. information in binary format, with bit D0 being the LSB. LATEST IN TIME BIT 2 BIT 3 BIT 4 BIT D13 D12 D11 D10 LATEST IN TIME BIT 2 BIT 3 BIT 4 BIT D13 D12 D11 D10 UDA1338H BIT 6 BIT BIT 6 BIT ...
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... C-bus mode, the DAC mute function is accessible via pin MCMODE with signal QMUTE. The exchange of data and control information between the microcontroller and the UDA1338H is accomplished through a serial hardware interface comprising the following pins as shown in Table 8: MCCLK: clock line with signal SCL MCDATA: data line with signal SDA ...
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... In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. Fig.14 START and STOP conditions on the START condition Fig.15 Acknowledge on the I 19 Preliminary specification UDA1338H SDA SCL P STOP condition MBC622 2 C-bus. not acknowledge acknowledge 8 9 ...
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... Before any data is transmitted on the I which should respond is addressed first. The addressing is always done with byte 1 transmitted after the start procedure. The UDA1338H acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The UDA1338H device address is shown in Table 14 ...
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... The first byte (8 bits) contains the device address ‘0011 000’ and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1338H. 4. After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1338H must start. 5. The UDA1338H acknowledges this register address (A). ...
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... Then the microcontroller generates the device address ‘0011 000’ again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge is followed from the UDA1338H. 8. The UDA1338H sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the microcontroller (master). ...
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... Philips Semiconductors Multichannel audio coder-decoder 11 REGISTER MAPPING In this chapter the register addressing and mapping of the microcontroller interface of the UDA1338H is given. In Table 17 an overview of the register mapping is given. In Table 18 the actual register mapping is given and the register definitions are explained in Sections 11.3 to 11.14. ...
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... Acrobat reader. white to force landscape pages to be ... 11.2 Register mapping Table 18 UDA1338H register mapping; note 1 ADD FUNCTION D15 D14 D13 D12 System settings (2) 00H system RST VFS1 VFS0 ...
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Acrobat reader. white to force landscape pages to be ... ADD FUNCTION D15 D14 D13 D12 18H DAC mixing ICS1 ICS0 channel 1 0 ...
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... DAC power control. A 1-bit value to reduce the power consumption of the DAC. If bit DAP = 1, then the state is power-on; if bit DAP = 0 (default), then the state is power-off. 2002 Nov VFS0 VCE OP0 FS1 FS0 Preliminary specification 11 10 VAP DSD SC1 ACE ADP DCE 1 0 DESCRIPTION UDA1338H 9 8 SC0 DAP ...
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... DAC MODE SYSCLK (128f , 256f , 384f , 512f 768f ) s WSDA ( SYSCLK (128f , 256f , 384f , 512f 768f ) s WSDA ( FUNCTION 12 kHz 50 to 100 kHz 100 to 200 kHz 11 10 MTA AIF2 AIF1 DIS0 DIF2 DIF1 0 0 UDA1338H REMARK default REMARK default AIF0 DIF0 0 0 ...
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... DVD = 0 (default), s rate is selected S-bus format (default) LSB-justified format, 16 bits LSB-justified format, 20 bits LSB-justified format, 24 bits MSB-justified format multichannel format, 20 bits multichannel format, 24 bits (format 1) multichannel format, 24 bits (format 2) 28 Preliminary specification UDA1338H FUNCTION 2 S-bus ...
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... ADC. If bit VIF = 1, then mono-channel format; if bit VIF = 0 (default), then I format. Table 31 BCK frequency of voice ADC bits BCK1 BCK0 2002 Nov WSM VH1 Preliminary specification INPUT TO DAC VH0 PVA MTV 1 0 DESCRIPTION FUNCTION 32f s 64f (default) s 128f s 256f s UDA1338H VIF S-bus ...
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... DAC channel 1 and 2 status. A 1-bit value to indicate the hard mute status of DAC channel 1 and 2. If bit DS0 = 1, then power-down is ready and the clock may be disabled; if bit DS0 = 0, then power-down is not ready and the clock should not be disabled. 2002 Nov 21 (default AS1 30 Preliminary specification FUNCTION AS0 DS2 DS1 DESCRIPTION UDA1338H DS0 ...
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... CS5 CS4 CS3 CS2 2002 Nov MC5 MC4 CS5 CS4 MC1 MC0 CS1 CS0 channel 1 selected : : : channel 2 and channel 4 selected : : : all channels selected 31 Preliminary specification 11 10 MC3 MC2 MC1 CS3 CS2 CS1 0 0 DESCRIPTION FUNCTION FUNCTION UDA1338H 9 8 MC0 CS0 0 0 ...
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... Nov DE2 DE1 VC6 VC5 VC4 dB. Default 0000 0000. See Table 44. INPUT TO DAC OUTPUT 32 Preliminary specification FUNCTION 11 10 DE0 VC3 VC2 VC1 0 0 DESCRIPTION UDA1338H VC0 0 0 ...
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... Nov 21 DE0 0 no de-emphasis (default) 1 de-emphasis of 32 kHz 0 de-emphasis of 44.1 kHz 1 de-emphasis of 48 kHz 0 de-emphasis of 96 kHz 1 not used 0 not used 1 not used VC3 VC2 VC1 VC0 Preliminary specification UDA1338H FUNCTION VOLUME (dB) 0 (default) 0.25 0.50 0.75 1.00 1. ...
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... All the DAC features which are written in register 11H are copied into the even channel registers, except the bits ICS[1:0] and DE[2:0]. 2002 Nov DE2 DE1 VC6 VC5 VC4 DE2 DE1 VC6 VC5 VC4 VC6 VC5 VC4 Preliminary specification UDA1338H DE0 VC3 VC2 VC1 DE0 VC3 VC2 VC1 VC3 VC2 VC1 ...
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... Table 51 Audio ADC input amplifier gain bits IA3 IA2 IB3 IB2 2002 Nov VC6 VC5 VC4 IA1 IA0 IB1 IB0 Preliminary specification VC3 VC2 VC1 IB3 IB2 IB1 IA3 IA2 IA1 0 0 DESCRIPTION GAIN (dB) 0 (default +12 +15 +18 +21 +24 UDA1338H VC0 IB0 IA0 0 0 ...
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... Table 55 Supplemental settings 1 register (address 30H) BIT 15 Symbol Reset default 0 BIT 7 Symbol PDT Reset default 0 2002 Nov IV4 IV2 IV1 IV0 Preliminary specification IV3 IV2 IV1 0 0 DESCRIPTION GAIN (dB) 0 (default) +1.5 +3 +4.5 +6 +7.5 : +28.5 +30 not used not used UDA1338H IV0 ...
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... Nov 21 seconds; if bit PDT = 0 (default), then 512 DITH1 DITH0 dither (mid level); default reserved reserved reserved DC dither (low level) DC plus AC dither (low level) DC dither (high level) DC plus AC dither (high level) 37 Preliminary specification DESCRIPTION VMTP 0 0 DESCRIPTION ); FUNCTION UDA1338H seconds PDLNA 0 0 ...
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... In accordance with the “General specification for integrated circuits (SNW-FQ-611D)” THERMAL CHARACTERISTICS SYMBOL PARAMETER R thermal resistance from junction to ambient th(j-a) 2002 Nov 21 CONDITIONS MIN. note note 2 2000 note 3 200 CONDITIONS in free air 38 Preliminary specification UDA1338H MAX. UNIT 4.0 V 150 C +125 C +85 C +2000 V +200 V VALUE UNIT 85 K/W ...
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... ADC DAC kHz VOICE audio and voice ADCs power-down DAC power-down 2 0.85V with respect to 0.45V V SSA(AD) 0.0 ref 4 39 Preliminary specification UDA1338H MIN. TYP. MAX. 3.3 3.6 3.3 3.6 3.3 3 tbf tbf 0 DDD 0.4 0.5V 0.55V DDA(AD) DDA(AD) ...
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... Preliminary specification UDA1338H = 48 kHz; all voltages s MIN. TYP. MAX. UNIT 2.5 1.2 0.7 dB 1 ...
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... A-weighted setting setting setting setting setting setting setting setting setting code = 0; A-weighted kHz; ripple (p-p) ripple 41 Preliminary specification UDA1338H TYP. MAX. UNIT tbf dB tbf dB tbf dB ...
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... A-weighted code = 0; A-weighted 107 kHz; ripple (p-p) ripple at 0 dBFS digital input at 0 dBFS at 20 dBFS at 60 dBFS; A-weighted code = 0; A-weighted kHz; ripple (p-p) ripple 42 Preliminary specification UDA1338H TYP. MAX. UNIT 50 tbf dB 2.0 2.1 V <0.1 dB 100 93 ...
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... MHz sys f 19.2 MHz sys f < 19.2 MHz sys f 19.2 MHz sys DAC (see Fig.17) note 2 note 2 43 Preliminary specification UDA1338H MIN. TYP 0.3T sys 0.4T sys 0.3T sys 0.4T sys 30 30 ...
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... CONDITIONS MIN. WSV-out mode 30 500 250 250 190 190 190 190 190 190 1.3 0.6 note 0.1C note 0.1C 1.3 0.6 0.6 100 0 0.6 note Preliminary specification UDA1338H TYP. MAX. UNIT +30 ns 2000 kHz 400 kHz s s 300 ns b 300 ...
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... WS t BCKH t r BCK T cy(BCK) DATAO DATAI 2002 Nov 21 t CWL T sys Fig.16 System clock timing. t h(WS su(WS) t BCKL t d(DATAO-WS) 2 Fig.17 I S-bus serial interface timing. 45 Preliminary specification UDA1338H MGR984 t d(DATAO-BCK) t h(DATAO) t su(DATAI) t h(DATAI) MGS756 ...
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... Fig.19 L3-bus data transfer (write and read) mode timing. 2002 Nov 21 t CLK(L3)L t CLK(L3)H t su(L3)A t su(L3)DA t h(L3)DA BIT 0 Fig.18 L3-bus address mode timing. t CLK(L3)L t CLK(L3)H t su(L3)DA t h(L3)DA BIT 0 46 Preliminary specification UDA1338H t su(L3)A t h(L3)A T cy(CLK)(L3) BIT 7 t stp(L3) t h(L3)D T cy(CLK)L3 BIT 7 t dis(L3)R t d(L3)R MGU015 MGL723 ...
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... Philips Semiconductors Multichannel audio coder-decoder handbook, full pagewidth SDA t LOW SCL t HD;STA t HD;DAT S 2002 Nov SU;DAT t SU;STA t HIGH Sr 2 Fig.20 I C-bus timing 47 Preliminary specification UDA1338H t HD;STA BUF t SU;STO P S MSC610 ...
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... Nov 2.5 scale (1) ( 0.40 0.25 10.1 10.1 12.9 0.8 0.20 0.14 9.9 9.9 12.3 REFERENCES JEDEC EIAJ 48 Preliminary specification detail 12.9 0.95 1.3 0.15 0.15 0.1 12.3 0.55 EUROPEAN PROJECTION UDA1338H SOT307 (1) ( 1.2 1 0.8 0.8 0 ISSUE DATE 95-02-04 97-08-01 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 49 Preliminary specification UDA1338H ...
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... Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Nov 21 (1) not suitable not suitable suitable not recommended not recommended 50 Preliminary specification UDA1338H SOLDERING METHOD (2) WAVE REFLOW suitable (3) suitable suitable (4)(5) suitable ...
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... Preliminary specification UDA1338H DEFINITION These products are not Philips Semiconductors ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 2002 Nov 21 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 52 Preliminary specification UDA1338H 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors Multichannel audio coder-decoder 2002 Nov 21 NOTES 53 Preliminary specification UDA1338H ...
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... Philips Semiconductors Multichannel audio coder-decoder 2002 Nov 21 NOTES 54 Preliminary specification UDA1338H ...
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... Philips Semiconductors Multichannel audio coder-decoder 2002 Nov 21 NOTES 55 Preliminary specification UDA1338H ...
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... Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. ...