L640DU12RI Advanced Micro Devices, L640DU12RI Datasheet
L640DU12RI
Specifications of L640DU12RI
Related parts for L640DU12RI
L640DU12RI Summary of contents
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Am29LV640D/Am29LV641D Data Sheet The following document contains information on Spansion memory products. Although the docis marked with the name of the company that originally developed the specification, Spansion will con- tinue to offer these products to existing customers. Continuity of ...
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DATA SHEET Am29LV640D/Am29LV641D 64 Megabit ( 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO™ Control DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — 3.0 to 3.6 volt read, erase, and program operations ■ VersatileIO™ control — ...
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GENERAL DESCRIPTION The Am29LV640DU/Am29LV641DU Mbit, 3.0 Volt (3 3.6 V) single power supply flash memory device organized as 4,194,304 words. Data appears on DQ0-DQ15. The device is designed to be pro- grammed in-system with the ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . ...
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PRODUCT SELECTOR GUIDE Part Number V = 3.0–3 Speed Option V = 3.0–3 Max Access Time (ns) CE# Access Time (ns) OE# Access Time (ns) Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM ...
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CONNECTION DIAGRAMS A15 1 A14 2 A13 3 A12 4 A11 5 A10 A21 A20 10 WE# 11 RESET# 12 ACC 13 WP# 14 A19 15 A18 16 A17 ...
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CONNECTION DIAGRAM A13 A12 WE# RESET RY/BY# ACC A17 NC Balls ...
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CONNECTION DIAGRAMS A8 B8 RFU RFU A7 B7 A13 A12 WE# RESET RY/BY# ACC A17 RFU RFU Special Handling Instructions for FBGA/fBGA Packages ...
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PIN DESCRIPTION A0–A21 = 22 Addresses inputs DQ0–DQ15 = 16 Data inputs/outputs CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input WP# = Hardware Write Protect input (N/A on FBGA) ACC = Acceleration Input ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29LV640D Am29LV641D H 90R E DEVICE NUMBER/DESCRIPTION Am29LV640DU/DH/DL, Am29LV641DH/DL 64 Megabit (4 ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch ...
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The device remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” on page 10 for more infor mation. Refer to the AC “Read-Only Operations” on ...
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The RESET# pin can be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during ...
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Table 2. Sector Address Table (Sheet Sector A21 A20 SA26 0 0 SA27 0 0 SA28 0 0 SA29 0 0 SA30 0 0 SA31 0 0 SA32 0 1 SA33 0 1 SA34 0 1 SA35 ...
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Table 2. Sector Address Table (Sheet Sector A21 A20 SA61 0 1 SA62 0 1 SA63 0 1 SA64 1 0 SA65 1 0 SA66 1 0 SA67 1 0 SA68 1 0 SA69 1 0 SA70 ...
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Table 2. Sector Address Table (Sheet Sector A21 A20 SA96 1 1 SA97 1 1 SA98 1 1 SA99 1 1 SA100 1 1 SA101 1 1 SA102 1 1 SA103 1 1 SA104 1 1 SA105 ...
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Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with ...
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Sector Group Protection and Unprotection The hardware sector group protection feature disables both program and erase operations in any sector group. In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same ...
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Write Protect (WP#) The Write Protect function provides a hardware method of protecting the first or last sector without using the system asserts V on the WP# pin, the device IL disables program and erase functions ...
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START PLSCNT = 1 RESET Wait 1 μs Temporary Sector No First Write Group Unprotect Cycle = 60h? Mode Yes Set up sector group address Sector Group Protect: Write 60h to sector group address with A6 = ...
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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 128 words in length, and uses a ...
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Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE#, do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE CE# = ...
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Addresses (x16) Data 1Bh 0027h 1Ch 0036h 1Dh 0000h 1Eh 0000h 1Fh 0004h 20h 0000h 21h 000Ah 22h 0000h 23h 0005h 24h 0000h 25h 0004h 26h 0000h Addresses (x16) Data 27h 0017h 28h 0001h 29h 0000h 2Ah 0000h 2Bh 0000h ...
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Table 9. Primary Vendor-Specific Extended Query Addresses (x16) Data 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 0000h 46h 0002h 47h 0004h 48h 0001h 49h 0004h 4Ah 0000h 4Bh 0000h 4Ch 0000h 4Dh 00B5h 4Eh 00C5h 4Fh ...
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The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase op- eration the device is in the autoselect mode. See the ...
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Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device returns to the read mode, to ...
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When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write ...
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Refer to “Write Operation Status” on page 29 tion. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to “Autoselect Mode” on page 16 and mand Sequence” on ...
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Command Definitions Command Sequence Addr Read (Note Reset (Note 6) 1 XXX Manufacturer ID 4 555 Device ID 4 555 SecSi™ Sector Factory 6 555 Protect (Note 8) Sector Group Protect Verify 4 555 (Note 9) Enter ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 11 on page 32 and the following subsections describe the function of these bits. DQ7 ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied ...
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DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description I Input Load Current (Note LI I A9, ACC Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write ...
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DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6.2 kΩ L Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Note < ...
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AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output Delay GLQV ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
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AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std. Description t t Write Cycle Time AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t t Address Hold ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data Illustration shows device in word ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE Data 55h RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid ...
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AC CHARACTERISTICS t RC Addresses VA t ACC OE# t OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read ...
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AC CHARACTERISTICS Addresses CE# t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read ...
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AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR ID RESET# Setup Time for Temporary Sector t RSP Unprotect RESET# Hold Time from RY/BY# High for t RRB Temporary Sector Group ...
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AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector Group Protect or Unprotect Data 60h 1 µs CE# WE# OE# * For sector group protect For sector group ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup Time DVEH ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Word Program Time Chip Program Time (Note 3) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3 programming typicals ...
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PHYSICAL DIMENSIONS SSO056—56-Pin Shrink Small Outline Package (SSOP) January 22, 2007 22366C6 Am29LV640D/Am29LV641D Dwg rev AB; 10/99 49 ...
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PHYSICAL DIMENSIONS FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA package Am29LV640D/Am29LV641D Dwg rev AF; 10/99 22366C6 January 22, 2007 ...
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PHYSICAL DIMENSIONS LAA064—64-Ball Fortified Ball Grid Array ( January 22, 2007 22366C6 BGA package Am29LV640D/Am29LV641D 51 ...
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PHYSICAL DIMENSIONS TS 048—48-Pin Standard TSOP Note: For reference only. BSC is an ANSI standard for Basic Space Centering. * For reference only. BSC is an ANSI standard for Basic Space Centering ...
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REVISION SUMMARY Revision A (April 26, 1999) Initial release. Revision A+1 (May 4, 1999) Global Deleted references to the 4-word unique ESN. Re- placed references to V with V . CCQ IO Connection Diagrams 63-ball FBGA: Corrected signal for ball ...
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Test Conditions Test Conditions table: Redefined output timing mea- surement reference level as 0 Added note to table and figure. Erase and Program Operations table, Alternate CE# Controlled Erase and Program Operations table, Erase and Programming Performance table ...
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... Copyright © 1999–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...