ADSP-2161 Analog Devices, ADSP-2161 Datasheet
ADSP-2161
Specifications of ADSP-2161
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ADSP-2161 Summary of contents
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... ROM and data memory RAM, a programmable timer and two serial ports. The ADSP-2165/ADSP-2166 also adds program memory and power-down mode. This data sheet describes the following ADSP-216x Family processors: ADSP-2161/ADSP-2162/ ADSP-2163/ADSP-2164 Custom ROM-programmed DSPs: ADSP-2165/ADSP-2166 ROM-programmed ADSP-216x processors with power-down and ...
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... POWER DISSIPATION EXAMPLE . . . . . . . . . . . . . . . . . 19 ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 19 CAPACITIVE LOADING . . . . . . . . . . . . . . . . . . . . . . . . . 19 TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1 Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1 Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1 TIMING PARAMETERS 3 (ADSP-2161/ADSP-2163/ADSP-2165 GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MEMORY REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . 21 CLOCK SIGNALS AND RESET . . . . . . . . . . . . . . . . . . . 22 INTERRUPTS AND FLAGS . . . . . . . . . . . . . . . . . . . . . . 23 BUS REQUEST/BUS GRANT . . . . . . . . . . . . . . . . . . . . . 24 MEMORY READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MEMORY WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SERIAL PORTS ...
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... ARCHITECTURE OVERVIEW Figure 1 shows a block diagram of the ADSP-216x architecture. The processors contain three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations ...
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... There is also a master RESET signal. Booting circuitry provides for loading on-chip program memory automatically from byte-wide external memory. After reset, three wait states are automatically generated. This allows, for example ADSP-2161 to use a 200 ns EPROM as PROGRAM DATA REGISTER MEMORY ...
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... Pin Function Descriptions show pin definitions for the ADSP- 216x processors. Any inputs not used must be tied to V SYSTEM INTERFACE Figure 3 shows a typical system for the ADSP-216x with two serial I/O devices, an optional external program and data memory. A total of 12K words of data memory and 15K words of program memory is addressable ...
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... A clock output signal (CLKOUT) is generated by the processor, synchronized to the processor’s internal cycles. Reset The RESET signal initiates a complete reset of the ADSP-216x. The RESET signal must be asserted when the chip is powered up to assure proper initialization. If the RESET signal is applied during initial power-up, it must be held long enough to allow the processor’ ...
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... Program Memory Maps Program memory can be mapped in two ways, depending on the state of the MMAP pin. Figure 4 shows the program memory map for the ADSP-2165/ADSP-2166. Figures 5 and 6 show the program memory maps for the ADSP-2161/ADSP-2162 and ADSP-2163/ADSP-2164, respectively. REV. 0 ADSP-2165/ADSP-2166 When MMAP = 0, on-chip program memory ROM occupies 12K words beginning at address 0x0000 ...
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... ROM 0x0FF0 0x0FFF 0x1000 Figure 7. ADSP-2165/ADSP-2166 Data Memory Map 10K ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164 For the ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164, on- 0x37FF chip data memory RAM resides in the 512 words beginning at 0x3800 2K address 0x3800, also shown in Figure 8. Data memory locations ROM from 0x3A00 to the end of data memory at 0x3FFF are reserved. ...
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... Three-stating the data and address buses and the PMS, DMS, BMS, RD, WR output drivers, • Asserting the bus grant (BG) signal, and halting program execution. If the Go mode is set, however, the ADSP-216x will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-216x is performing an external memory access ...
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... This can be overcome by locating program memory data in on-chip memory. Ordering Procedure for ADSP-216x ROM Processors To place an order for a custom ROM-coded ADSP-2161, ADSP-2162, ADSP-2163, ADSP-2164 , ADSP-2165 or ADSP- 2166 processor, you must: 1. Complete the following forms contained in the ADSP ROM ...
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... Instruction Set The ADSP-216x assembly language uses an algebraic syntax for ease of coding and readability. The sources and destinations of computations and data movements are written explicitly in each assembly statement, eliminating cryptic assembler mnemonics. Every instruction assembles into a single 24-bit word and executes in a single cycle ...
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... ADSP-216x Program Flow Instructions DO <addr> [UNTIL term] ; [IF cond] JUMP (Ix) ; [IF cond] JUMP <addr>; [IF cond] CALL (Ix) ; [IF cond] CALL <addr>; IF [NOT ] FLAG_IN JUMP <addr>; IF [NOT ] FLAG_IN CALL <addr>; [IF cond] SET|RESET|TOGGLE [IF cond] RTS ; [IF cond] RTI ; IDLE [(n)] ; Miscellaneous Instructions NOP ; MODIFY (Ix , My); [PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ; ...
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... SPECIFICATIONS ADSP-2161/ADSP-2163/ADSP-2165–RECOMMENDED OPERATING CONDITIONS Parameter V Supply Voltage DD T Ambient Operating Temperature AMB See “Environmental Conditions” for information on thermal specifications. ELECTRICAL CHARACTERISTICS Parameter Hi-Level Input Voltage IH V Hi-Level CLKIN and Reset Voltage Lo-Level Input Voltage Hi-Level Output Voltage Lo-Level Output Voltage ...
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... FREQUENCY – MHz VALID FOR ALL TEMPERATURE GRADES. 1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2 IDLE REFERS TO ADSP-216x OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V 3 MAXIMUM POWER DISSIPATION AT V Figure 9. ADSP-2161/ADSP-2163/ADSP-2165 (Typical) vs. Frequency Test Conditions max ...
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... load capacitance output switching frequency. Example ADSP-2161 application where external data memory is used and no other outputs are active, power dissipation is calcu- lated as follows: Assumptions: • External data memory is accessed every cycle with 50% of the address pins switching. • External data memory writes occur every other cycle with 50% of the data pins switching. • ...
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... ADSP-216x SPECIFICATIONS ADSP-2161/ADSP-2163/ADSP-2165 TEST CONDITIONS Figure 12 shows voltage reference levels for ac measurements. INPUT OUTPUT Figure 12. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured out- put high or low voltage to a high impedance state ...
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... Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0 All ADSP-2162, ADSP-2164 and ADSP-2166 outputs are CMOS and will drive to V Three-stateable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RFS1, TFS1, DT0, SCLK0, RFS0, TFS0 BR, CLKIN Active (to force three-state condition). ...
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... Supply Current (Idle) DD NOTES 1 Current reflects device operating with no output loads 0.4 V and 2 Idle refers to ADSP-216x state of operation during execution of IDLE instruction. Deasserted pins are driven to either V For typical supply current (internal power dissipation) figures, see Figure 15. Specifications subject to change without notice 9mW 8 6 ...
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... load capacitance output switching frequency. Example ADSP-2162 application where external data memory is used and no other outputs are active, power dissipation is calcu- lated as follows: Assumptions: • External data memory is accessed every cycle with 50% of the address pins switching. • External data memory writes occur every other cycle with 50% of the data pins switching. • ...
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... ADSP-216x SPECIFICATIONS ADSP-2162/ADSP-2164/ADSP-2166 TEST CONDITIONS Figure 18 shows voltage reference levels for ac measurements. INPUT OUTPUT Figure 18. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state ...
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... TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165) GENERAL NOTES Use the exact timing information given. Do not attempt to de- rive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect sta- tistical variations and worst cases. Consequently, you cannot meaningfully add parameters to derive longer times ...
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... ADSP-216x TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165) CLOCK SIGNALS AND RESET Parameter Timing Requirements: t CLKIN Period CK t CLKIN Width Low CKL t CLKIN Width High CKH RESET Width Low t RSP Switching Characteristics: t CLKOUT Width Low CPL t CLKOUT Width High CPH t CLKIN High to CLKOUT High CKOH ...
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... TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165) INTERRUPTS AND FLAGS Parameter Timing Requirements: IRQx Setup Before IFS 2, 3 CLKOUT Low IRQx Setup Before IFS 2, 3 CLKOUT Low IRQx Hold After CLKOUT IFH 2, 3 High Switching Characteristics Hold After CLKOUT High FOH t FO Delay from CLKOUT High ...
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... ADSP-216x TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165) BUS REQUEST/BUS GRANT Parameter Timing Requirements: BR Hold After CLKOUT High Setup Before CLKOUT Low t BS Switching Characteristics: CLKOUT High to DMS PMS, BMS, RD, WR Disable DMS, PMS, BMS, RD SDB Disable to BG Low BG High to DMS, PMS BMS, RD, WR Enable ...
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... TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165) MEMORY READ Parameter Timing Requirements: RD Low to Data Valid t RDD A0–A13, PMS, DMS, BMS to Data Valid t AA Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD A0–A13, PMS, DMS, BMS Setup Before RD Low t ASR A0– ...
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... ADSP-216x TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165) MEMORY WRITE Parameter Switching Characteristics: Data Setup Before WR High t DW Data Hold After WR High Pulsewidth Low to Data Enabled t WDE A0–A13, DMS, PMS Setup Before WR Low t ASW Data Disable Before Low t DDR CLKOUT High to WR Low t CWR A0–A13, DMS, PMS, Setup Before WR Deasserted ...
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... TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165) SERIAL PORTS Parameter Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup Before SCLK Low SCS t DR/TFS/RFS Hold After SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid ...
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... Timing requirements guarantee that the processor operates correctly with other devices. MEMORY REQUIREMENTS The table below shows common memory device specifications and the corresponding ADSP-216x timing parameters, for your convenience. ADSP-216x Timing Parameter Timing Parameter Definition A0– ...
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... TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166) CLOCK SIGNALS AND RESET Parameter Timing Requirements: t CLKIN Period CK t CLKIN Width Low CKL t CLKIN Width High CKH RESET Width Low t RSP Switching Characteristics: t CLKOUT Width Low CPL t CLKOUT Width High CPH t CLKIN High to CLKOUT High CKOH NOTE 1 Applies after power-up sequence is complete ...
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... IFS IFH following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual, Third Edition, for further information on interrupt servicing.) 3 Edge-sensitive interrupts require pulse widths greater than 10 ns ...
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... Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual, Third Edition, states that, “When BR is recognized, the processor responds immedi- ately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors asserted in the cycle after BR is recognized. ...
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... ADSP-216x TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166) MEMORY READ Parameter Timing Requirements: RD Low to Data Valid t RDD A0–A13, PMS, DMS, BMS Data Valid Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD A0–A13, PMS, DMS, BMS t ASR Setup Before RD Low A0– ...
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... TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166) MEMORY WRITE Parameter Switching Characteristics: Data Setup Before WR High t DW Data Hold After WR High Pulsewidth Low to Data Enabled t WDE A0–A13, DMS, DMS Setup t ASW Before WR Low Data Disable Before WR t DDR or RD Low CLKOUT High to WR Low t CWR A0– ...
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... ADSP-216x TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166) SERIAL PORTS Parameter Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup SCS Before SCLK Low t DR/TFS/RFS Hold After SCH SCLK Low t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC OUT t SCLK High to DT Enable SCDE t SCLK High to DT Valid ...
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... Scale) IRQ2 PLCC Pin Number Name BR 35 IRQ2 36 RESET GND A10 51 A11 –35– ADSP-216x SCLK1 IRQ0 IRQ1 SCLK0 DR0 50 49 GND RFS0 48 TFS0 47 DT0 Pin PLCC Pin Name Number Name A12 52 FO IRQ1 A13 53 PMS IRQ0 54 DMS 55 FI BMS 56 SCLK1 ...
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... A10 28 9 A11 29 10 A12 30 11 A13 31 PMS 12 32 DMS 13 33 BMS XTAL 36 17 CLKIN 37 18 PWDACK PWDFLAG *ADSP-2165/ADSP-2166 only. Others “NC”. PIN CONFIGURATIONS 80-Lead MQFP 1 PIN 1 2 IDENTIFIER ADSP-216x 10 TOP VIEW 11 (Not to Scale Pin MQFP Name Number CLKOUT DT0 ...
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... REV. 0 OUTLINE DIMENSIONS ADSP-216x 68-Lead Plastic Leaded Chip Carrier (PLCC) 0.175 (4.45) 0.169 (4.29 0.050 (1.27) TYP 0.925 (23.50) 0.895 (22.73) 0.019 (0.48) 0.017 (0.43) 0.029 (0.74) 0.027 (0.69 0.104 (2.64) TYP –37– ADSP-216x PIN 1 IDENTIFIER BOTTOM VIEW (PINS UP) ...
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... ADSP-216x 0.041 (1.03) 0.031 (0.78) OUTLINE DIMENSIONS ADSP-216x 80-Lead Plastic Quad Flatpack (MQFP) 0.690 (17.45) 0.667 (16.95) 0.134 (3.40) 0.555 (14.10) MAX 0.547 (13.90) 0.486 (12.35) BSC 80 1 SEATING PLANE TOP VIEW (PINS DOWN) 0.004 (0.10 MAX 0.010 (0.25) 0.014 (0.35) MIN 0 ...
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... Ambient Temperature 1 Part Number Range 2 ADSP-2161KP-66 2 ADSP-2161BP-66 2 ADSP-2161KS-66 2 ADSP-2161BS-66 2 ADSP-2162KP-40 (3 ADSP-2162BP-40 (3 ADSP-2162KS-40 (3 ADSP-2163KP-66 2 ADSP-2163BP-66 2 ADSP-2163KS-66 2 ADSP-2163BS-66 2 ADSP-2163KP-100 2 ADSP-2163BP-100 2 ADSP-2163KS-100 2 ADSP-2163BS-100 2 ADSP-2164KP-40 (3 ADSP-2164BP-40 (3 ADSP-2164KS-40 (3 ADSP-2164BS-40 (3.3 V) ADSP-2165KS-80 ADSP-2165KS-100 ADSP-2165BS-80 ADSP-2165BS-100 ADSP-2166KS-52 (3.3 V) ADSP-2166KS-66 (3.3 V) ADSP-2166BS-52 (3.3 V) ADSP-2166BS-66 (3.3 V) NOTES Commercial Temperature Range ( +70 C). ...