IDT709279 Integrated Device Technology, Inc., IDT709279 Datasheet
IDT709279
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IDT709279 Summary of contents
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... True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 9/12/15ns (max.) – Industrial: 12ns (max.) Low-power operation – IDT709279S Active: 950mW (typ.) Standby: 5mW (typ.) – IDT709279L Active: 950mW (typ.) Standby: 1mW (typ.) ...
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... This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Industrial and Commercial Temperature Ranges With an input data register, the IDT709279 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’ ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM Left Port Right Port Chip Enables R/W R/W Read/Write Enable Output Enable Address 0L 14L 0R 14R I/O - I/O I/O - I/O Data Input/Output 0L 15L 0R 15R CLK CLK Clock Upper Byte Select Lower Byte Select L R ADS ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM Previous Addr Address Address Used CLK NOTES: 1. "H" "L" "X" = Don't Care. IH, IL LB, UB, and and R Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE 5 ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL V Output High Voltage OH NOTE Vcc < 2.0V input leakages are undefined. Symbol Parameter CE I Dynamic Operating CC L Current Outputs Disabled (Both Ports Active) ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT 347 Figure 1. AC Output Test load. , tCD 1 tCD 2 (Typical, ns) Figure 3. Typical Output Derating (Lumped Capacitive Load). ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM Symbol t Clo ck Cycle Tim e (Flo w-Thro ug h) CYC1 (2) t Clo ck Cycle Tim line d ) CYC2 (2) t Clo ck Hig h Tim e (Flo w-Thro ug h) CH1 (2) t Clo Tim e (Flo w-Thro ug h) CL1 (2) t Clo ck Hig h Tim lined ) ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM FT t CH1 CLK UB (5) ADDRESS An DATA OUT (1) t CKLZ ( CH2 CLK UB (5) ADDRESS An (1 Latency) DATA OUT (2) OE NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). ...
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... ADDRESS 0 (B2) CE 0(B2 DATA OUT(B2) NOTES Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709279 for this waveform, and are setup for depth expansion in this example. ADDRESS = ADDRESS in this situation. (B1) (B2) 2. UB, LB, OE, and ADS = V , R/W, CNTEN, and CNTRST = 1(B1) 1(B2) 3 ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM CLK "A" R/W "A" ADDRESS "A" MATCH DATA VALID IN "A" CLK "B" R/W "B" ADDRESS MATCH "B" DATA OUT "B" NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM t CYC2 t t CH2 CLK UB (4) An ADDRESS DATA IN (2) DATA OUT READ t CYC2 t t CH2 CL2 CLK UB (4) An ADDRESS DATA IN (2) DATA OUT OE READ NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM t CYC1 t CH1 CLK UB (4) An ADDRESS DATA IN t CD1 (2) DATA OUT t CYC1 t CH1 CLK UB (4) An ADDRESS DATA IN t CD1 (2) DATA OUT OE READ NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM t CYC2 t t CH2 CL2 CLK ADDRESS SAD HAD ADS CNTEN (2) DATA OUT READ EXTERNAL ADDRESS t CYC1 t t CH1 CLK ADDRESS t t SAD HAD ADS CNTEN t CD1 (2) Qx DATA OUT t DC READ EXTERNAL ADDRESS NOTES: 1 ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM t CYC2 t CH2 CLK ADDRESS An (3) INTERNAL An ADDRESS t t SAD HAD ADS CNTEN DATA IN WRITE EXTERNAL ADDRESS t CYC2 t t CH2 CL2 CLK ADDRESS (3) INTERNAL (6) Ax ADDRESS R/W ADS CNTEN t t SRST HRST CNTRST DATA ...
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... IDT709279 Control Inputs IDT709279 Control Inputs The IDT709279 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM IDT XXXXX A 99 Device Power Speed Type NOTES: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. Old Flow-through Part A A Package Process/ Temperature Range Blank I ( 709279 512K (32K x 16-Bit) Synchronous Dual-Port RAM ...
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... IDT709279S/L High-Speed 32K x 16 Synchronous Dual-Port Static RAM 12/9/98: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Pages 13 & 14 Updated timing waveforms Page 15 Added Depth and Width Expansion section 6/3/99 Changed drawing format ...