IDT72841 Integrated Device Technology, Inc., IDT72841 Datasheet
IDT72841
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IDT72841 Summary of contents
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... The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs Offers optimal combination of large capacity, high speed, ...
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IDT72801/728211/72821/72831/72841/72851 WENA2/LDA WCLKA WENA1 RSA Commercial And Industrial Temperature Range ...
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IDT72801/728211/72821/72831/72841/72851 The IDT72801/72811/72821/72831/72841/72851s two FIFOs, referred to as FIFO A and FIFO B, are identical in every respect. The following Symbol Name I/O DA0-DA8 A Data Inputs I DB0-DB8 B Data Inputs I RSA RSB , Reset I WCLKA Write ...
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... Commercial And Industrial Temperature Range Symbol Com'l & Ind'l Unit V CC –0.5 to +7.0 V GND –55 to +125 C – ± 10 IDT72801 IDT72811 IDT72821 IDT72831 IDT72841 Commercial and Industrial t = 10, 15 CLK Min. Typ. –1 –10 = – — — — Max. Unit = OUT 4 Parameter Min. ...
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... GND to 3.0V 3ns 1.5V 1.5V See Figure 1 5 Com'l & (1) Ind'l IDT72801L25 IDT72811L25 IDT72821L25 IDT72831L25 IDT72841L25 IDT72851L25 Max. Min Max. Unit 66.7 — 40 MHz — 25 — ns — 10 — ns — 10 — ns — ...
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IDT72801/728211/72821/72831/72841/72851 FIFO A and FIFO B are identical in every respect. The following description explains the interaction of input and output signals for FIFO A. The correspond- ing signal names for FIFO B are provided in parentheses. — Data In ...
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... LOW after 256 writes to the IDT72801's FIFO A (B); 512 writes to the IDT72811's FIFO A (B); 1,024 writes to the IDT72821's FIFO A (B); 2,048 writes to the IDT72831's FIFO A (B); 4,096 writes to the IDT72841's FIFO A (B); or 8,192 writes to the IDT72851's FIFO A (B). FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of the Write Clock WCLKA (WCLKB). Empty Flag (EFA, EFB) — ...
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... IDT72801's FIFO A (B); (512-m) writes to the IDT72811's FIFO A (B); (1,024-m) writes to the IDT72821's FIFO A (B); (2,048-m) writes to the IDT72831's FIFO A (B); (4,096-m) writes to the IDT72841's FIFO A (B); or (8,192-m) writes to the IDT72851's FIFO A (B). FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of the Write Clock WCLKA (WCLKB). The offset “ ...
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IDT72801/728211/72821/72831/72841/72851 RSA (RSB) RENA1, RENA2 (RENB1, RENB2) WENA1 (WENB1) (1) WENA2/LDA (WENB2/LDB) EFA, PAEA (EFB, PAEB) FFA, PAFA (FFB, PAFB ( NOTES: 1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will ...
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IDT72801/728211/72821/72831/72841/72851 RCLKA (RCLKB) t ENS RENA1, RENA2 (RENB1, RENB2) EFA (EFB ( OEA (OEB) WCLKA (WCLKB) WENA1 (WENB1) WENA2 (WENB2) NOTE: is the minimum time between a rising WCLKA (WCLKB) ...
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IDT72801/728211/72821/72831/72841/72851 NO WRITE WCLKA (WCLKB) t SKEW1 ( FFA (FFB) WENA1 (WENB1) WENA2 (WENB2) (If Applicable) RCLKA (RCLKB) t ENH t ENS RENA1 (RENB2) OEA LOW (OEB ...
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... NOTES PAF offset. 2. (256-m) words for the IDT72801; (512-m) words the IDT72811; (1,024-m) words for the IDT72821; (2,048-m) words for the IDT72831; (4,096-m) words for the IDT72841; or (8,192-m) words for the IDT72851. is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between the 3 ...
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IDT72801/728211/72821/72831/72841/72851 t CLK WCLKA (WCLKB) LDA (LDB) WENA1 (WENB1 ( PAE OFFSET (LSB) t CLK t CLKH RCLKA (RCLKB) t LDA (LDB) t ENS RENA1, RENA2 (RENB1, RENB2 ...
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IDT72801/728211/72821/72831/72841/72851 SINGLE DEVICE CONFIGURATION — When FIFO A ( Single Device Configuration, the Read Enable 2 RENA2 (RENB2) control input WENA1 (WENB1) WENA2/LDA (WENB2/LDB Figure 14. Block Diagram of One of the IDT72801/72811/72821/72831/72841/72851's two FIFOs ...
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IDT72801/728211/72821/72831/72841/72851 The two FIFOs contained in the IDT72801/72811/72821/72831/72841/ 72851 can be used to prioritize two different types of data shared on a system bus. When writing from the bus to the FIFO, control logic sorts the intermixed Processor Clock Address ...
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... Stender Way Santa Clara, CA 95054 The SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. access from one device to the next in a sequential manner. These FIFOs operate in the Depth Expansion configuration when the following conditions are met: 1 ...