ISP1362 Philips Semiconductors, ISP1362 Datasheet
ISP1362
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ISP1362 Summary of contents
Page 1
... Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be hardware configured to function as a downstream port, an upstream port or an OTG port whereas port 2 can only be used as a downstream port ...
Page 2
... Supports endpoints with double buffering to increase throughput and ease real-time data transfer Supports controllable LazyClock (110 kHz 50%) output during ‘suspend’ Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller BUS © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 3
... Operating temperature range from Available in 64-pin LQFP and TFBGA packages. 3. Applications The ISP1362 can be used to implement a dual-role USB device in any application—USB host or USB peripheral—depending on the cable connection. If the dual-role device is connected to a typical USB peripheral, it behaves like a typical USB host. However, the dual-role device can also be connected any other USB host and behave like a typical USB peripheral ...
Page 4
... Mass storage: upload/download files Global Positioning System (GPS): obtain directions, mapping information Digital still camera: upload pictures Oscilloscope: configure oscilloscope. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Version SOT314-2 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 5
... MEMORY to system clock ADVANCED PHILIPS SLAVE HOST CONTROLLER ON-THE-GO CONTROLLER PHILIPS DEVICE CONTROLLER DC BUFFER GOODLINK MEMORY 4, 14, 26, 40, 52 D_SUSPEND D_WAKEUP OTGMODE CLKOUT 38 ISP1362 56 V DD_5V 35 H_PSW1 OVERCURRENT 36 H_PSW2 PROTECTION 42 H_OC1 41 H_OC2 46 H_DM2 USB 47 TRANSCEIVER H_DP2 49 OTG_PM1 OTG 50 TRANSCEIVER OTG_DP1 CHARGE 55 ...
Page 6
... DGND D10 13 D11 D12 15 D13 16 Fig 2. Pin configuration LQFP64. 9397 750 10767 Product data ISP1362BD Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller H_DP2 46 H_DM2 45 OTGMODE H_OC1 41 H_OC2 CLKOUT 37 DGND 36 H_PSW2 35 H_PSW1 34 D_SUSPEND/D_WAKEUP 33 H_SUSPEND/H_WAKEUP 004aaa050 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 7
... Philips Semiconductors Fig 3. Pin configuration TFBGA64. 9397 750 10767 Product data 004aaa151 ISP1362EE Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 8
... I/O bit 11 of the bidirectional data bus that connects to the push-pull input, internal registers and buffer memory of the ISP1362; three-state output the bus is in the high-impedance state when it is idle - - supply voltage (3.3 V) ...
Page 9
... Product data Pad Type Description bidirectional, I/O bit 15 of the bidirectional data bus that connects to the push-pull input, internal registers and buffer memory of the ISP1362; three-state output the bus is in the high-impedance state when it is idle - - digital ground input with I read strobe input ...
Page 10
... I overcurrent sense input for downstream port 2; both the digital and analog overcurrent inputs can be used for port 2, depending on the hardware mode register setting Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller details for details is used for BUS to the downstream port ...
Page 11
... V) bidirectional, I/O for test input and output, pulled to 0 push-pull input, three-state output Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Table 8 BUS sensing BUS © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 12
... PIO bus of the DC is selected bidirectional, I/O bit 0 of the bidirectional data bus that connects to the push-pull input, internal registers and buffer memory of the ISP1362; three-state output the bus is in the high-impedance state when it is idle bidirectional, I/O bit 1 of the bidirectional data bus that connects to the push-pull input, internal registers and buffer memory of the ISP1362 ...
Page 13
... A) and cables through some termination resistors. The transceiver is compliant with Universal Serial Bus Specification Rev 2.0 . 8.6 Overcurrent protection The ISP1362 has a built-in overcurrent protection circuitry. This feature monitors the current drawn on the downstream V exceeds the current threshold. The built-in overcurrent protection feature can be used when the port acts as a host port ...
Page 14
... PIO and direct memory access (DMA) modes. When CS is LOW (active), the address pin A1 has priority over DREQ/DACK. Therefore, as long as the CS pin is held LOW, the ISP1362 bus interface does not response to any DACK signals. When CS is HIGH (inactive), the bus interface will response to DREQn/DACKn ...
Page 15
... The buffer memory of the DC follows a similar architecture. Details on the DC memory area allocation can be found in memory does not support the direct addressing mode. 9.1.1 Memory organization for the HC The HC in the ISP1362 has a total of 4096 bytes of buffer memory. This buffer area is divided into four parts (see Table 4: Buffer memory area ...
Page 16
... ATL buffers are further divided into blocks of equal sizes depending on the value written into the HcATLBlkSize register (ATL) and the HcINTLBlkSize register (INTL). The ISP1362 HC supports blocks in the ATL and INTL buffers. Each of these blocks can be used for one complete Philips Transfer Descriptor (PTD) data. ...
Page 17
... While the PTD header remains 8 bytes for all PTDs, the PTD payload can be of any size. However, the PTD payload is padded to the next DWord boundary when the HC calculates the location of the next PTD header. The ISP1362 HC checks the payload size from the ‘Total size’ field of the PTD itself and calculates the location of the next PTD header based on this information ...
Page 18
... Fig 6. A sample snapshot of the ISTL memory management scheme. 9.1.2 Memory organization for the DC The ISP1362 DC has a total of 2462 bytes of built-in buffer memory. This buffer memory is multiconfigurable to support the requirements of different applications. The DC buffer memory is divided into 16 areas to be used by control OUT, control IN and 14 programmable endpoints ...
Page 19
... The ISP1362 provides the PIO mode for external microprocessors to access its internal control registers and buffer memory. It occupies only four I/O ports or four memory locations of a microprocessor. An external microprocessor can read or write to the internal control registers and buffer memory of the ISP1362 through the PIO operating mode. ISP1362. ...
Page 20
... Fig 8. PIO interface between a microprocessor and the ISP1362. 9.3 DMA mode The ISP1362 also provides the DMA mode for external microprocessors to access the internal buffer memory of the ISP1362. The DMA operation enables data to be transferred between the system memory of a microprocessor and the internal buffer memory of the ISP1362. ...
Page 21
... The register structure in the ISP1362 is a command-data register pair structure. A complete register access needs a command phase followed by a data phase. The command (also named as the index of a register) is used to inform the ISP1362 about the register that will be accessed at the data phase. On the 16-bit data bus of a microprocessor, a command occupies the lower byte and the upper byte is fi ...
Page 22
... CMD/DATA SWITCH 1 command port Host or Device bus interface data port 0 A0 Control registers Read 16-bit A0/ D[15:0] Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Commands Command register . . . 004aaa160 Write16-bit 004aaa045 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 23
... Command phase Writing to a 16/32-bit register 32-bit access 16-bit access Data phase Command phase Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Second data phase for 32-bit register Second data phase for 32-bit register 004aaa046 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 24
... Data phase } 9.5 PIO access to the buffer memory The buffer memory in the ISP1362 can be addressed by using either the direct addressing method or the indirect addressing method. 9.5.1 PIO access to the buffer memory by using direct addressing This method uses the HcDirectAddressLength register to specify two parameters required to randomly access the ISP1362 buffer memory (total of 4096 bytes) ...
Page 25
... After writing the proper value into the HcDirectAddressLength register, data is accessible from the HcDirectAddressData register (called as HcDirAddr_Port in the following sample code). A sample code for writing word_size bytes of data from *w_ptr into the memory locations of the ISP1362 buffer starting from the address start_addr is as follows: void direct_write(unsigned int *w_ptr,unsigned int ...
Page 26
... The ISP1362 uses two DMA channels to individually serve the HC and the DC. The DMA transfer allows the system CPU to work on other tasks while the DMA controller transfers data to or from the ISP1362. The DMA slave controller, in the ISP1362, is compatible with the 8327 type DMA controller. ...
Page 27
... Combining the two DMA channels The ISP1362 allows systems with limited DMA channels to use a single DMA channel (DMA1) for both the HC and the DC. This option can be enabled by writing logic 1 to the OneDMA bit of the HcHardwareConfiguration register. If this option is enabled, the polarity of the DC DMA and the HC DMA must be set to DACK active LOW and DREQ active HIGH ...
Page 28
... LE LATCH INT1 From INT2 OneINT HcHardwareConfiguration register 14). A pair of registers control each group. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Hc PInterruptEnable register OR HcHardwareConfiguration register InterruptPinEnable 004aaa210 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 29
... To re-enable the interrupt generation: 1. Set all bits in the HcmPInterruptEnable register according to the HCD requirements. 2. Set the InterruptPinEnable bit to logic 1. 9.7.2 Interrupt in the DC The registers that control the interrupt generation in the ISP1362 DC are: • DcMode (bit 3) • DcHardwareConfiguration (bits 0 and 1) • ...
Page 30
... However, non-portable devices (even standard hosts) can also benefit from OTG features. The ISP1362 OTG controller is designed to perform all the tasks specified in the OTG supplement. It supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices. The ISP1362 uses software implementation of HNP/SRP for maximum fl ...
Page 31
... Charge/discharge resistors for V 10.2 Dual-role device When port 1 of the ISP1362 is configured in the OTG mode, it can be used as an OTG dual-role device. A dual-role device is a USB device that can function either as a host peripheral host, the ISP1362 can support all four types of transfers (control, bulk, isochronous and interrupt) at full-speed or low-speed peripheral, the ISP1362 can support 2 control endpoints and confi ...
Page 32
... OtgControl register to logic 0]. BUS BUS for about 30 ms [by using DISCHRG_V BUS pulsing. The ISP1362 allows you to choose which SRP to support and has a by detecting SRP. In this case, it may choose to disable BUS Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller pulsing ...
Page 33
... B-device may turn on its DP pull-up at this time. 9397 750 10767 Product data 15 driven Legend Pull-up dominates Pull-down dominates Normal bus activity Figure 15: Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 004aaa079 33 of 148 ...
Page 34
... Timers: The HNP state machine uses four timers: a_wait_vrise_tmr, a_wait_bcon_tmr, a_aidl_bdis_tmr and b_ase0_brst, tmr. All timers are started on entry to and reset on exit from their associated states. The ISP1362 provides a programmable timer that can be used as any of these four timers. 9397 750 10767 ...
Page 35
... Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller b_idle drv_vbus/ chrg_vbus/ id loc_conn/ loc_sof/ a_bus_drop/ & (a_bus_req | a_srp_det) a_wait_vrise drv_vbus loc_conn/ loc_sof a_vbus_drop | a_vbus_vld | ...
Page 36
... HNP implementation and OTG state machine The OTG state machine is the software behind all the OTG functionality implemented in the microprocessor system that is connected to the ISP1362. The ISP1362 provides all input status, the output control and timers to fully support the state machine transitions in These registers include: • ...
Page 37
... Philips document ISP1362 Embedded Programming Guide . 10.5 Power saving in the idle state and during wake-up The ISP1362 can be put in the power saving mode if the OTG device is not in a session. This significantly reduces the power consumption. In this mode, both the DC and the HC are suspended. The PLL and the oscillator are stopped, and the charge pump is in the suspend state ...
Page 38
... Fig 18. External capacitors connection. 11. USB Host Controller (HC) 11.1 USB states of the HC The USB HC in the ISP1362 has four USB states: USBOperational, USBReset, USBSuspend and USBResume These states define the responsibilities of the HC related to the USB signaling and bus states. These signals are visible to the HC Driver (HCD), the software driver of the HC, by using the control registers of the ISP1362 USB HC ...
Page 39
... ISP1362 hardware. In this state of operation PTD is written to the buffer memory, it would be processed and sent. 11.3 USB ports The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be configured as a downstream port (host), an upstream port (device dual-role port (OTG). Port fixed downstream port. ...
Page 40
... PTD structure will have an offset of 40 bytes [sum of the block size (32 bytes) and the PTD header size (8 bytes)]. However, because of the fixed block size of the ISP1362 HC, even a PTD with 4 bytes of payload will take up all the 40 bytes in a block. ...
Page 41
... B7[7:0] Special fields for ATL, interrupt and ISO ATL Interrupt reserved reserved Paired reserved Ping-Pong reserved reserved PollingRate[7:5]; StartingFrame[4:0] Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller PTD data #1 PTD data #2 PTD data #N 004aaa121 2 1 Toggle ActualBytes[9:8] Speed MaxPktSize[9:8] TotalBytes[9:8] [1] ...
Page 42
... USB data rate. This indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 43
... Possible to send maximum of 18 USB bulk packets frame (1.152 Mbyte/s) by using the paired PTD feature. • Provides the status of every transfer endpoints (PTD) by monitoring the HcATLDoneMap of the ISP1362. This register provides information on which PTD transfers are complete. • Sets the IRQ after the user-specified number of transfers is done. ...
Page 44
... This section provides an example on how a USB transfer descriptor ‘Get Descriptor’ (commonly used in device enumeration) is used to illustrate the ISP1362 PTD application. To perform this example, make sure the ISP1362 is in the Operational state, and then connect a USB device (for example, a USB mouse port. ...
Page 45
... Supports multi-buffering by using the ISTL0/ISTL1 toggling mechanism. • The CPU can decide (in ms) how fast it can serve the ISP1362. This gives the CPU the flexibility to decide how much time it takes to read and fill in the ISO data. • The ISTL buffer can be updated on-the-fly by using the direct addressing memory architecture ...
Page 46
... Philips Semiconductors 11.8 Overcurrent protection circuit The ISP1362 has a built-in overcurrent protection circuitry. You can enable or disable this feature by setting or resetting AnalogOCEnable (bit 10) of the HcHardwareConfiguration register. If this feature is disabled assumed that there is an external overcurrent protection circuitry. 11.8.1 Using internal OC detection circuit ...
Page 47
... F (25 V) DGND DGND R41 C38 R42 DGND DGND for H_DM2 and H_DP2 supply V BUS Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller CC connection, OC H_OCn EN H_PSWn R25 DMn R26 DPn C37 47 pF 004aaa149 from an external source. In this BUS that will be sensed by BUS © ...
Page 48
... SUSPEND/WAKEUP pin must be pulled- large resistor (100 the suspend state, this pin is HIGH. To wake up the HC, this pin must be pulled LOW. The ISP1362 can be partially suspended (only the HC or only the DC). In the partially suspended state, clock circuit and PLL continue to work. To save power, both the HC and the DC must be set to the suspend mode ...
Page 49
... OUT data transfer data transfer means transfer from the ISP1362 to an external USB host (through the upstream port), and an OUT transfer means transfer from an external USB host to the ISP1362. In the device mode, the ISP1362 acts as a USB device. 12.1.1 IN data transfer • ...
Page 50
... Remark: If the OneDMA bit in the HcHardwareConfiguration register is set to logic 1, the DC DMA controller handshake signals DREQ2/DACK2 are routed to DREQ1/DACK1. 9397 750 10767 Product data Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
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... Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller DMA mode Endpoint type access [1][2] no control OUT [1][2] no control IN supported programmable supported programmable supported programmable ...
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... Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Isochronous 16 bytes 32 bytes 48 bytes 64 bytes 96 bytes 128 bytes 160 bytes 192 bytes 256 bytes ...
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... OUT 16 16-byte interrupt IN 64 double-buffered 64-byte bulk OUT 64 double-buffered 64-byte bulk IN Table Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller 14), whether endpoints are enabled © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
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... Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Table 17. The transfer direction (read or Transfer direction EPDIR = 0 EPDIR = 1 OUT: read IN: write OUT: read IN: write OUT: read IN: write OUT: read IN: write OUT: read IN: write ...
Page 55
... DACK2 DACK RD IOR WR IOW Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller 114). The pin functions for this mode Function DC requests a DMA transfer DMA controller confirms the transfer DMA controller terminates the transfer instructs the DC to put data on the bus ...
Page 56
... DMA operation after transferring the data bytes of this packet. 9397 750 10767 Product data A DMA transfer to or from a bulk endpoint can be terminated by any and Table 119): Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 57
... This is achieved by shutting down the power to system components or supplying them with a reduced voltage. The steps leading to the suspend status are as follows the event of no SOF for 3 ms, the DC in the ISP1362 sets bit SUSPND of the DcInterrupt register. This will generate an interrupt if bit IESUSP of the DcInterruptEnable register is set. ...
Page 58
... DC in the ISP1362 resumes its normal functionality (this could be set to 100 s by setting the TEST0 pin to HIGH case of a remote wake-up, the DC in the ISP1362 drives a K-state on the USB bus for 10 ms. 5. The application restores itself and other system components to normal operating mode ...
Page 59
... Philips Semiconductors 6. After wake-up, the internal registers of the DC in the ISP1362 are read and write-protected to prevent corruption by inadvertent writing during power-up of external components. The firmware must send an Unlock Device command to the DC in the ISP1362 to restore its full functionality. 13. OTG registers Table 21: ...
Page 60
... DP of the OTG PULLDN_ port DP 1 — connects the on-chip pull-down resistor the OTG port Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller pulsing BUS © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 61
... V BUS 1 — enable driving V BUS reserved - - - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued BUS BUS through a BUS of the OTG port BUS of the OTG port BUS of the OTG port of the OTG port 10 9 SE0_2MS ...
Page 62
... This bit reflects the logic level of the ID pin. 0 — ID pin is LOW (mini-A plug is inserted in the device’s mini-AB receptacle) 1 — ID pin is HIGH (no plug or mini-B plug is inserted in the device’s mini-AB receptacle) Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller B_SESS_ ...
Page 63
... This bit is used to detect state change when the device is RESUME in the ‘suspend’ state. Writing logic 1 clears this bit. Writing logic 0 has no effect. 0 — no event 1 — a resume signal (J ‘suspend’ state Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller OTG_TMR B_SE0_ A_SRP_ ...
Page 64
... ID pin is shorted to ground or pulled HIGH). Write logic 1 to clear this bit. Writing logic 0 has no effect. 0 — no event 1 — ID_REG bit has changed Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 65
... Logic 1 enables interrupt upon detection of B_SESS_END status END_IE change. A_VBUS_ Logic 1 enables interrupt upon detection of A_VBUS_VLD status VLD_IE change. ID_REG_IE Logic 1 enables interrupt upon detection of the ID_REG status change. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller OTG_ B_SE0_ A_SRP_ TMR_IE SRP_IE ...
Page 66
... TMR_INIT_ These bits define the initial value used by the OTG timer. The timer VALUE interval is 0.01 ms. Maximum timer allowed is 167.772 s. [23: reserved - - - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller R/W R/W R/W ...
Page 67
... HC operational registers (32 bits). These operational registers are made compatible to Open Host Controller Interface (OpenHCI) operational registers. This enables the OpenHCI HCD to be ported easily to the ISP1362. Reserved bits may be defined in future releases of this specification. To ensure interoperability, the HCD that does not use a reserved field must not assume that the reserved fi ...
Page 68
... Section 14.7.1 on page 99 16 Section 14.7.2 on page 99 16 Section 14.7.3 on page 100 16 Section 14.7.4 on page 100 Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Functionality HC Control and Status registers HC Frame Counter registers HC Root Hub registers HC DMA and Interrupt Control registers ...
Page 69
... Section 14.9.7 on page 106 16 Section 14.9.8 on page 107 Section 14.9.9 on page 107 reserved - - - - - - reserved - - - - - - reserved - - - - - - REV[7: Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Functionality Interrupt Transfer registers Aperiodic Transfer registers Table 35 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 70
... Table 37 shows the bit allocation of the register reserved - - - - - - reserved - - - - - - reserved - - - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller RWE RWC reserved 0 0 R/W R reserved - - - - © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 71
... The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. - reserved 39. This register is used by the HC to receive commands issued by the HCD, Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 72
... HC upon the completion of the reset operation. The reset operation must be completed within 10 ms. This bit, when set, should not cause a reset to the Root Hub and no subsequent reset signaling should be asserted to its downstream ports. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller ...
Page 73
... The HCD clears this bit after the HC has been reset. Philips Host Controller Interface (PHCI): Always set to logic 0. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller 14.1.5) and the MasterInterruptEnable 26 25 ...
Page 74
... SchedulingOverrun: This bit is set when the USB schedules for current frame overruns. A scheduling overrun also causes the SchedulingOverrunCount (SOC) of HcCommandStatus to be incremented reserved - - - - - - reserved - - - - - - reserved - - - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued Table 43 contains © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 75
... Resume Detect SF 0 — ignore 1 — enable interrupt generation due to Start of Frame - reserved SO 0 — ignore 1 — enable interrupt generation due to Scheduling Overrun Table reserved - - - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller reserved R/W - R/W provides the bit allocation of the ...
Page 76
... RD 0 — ignore 1 — disable interrupt generation due to Resume Detect SF 0 — ignore 1 — disable interrupt generation due to Start of Frame - reserved SO 0 — ignore 1 — disable interrupt generation due to Scheduling Overrun Table Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller ...
Page 77
... By setting the HostControllerReset (HCR) field of the HcCommandStatus register because this causes the HC to reset this field to its nominal value. The HCD may choose to restore the stored value upon completing the Reset sequence. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller ...
Page 78
... When entering the USBOPERATIONAL state, the HC reloads it with the content of the FrameInterval (FI) part of the HcFmInterval register and uses the updated value from the next SOF. 51. It provides a timing reference for events happening in the HC and the HCD reserved - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller ...
Page 79
... SOF. However, the content needs to be written before the HC reads the first Endpoint Descriptor (ED) in that frame. After writing to HCCA, the HC needs to set the StartofFrame (SF) in HcInterruptStatus reserved - - - - - - reserved - - - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller ...
Page 80
... LST[10:0] LSThreshold: Contains a value that is compared to the FrameRemaining (FR) field before a low-speed transaction is initiated. The transaction is started only if FrameRemaining (FR) this field. The value is calculated by the HCD, which considers transmission and set-up overhead. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller LST[10: ...
Page 81
... On power up, clear this bit and then set it to logic 1 DT DeviceType: This bit specifies that the Root Hub is not a compound device not permitted. This field should always read as 0. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Table 55 ...
Page 82
... The maximum number of ports supported is 2. Table 57 shows the bit allocation of the register reserved - - - - - - reserved - - - - - - reserved - - - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued PPCM[2:0] IS R/W R/W R © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 83
... Hub. When cleared, the attached device is removable. When set, the attached device is not removable. Bit 2 — Device attached to Port #2 Bit 1 — Device attached to Port #1 Bit 0 — reserved reserved - - - - - - reserved - - - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller DR[2:0] IS R/W R/W R/W Table 59 for bit CCIC LPSC ...
Page 84
... ConnectStatusChange as a resume event, causing a state transition from USBSUSPEND to USBRESUME and setting the ResumeDetected interrupt. 0 — ConnectStatusChange is not a remote wake-up event 1 — ConnectStatusChange is a remote wake-up event On write—SetRemoteWakeupEnable: Writing logic 1 sets DeviceRemoveWakeupEnable. Writing logic 0 has no effect. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller ...
Page 85
... PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing logic 0 has no effect. Table 61 reserved - - - - PRSC OCIC - R/W R reserved - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued PSSC PESC 0 0 R/W R LSDA - - R/W © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 86
... CurrentConnectStatus (CCS) 1 — change in CurrentConnectStatus (CCS) Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only after a Root Hub reset to inform the system that the device is attached. - reserved Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller PSS PES CCS ...
Page 87
... On write—SetPortPower: The HCD writes logic 1 to set the PortPowerStatus (PPS) bit. Writing logic 0 has no effect. Remark: This bit always reads logic 1 if power switching is not supported. - reserved Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 88
... On write—ClearSuspendStatus: The HCD writes logic 1 to initiate a resume. Writing logic 0 has no effect. A resume is initiated only if PortSuspendStatus (PSS) is set. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 89
... PortEnableStatus (PES) bit. Writing logic 0 has no effect. CurrentConnectStatus (CSC) is not affected by any write. Remark: This bit always reads 1B when the attached device is nonremovable (DeviceRemoveable[NDP]). Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 90
... LOW), the pull-down resistors on OTG_DM1, OTG_DP1 are controlled by the LOC_PULL_DN_DP and LOC_PULL_DN_DM bits of the OtgControl register. SuspendClkNotStop 0 — clock can be stopped when suspended 1 — clock cannot be stopped when suspended Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Table 63 AnalogOC OneINT ...
Page 91
... INT1 is enabled; this bit should be used with the Hc PInterruptEnable register to enable pin INT1 contains the bit allocation of the HcDMAConfiguration register reserved - - - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 148 ...
Page 92
... This bit needs to be reset to zero when the DMA transfer is completed. Buffer_Type_Select Bit 3 [2: DMAReadWriteSelect 0 — read from the buffer memory of the HC 1 — write to the buffer memory of the HC Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller DMARead WriteSelect R/W R/W R/W Bit 2 ...
Page 93
... Count value of the HcATLDoneThresholdCount register or the time-out value of the HcATLPTDDoneThresholdTimeOut register has reached. The microprocessor is required to read HcINTLPTDDoneMap to check the PTDs that have completed their transactions. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Table 67. Table 68. 10 ...
Page 94
... For the microprocessor to perform the DMA transfer of ISO data from or to the ISTL buffer, the HC must first initialize the HcDMAConfiguration register. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 95
... Hc PInterruptEnable register: bit description Symbol Description - reserved OTG_IRQ_ 0 — power-up value InterruptEnable 1 — enables the OTG_IRQ interrupt ATL_IRQ_ 0 — power-up value InterruptEnable 1 — enables the ATL_IRQ interrupt Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller 70 OTG_IRQ_ ATL_IRQ_ Interrupt Interrupt Enable Enable - 0 ...
Page 96
... HC miscellaneous registers 14.5.1 HcChipID register (27H—Read only) This register contains the ID of the ISP1362. The upper byte identifies the product name (here 36H stands for the ISP1362). The lower byte indicates the revision number of the product including engineering samples (ES). ...
Page 97
... The ISTL0 buffer has not yet been read by the HC. BufferDone 1 — The ISTL0 buffer has been read by the HC. - reserved ISTL1_ActiveStatus 0 — The ISTL1 buffer is not accessed by the slave host. 1 — The ISTL1 buffer is accessed by the slave host. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Table 75 PairedPTD ISTL1 ...
Page 98
... DataByteCount[15: R/W R/W R DataByteCount[7: R/W R/W R BufferStartAddress[14: R/W R/W R BufferStartAddress[7: R/W R/W R/W Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued 77 R/W R/W R R/W R/W R R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 99
... Code (Hex): B0 — write 14.7.2 HcISTL0BufferPort register (40H—Read, C0H—Write) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data port for accessing the ISTL0 buffer. The starting address for accessing the buffer is always fixed at 0000H. Therefore, random access of the ISTL0 buffer is not allowed ...
Page 100
... Code (Hex): C0 — write 14.7.3 HcISTL1BufferPort register (42H—Read, C2H—Write) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data port for accessing the ISTL1 buffer. The starting address for accessing the buffer is always fixed at 0000H. Therefore, random access of the ISTL1 buffer is not allowed ...
Page 101
... Code (Hex): B3 — write 14.8.2 HcINTLBufferPort register (43H—Read, C3H—Write) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data port for accessing the INTL buffer. The starting address for accessing the buffer is always fixed at 0000H. Therefore, random access of the INTL buffer is not allowed ...
Page 102
... Code (Hex): C3 — write 14.8.3 HcINTLBlkSize register (53H—Read, D3H—Write) The ISP1362 requires the INTL buffer to be partitioned into several equal sized blocks so that the HC can skip the current PTD and proceed to process the next PTD easily. The block size of the INTL buffer is required to be specified in this register and must be a multiple of 8 bytes ...
Page 103
... The PTD is the last PTD stored in the buffer. Table 92 shows the bit allocation of the register reserved - - - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Table 90. Bit 0 of the © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 103 of 148 ...
Page 104
... Code (Hex): B4 — write 14.9.2 HcATLBufferPort register (44H—Read, C4H—Write) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data port for accessing the ATL buffer. The starting address for accessing the buffer is always fixed at 0000H. Therefore, random access of the ATL buffer is not allowed ...
Page 105
... Code (Hex): C4 — write 14.9.3 HcATLBlkSize register (54H—Read, D4H—Write) The ISP1362 partitions the ATL buffer into several equal sized blocks so that the HC can skip the current PTD and proceed to process the next PTD easily. The block size of the ATL buffer must be specified in this register and must be a multiple of 8 bytes. ...
Page 106
... The PTD is not the last PTD stored in the buffer. 1 — The PTD is the last PTD stored in the buffer. Table 101 shows the bit allocation of the register reserved - - - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller ActivePTD[4: © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 106 of 148 ...
Page 107
... R/W R/W Symbol Description - reserved PTDDoneCount[4:0] Number of PTDs processed by the HC reserved - - - - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Table 103 shows the bit PTDDoneCount[4: R/W R/W R/W Table 105 shows the bit allocation © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 108
... Maximum allowable time in ms for the HC to retry a transaction with NAK returned. Destination Code (Hex) DcEndpointConfiguration register 20 endpoint 0 OUT DcEndpointConfiguration register 21 endpoint 0 IN DcEndpointConfiguration register endpoint Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller R/W R/W R/W Table 107. [1] ...
Page 109
... OUT 70 [5] illegal (71) buffer memory endpoint [5] (OUT endpoints only) Endpoint 0 OUT 80 Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller [1] Transaction [2] read 1 byte [2] read 1 byte [2] read 1 byte [2] write/read 1 byte [2] write/read 1 byte write/read 2 bytes write/read 4 bytes ...
Page 110
... endpoint all registers with write access B0 DcScratch register B2/B3 DcFrameNumber register B4 DcChipID register B5 DcInterrupt register C0 1023, the firmware must take care of the upper byte. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller [1] Transaction - - [2] read 1 byte [2] read 1 byte [2] read 1 byte - [2] read 1 byte ...
Page 111
... DMA transfer direction (0 = read write). DBLBUF Logic 1 indicates that this endpoint has double buffering. FFOISO Logic 1 indicates an isochronous endpoint. Logic 0 indicates a bulk or interrupt endpoint. FFOSZ[3:0] Selects the buffer memory size according to 110. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Table 14). Automatic FFOSZ[3: ...
Page 112
... R/W R/W R/W Symbol Description - reserved GOSUSP Writing logic 1 followed by logic 0 will activate the ‘suspend’ mode. - reserved INTENA Logic 1 enables all interrupts. Bus reset value: unchanged. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller R/W R/W R DBGMOD reserved SOFTCT ...
Page 113
... OtgControl register controls the pull-up resistor on the OTG_DP1 pin. Table NOLAZY CLKRUN R/W R/W R DAKPOL reserved WKUPCS R/W - R/W Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Table 114). Bus 114. A bus reset will not change any CKDIV[3: R/W R/W R reserved INTLVL INTPOL R/W R/W R/W © ...
Page 114
... Bus reset value: unchanged. INTPOL Selects the INT2 signal polarity (0 = active LOW active HIGH). Bus reset value: unchanged. Table 116. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller The clock frequency range is © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 115
... Logic 1 enables interrupt upon the EOT detection. IESUSP Logic 1 enables interrupt upon detection of a ‘suspend’ state. IERESM Logic 1 enables interrupt upon detection of a ‘resume’ state. IERST Logic 1 enables interrupt upon detection of a bus reset. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller ...
Page 116
... Selects the DMA burst length: 00 — single-cycle mode (1 byte) 01 — burst mode (4 bytes) 10 — burst mode (8 bytes) 11 — burst mode (16 bytes) Bus reset value: unchanged. Table 120. Writing to the register sets the number of bytes for Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller ...
Page 117
... R/W R DMACR[7: R/W R/W R/W Symbol Description DMACR[15:0] DcDMACounter register 2) bytes can be written or read, N representing the size of the 1) divided by 2. After each read or write action the buffer pointer is Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller R/W R/W R R/W R/W R/W © ...
Page 118
... D[15:0] 2 … … … Table 124. Reading the DcEndpointStatus register will clear the interrupt bit 15.2.3). Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller 2 bytes (isochronous endpoint: N Table Table 123. Description command code (00H to 1FH) ignored packet length data word 1 (data byte 2, data byte 1) data word 2 (data byte 4, data byte 3) … ...
Page 119
... Set-up packet. SETUPT Logic 1 indicates that the buffer contains a Set-up packet. CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller SETUPT CPUBUF reserved 0 0 ...
Page 120
... Logic 1 indicates that the secondary endpoint buffer is full. EPFULL0 Logic 1 indicates that the primary endpoint buffer is full. DATA_PID This bit indicates the data PID of the next packet (0 = DATA0 PID DATA1 PID). Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Section 12.3.6. Section 12.3.6. 3 ...
Page 121
... Logic 1 indicates that a new event occurred before the previous status was read. DATA01 This bit indicates the PID type of the last successfully received or transmitted packet (0 = DATA0 PID DATA1 PID). Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued Section 12.3.6. 3 ...
Page 122
... DATA PID; data was ignored Table 131 UNLOCK[15:8] = AAH Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued Table 130 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 122 of 148 ...
Page 123
... Sending data AA37H unlocks the internal registers and buffer memory for writing, following a ‘resume’ R/W R SFIR[7: R/W R/W R/W Symbol Description - reserved; must be logic 0 SFIR[12:0] Scratch Information register Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Table 133 SFIR[12: R/W R/W R ...
Page 124
... SOFR[7: Symbol Description - reserved SOFR[9:0] frame number Phase Bus lines Word # command D[15:8] - D[7:0] - data D[15:0] 0 138 CHIPIDH[7: CHIPIDL[7: Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller SOFR[9: Description ignored command code (B4H) frame number © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 125
... Logic 1 indicates the interrupt source: control IN endpoint. EP0OUT Logic 1 indicates the interrupt source: control OUT endpoint. BUSTATUS Monitors the current USB bus status (0 = awake suspend). SP_EOT Logic 1 indicates that an EOT interrupt has occurred for a short period. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller ...
Page 126
... USB bus. RESUME Logic 1 indicates that a ‘resume’ state was detected. RESET Logic 1 indicates that a bus reset condition was detected. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 126 of 148 ...
Page 127
... O(od) T ambient temperature amb [ tolerant. 9397 750 10767 Product data Conditions pins V < > < Conditions Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Min Max Unit 0.5 +4.6 V 0.5 +6 100 mA [1] 2000 +2000 V 60 +150 C Min ...
Page 128
... These values are applicable to transistor inputs. The value will be different if internal pull-up or pull-down resistors are used. 9397 750 10767 Product data = unless otherwise specified. Conditions HC and DC are [1] suspended = unless otherwise specified. Conditions [ [2] pin to GND Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Min Typ Max - Min Typ Max - - 0.8 2 ...
Page 129
... F unless otherwise specified. LOAD Conditions from V LOAD BUS(OTG) external capacitor 3 external capacitor 3 external capacitor 3 not driven BUSOTG Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Min Typ Max [1] 0 0 0.8 2 0.3 2 ...
Page 130
... ATX is idle LOAD mA; ATX is idle LOAD mA LOAD IN when the DC/DC regulator is active enabled when V is LOW BUSPULSE_n enabled when V is HIGH BUSPULLDOWN DRV_VBUS = 0 when ID = HIGH (device) and DRV_VBUS =1 Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Min Typ Max Unit - - 300 A 4 ...
Page 131
... 3 3 charge-pump capacitor. Fig 26. Output voltage versus load current. 9397 750 10767 Product data Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller 004aaa211 load (mA) 004aaa212 load (mA) © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 131 of 148 ...
Page 132
... [ pF 1 Conditions pF; L 10 pF; L 90 unless otherwise specified. LOAD Conditions mA; LOAD LOAD Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Min Typ Max [ [ 100 - 500 unless otherwise TERM Min Typ Max ...
Page 133
... VBUS(VALID_dly) BUS V output ripple with constant RIPPLE load 9397 750 10767 Product data …continued = unless otherwise specified. LOAD Conditions LOAD Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Min Typ Max 100 - 200 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 134
... HIGH logic LOW stop, not active (OFF) start, active (ON) valid logic level invalid logic level high-impedance (floating, three-state) Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 134 of 148 ...
Page 135
... WHSH t WR data set-up time WDSU t WR data hold time WDH 9397 750 10767 Product data Conditions Min 5 2 register access 300 buffer access 462 110 143 - - 26 110 136 Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Typ Max Unit - - ...
Page 136
... Product data t SHSL t RLRH t RHRL t RLDV data data valid valid t WHWL WDH data data valid valid Conditions Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller t SLRL t SLWL t RHSH t WHSH RHDZ data data valid valid WDSU data data valid valid MGT969 Min ...
Page 137
... Product data t RHAX t AVRL t SHDZ (1) t RLRH t SHRL t RHSH t WHAX t AVWL (1) t SHWL t WHSH t WHDZ Conditions Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller 004aaa105 004aaa106 Min Typ Max © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Unit ns ns ...
Page 138
... RD/WR HIGH to DACK1 HIGH SHAH t DREQ1 HIGH to DACK1 LOW RHAL 9397 750 10767 Product data …continued Conditions ALRL t SHAH t AHRH t RLDV t RHDZ data valid data valid t WSU t WHD Conditions Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Min Typ Max [ ...
Page 139
... Fig 32. DC single-cycle DMA timing (8237 mode). 9397 750 10767 Product data …continued Conditions 4-cycle burst mode 8-cycle burst mode 4-cycle burst mode 8-cycle burst mode t RHRL RLRH Conditions ASRP Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Min Typ Max [ 105 - - 150 - - 72 - ...
Page 140
... DACK2 on ASDV t data hold after DACK2 off APDZ 9397 750 10767 Product data Conditions Min - 25 180 - - t ASRP t APRS t ASAP t APDZ t ASDV Conditions Min - 25 180 - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Typ Max Unit - 004aaa112 Typ Max Unit - 40 ns ...
Page 141
... DACK2 (1) Programmable polarity: shown as active LOW. Fig 35. DC burst mode DMA timing. 9397 750 10767 Product data t ASAP t ASRP t ASDV Conditions (min) t RSIH t ILRP t IHIL Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller t APRS t APDZ 004aaa113 Min Typ Max 160 - - ...
Page 142
... 2 scale (1) ( 0.18 10.1 10.1 12.15 12.15 0.5 1.0 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC EIAJ MS-026 Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller SOT314 detail X (1) ( 0.75 1.45 1.45 7 0.2 0.12 0.1 o 0.45 1.05 1.05 0 EUROPEAN ISSUE DATE ...
Page 143
... 6.1 0.5 4.5 4.5 0.15 0.05 5.9 REFERENCES JEDEC JEITA MO-195 - - - Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller detail 0.08 0.1 EUROPEAN ISSUE DATE PROJECTION 00-11-22 02-04-09 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. SOT543-1 ...
Page 144
... The footprint must incorporate solder thieves at the downstream end. 9397 750 10767 Product data Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller 2.5mm 3 so called 3 so © ...
Page 145
... Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 9397 750 10767 Product data methods [1] [4] , SO, SOJ Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Soldering method Wave Reflow not suitable suitable [3] not suitable ...
Page 146
... Table 138 and Table 139: changed the chip ID 145: added table note 2 147: updated I LOAD Figure 27. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 146 of 148 ...
Page 147
... SoftConnect — trademark of Koninklijke Philips Electronics N.V. SPARClite — registered trademark of Sparc International. StrongARM — trademark of ARM Ltd. Toshiba — registered trademark of Toshiba Corp. Rev. 02 — 19 February 2003 ISP1362 Single-chip USB OTG controller Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 147 of 148 ...
Page 148
... Date of release: 19 February 2003 Document order number: 9397 750 10767 Single-chip USB OTG controller 12.5 ISP1362 DC Suspend/Wake- OTG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13.1 OtgControl register (62H—Read, E2H—Write 13.2 OtgStatus register (67H— ...