ADSP-BF561 Analog Devices, ADSP-BF561 Datasheet
ADSP-BF561
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ADSP-BF561 Summary of contents
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... DMA CONTROLLER2 32 DAB PPI PPI Figure 1. Functional Block Diagram One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel:781/329-4700 Fax:781/326-8703 ® Blackfin Embedded Symmetric Multi-Processor ADSP-BF561 2 S Channels IRQ CTRL/ JTAG TEST TIMER EMULATION UART IRDA® SRAM 128 KBYTES SPORT0 SPORT1 ...
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... ADSP-BF561 TABLE OF CONTENTS General Description ................................................. 3 Portable Low-Power Architecture ............................. 3 Blackfin Processor Core .......................................... 3 Memory Architecture ............................................ 4 Internal (On-chip) Memory ................................. 4 External (Off-Chip) Memory ................................ 5 I/O Memory Space ............................................. 6 Booting ........................................................... 6 Event Handling ................................................. 6 Core Event Controller (CEC) ................................ 6 System Interrupt Controller (SIC) .......................... 6 Event Control ................................................... 7 DMA Controllers .................................................. 8 WatchDog Timers ................................................ 8 Serial Ports (SPORTs) ............................................ 9 Serial Peripheral Interface (SPI) Ports ...
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... The ADSP-BF561 processor has 328 KBytes of on-chip mem- ory. Each Blackfin core includes: • 16K Bytes of Instruction SRAM/Cache • 16K Bytes of Instruction SRAM • ...
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... L1/L2 memories and the external memory spaces. Internal (On-chip) Memory The ADSP-BF561 has four blocks of on-chip memory providing high-bandwidth access to the core. The first is the L1 instruction memory of each Blackfin core consisting of 16K bytes of 4-way set-associative cache memory and 16K bytes of SRAM ...
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... Mapped Registers (MMRs) but share the same system MMR registers and 128 KB L2 SRAM memory. External (Off-Chip) Memory The ADSP-BF561 external memory is accessed via the External Bus Interface Unit (EBIU). This interface provides a glueless connection four banks of synchronous DRAM COREAM EM O RYM AP ...
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... The System Interrupt Controller provides the mapping and routing of events from the many peripheral interrupt sources, to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF561 provides a default mapping, the user can alter the mappings and priorities of interrupt events by writ- ing the appropriate values into the Interrupt Assignment Registers (IAR) ...
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... Default User IVG Interrupt 19 IVG08 20 IVG08 Event Control 21 IVG08 The ADSP-BF561 provides the user with a very flexible mecha- 22 IVG08 nism to control the processing of events. In the CEC, three 23 IVG09 registers are used to coordinate and control events. Each of the 24 IVG09 registers, as follows, is 16-bits wide, while each bit represents a ...
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... DMA (IMDMA) Controller. The IMDMA Controller allows data transfers between any of the internal L1 and L2 memories. WATCHDOG TIMERS Each ADSP-BF561 core includes a 32-bit timer, which can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the proces- sor to a known state, via generation of a hardware reset, non- maskable interrupt (NMI), or general- purpose interrupt, if the timer expires before being reset by software ...
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... H.100, H.110, MVIP-90, and HMVIP standards. SERIAL PERIPHERAL INTERFACE (SPI) PORTS The ADSP-BF561 has one SPI-compatible ports that enable the processor to communicate with multiple SPI-compatible devices. The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSIx, and Master Input- Slave Output, MISO) and a clock pin (Serial Clock, SCK) ...
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... PFx pin as input or output. • Flag Control and Status Registers – Rather than forcing the software to use a read-modify-write process to control the setting of individual flags, the ADSP-BF561 employs a "write one to set" and "write one to clear" mechanism that allows any combination of individual flags to be set or cleared in a single instruction, without affecting the level of any other flags ...
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... The use of multiple power domains maximizes (SCLK) flexibility, while maintaining compliance with industry stan- dards and conventions. By isolating the internal logic of the ADSP-BF561 into its own power domain, separate from the I/O, Rev. PrC | Page April 2004 ADSP-BF561 PLL ...
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... The percent power savings is calculated as: ) and clock DDINT % Power Savings VOLTAGE REGULATION The ADSP-BF561 processor provides an on-chip voltage regula- tor that can generate processor core voltage levels 0.85V(-5% / +10%) to 1.2V(-5% / +10%) from an external 2. 3.6 V supply. Figure 4 required to complete the power management system. The regu- ...
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... Preliminary Technical Data CLOCK SIGNALS The ADSP-BF561 can be clocked by an external crystal, a sine wave input buffered, shaped clock derived from an external clock oscillator external clock is used, it should be a TTL compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. This signal is connected to the processor’ ...
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... Code density enhancements, which include intermixing of 16- and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded as 16-bits. DEVELOPMENT TOOLS The ADSP-BF561 is supported with a complete set of TM CROSSCORE including Analog Devices emulators and the VisualDSP++® development environment. The same emulator hardware that supports other Analog Devices processors also fully emulates the ADSP-BF561 ...
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... File (LDF), allowing the developer to move between the graphi- cal and textual environments. Analog Devices’ emulators use the IEEE 1149.1 JTAG test access port of the ADSP-BF561 to monitor and control the target board processor during emulation. The emulator provides full- speed emulation, allowing inspection and modification of mem- ory, registers, and processor stacks. Non intrusive in-circuit emulation is assured by the use of the processor’ ...
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... ADSP-BF561 PIN DESCRIPTIONS ADSP-BF561 pin definitions are listed in inputs should be tied or pulled to V DDEXT Table 8. Pin Descriptions Block Pin Name Type Signals Function EBIU ADDR[25:2] O DATA[31:0] I/O ABE[3:0]/SDQM[3: BGH O EBIU SRAS O (SDRAM) SCAS O SWE O SCKE O SCLK0/CLKOUT O SCLK1 O SA10 O SMS[3:0] O EBIU ...
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... Sport1 Transmit Serial Clock / Programmable Flag 1 Sport1 Transmit Frame Sync / Programmable Flag 1 Sport1 Transmit Data Primary / Programmable Flag 1 Sport1 Transmit Data Secondary / Programmable Flag Rev. PrC | Page April 2004 ADSP-BF561 Driver Pull-up/down requirement Type C software configurable, no pull-up/down necessary C software configurable, no pull-up/down necessary C software configurable, ...
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... ADSP-BF561 Table 8. Pin Descriptions (Continued) Block Pin Name Type Signals Function PF/TIMER PF15/EXT CLK I/O PF14 I/O PF13 I/O PF12 I/O PF11 I/O PF10 I/O PF9 I/O PF8 I/O PF7/SPISEL7/ I/O TMR7 PF6/SPISEL6/ I/O TMR6 PF5/SPISEL5/ I/O TMR5 PF4/SPISEL4/ I/O TMR4 ...
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... Table 8. Pin Descriptions (Continued) Block Pin Name Type Signals Function Supplies VDDEXT P VDDINT P GND G No Connection NC Total pins 23 Power Supply 14 Power Supply 41 Power Supply Return 2 NC 256 Rev. PrC | Page April 2004 ADSP-BF561 Driver Pull-up/down requirement Type - N/A - N/A - N/A - N/A ...
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... Low Level Input Voltage IL T Ambient Operating Temperature AMBIENT Industrial Commercial 1 The ADSP-BF561 is 3.3 V tolerant (always accepts up to 3.6 V maximum V (maximum) approximately equals V (maximum). This 3.3 V tolerance applies to bi-directional and input only pins. DDEXT ELECTRICAL CHARACTERISTICS Parameter 1 V High Level Output Voltage ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-BF561 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precau- tions are recommended to avoid performance degradation or loss of functionality. – ...
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... Table 12 describe the timing requirements for the ADSP-BF561 clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock, system clock and Voltage Controlled Oscillator (VCO) operating fre- Table 9. Core and System Clock Requirements—ADSP-BF561SKBCZ500 ...
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... For more information, see the System Design chapter of the ADSP- SCLK t CKINH t WRST t SCLKD Figure 7. Clock and Reset Timing Rev. PrC | Page April 2004 ADSP-BF561 Min Max 25.0 100.0 10.0 10 CKIN 4 7.5 t SCLK ...
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... ADSP-BF561 Asynchronous Memory Read Cycle Timing Table 14. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements t DATA15–0 Setup Before CLKOUT SDAT t DATA15–0 Hold After CLKOUT HDAT t ARDY Setup Before CLKOUT SARDY t ARDY Hold After CLKOUT HARDY Switching Characteristic t Output Delay After CLKOUT ...
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... DO AWE ARDY t END AT DATA15–0 WRITE DATA 1 1 ACCESS HOLD PROGRAMMED WRITE EXTENDED ACCESS 2 CYCLES 1 CYCLE 1 CYCLE HARDY SARDY t SARDY Figure 9. Asynchronous Memory Write Cycle Timing Rev. PrC | Page April 2004 ADSP-BF561 Min Max 4.0 0.0 6.0 1.0 6.0 0 Unit ...
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... ADSP-BF561 SDRAM Interface Timing Table 16. SDRAM Interface Timing Parameter Timing Requirement t DATA Setup Before CLKOUT SSDAT t DATA Hold After CLKOUT HSDAT Switching Characteristic t CLKOUT Period SCLK t CLKOUT Width High SCLKH t CLKOUT Width Low SCLKL t Command, ADDR, Data Delay After CLKOUT DCAD ...
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... These are preliminary timing parameters that are based on worst-case operating conditions. 2 The pad loads for these timing parameters are 20 pF Figure 11. External Port Bus Request and Grant Cycle Timing Rev. PrC | Page April 2004 ADSP-BF561 Min Max 4.6 0.0 4.5 4.5 3.6 3.6 3.6 3 ...
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... ADSP-BF561 Parallel Peripheral Interface Timing Table 18, Figure 12, describes Parallel Peripheral Interface operations. Table 18. Parallel Peripheral Interface Timing Parameter Timing Requirements 1 t PPIx_CLK Width PCLKW 1 t PPI_CLK Period PCLK Timing Requirements t External Frame Sync Setup Before PPI_CLK SFSPE t External Frame Sync H old After PPI_CLK ...
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... Transmit Data Delay After TSCLK DDTE t Transmit Data Hold After TSCLK HDTE 1 Referenced to drive edge. Figure 13 on Page Rev. PrC | Page April 2004 ADSP-BF561 Min Max 3.0 3.0 3.0 3.0 4.5 15.0 Min Max TBD TBD 6.0 0.0 4.5 15.0 Min Max 1 10 ...
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... ADSP-BF561 Table 22. Serial Ports—Internal Clock Parameter Switching Characteristics t TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS) DFS I t TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS) HOFS I t Transmit Data Delay After TSCLK DDT I t Transmit Data Hold After TSCLK HDT I t TSCLK/RSCLK Width ...
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... RFS t t SDRI SAMPLE EDGE TCLK t t SFSI HFSI TFS DT TCLK/RCLK TCLK/RCLK Figure 13. Serial Ports Rev. PrC | Page April 2004 ADSP-BF561 DATA RECEIVE— EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKW t DFSE FSE SFSE HFSE t t SDRE HDRE DATA TRANSMIT — EXTERNAL CLOCK ...
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... ADSP-BF561 EXTERNAL RFS WITH MCE = 1, MFD = 0 RSCLK RFS DT LATE EXTERNAL TFS TSCLK TFS DT DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE/I t DDTENFS t HDTE/I 1ST BIT t DDTLFSE DRIVE SAMPLE DRIVE t HOFSE/I t SFSE/I t DDTE/I t DDTENFS t HDTE/I 1ST BIT t DDTLFSE Figure 14. External Late Frame Sync (Frame Sync Setup < t Rev ...
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... SFSE/I HOFSE/I t DDTE/I t DTENLSCK t HDTE/I 1ST BIT t DDTLSCK DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE/I t DTENLSCK t HDTE/I 1ST BIT t DDTLSCK Figure 15. External Late Frame Sync (Frame Sync Setup > t Rev. PrC | Page April 2004 ADSP-BF561 2ND BIT 2ND BIT 2) SCLK/ ...
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... ADSP-BF561 Serial Peripheral Interface (SPI) Port—Master Timing Table 25 and Figure 16 describe SPI port master operations. Table 25. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Timing Requirements t Data input valid to SCK edge (data input setup) SSPIDM t SCK sampling edge to data input invalid ...
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... MSB VALID (INPUT SPICLK SPICLM t SPICHM t t DDSPIDM HDSPIDM MSB t t HSPIDM SSPIDM MSB VALID t DDSPIDM t HSPIDM LSB VALID Figure 16. Serial Peripheral Interface (SPI) Port—Master Timing Rev. PrC | Page April 2004 ADSP-BF561 t t HDSM SPITDM LSB t HSPIDM LSB VALID t HDSPIDM LSB ...
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... ADSP-BF561 Serial Peripheral Interface (SPI) Port—Slave Timing Table 26 and Figure 17 describe SPI port slave operations. Table 26. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements t Serial clock high period SPICHS t Serial clock low period SPICLS t Serial clock period SPICLK ...
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... HDSPID DDSPID MSB SSPID HSPID MSB VALID t DDSPID MSB t SSPID MSB VALID LSB VALID Figure 17. Serial Peripheral Interface (SPI) Port—Slave Timing Rev. PrC | Page April 2004 ADSP-BF561 t t SPICLK HDS SPITDS t DSDHI LSB t HSPID SSPID LSB VALID t DSDHI LSB t HSPID ...
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... ADSP-BF561 Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure 18 describes UART port receive and transmit operations. The maximum baud rate is SCLK/16. As shown in there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART ...
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... HTO CLKOUT TMRx (PWM OUTPUT MODE) TMRx (WIDTH CAPTURE AND EXTERNAL CLOCK MODES equals (2 –1) cycles. HTO t HTO Figure 19. Timer PWM_OUT Cycle Timing Rev. PrC | Page April 2004 ADSP-BF561 Min Max Unit 1 SCLK cycles 1 SCLK cycles –1) SCLK cycles ...
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... ADSP-BF561 Programmable Flags Cycle Timing Table 28 and Figure 20 describe programmable flag operations. Table 28. Programmable Flags Cycle Timing Parameter Timing Requirement t Flag input pulsewidth WFI Switching Characteristic t Flag output delay from CLKOUT low DFO CLKOUT PF (OUTPUT) PF (INPUT) t DFO FLAG OUTPUT t WFI FLAG INPUT Figure 20 ...
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... TFS0-1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPIxD7-0. TCK TMS TDI TDO SYSTEM INPUTS t SYSTEM OUTPUTS TCK t t STAP HTAP t DTDO t t SSYS HSYS DSYS Figure 21. JTAG Port Timing Rev. PrC | Page April 2004 ADSP-BF561 Min Max Unit TCK cycles ...
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... Note also that it is not common for an application to have 100%,or even 50%, of the outputs switching TBD A simultaneously. OUTPUT DRIVE CURRENTS Figure 22 ers of the ADSP-BF561. The curves represent the current drive capability of the output drivers as a function of output voltage. = 0V). DDINT in Figure Tim- Figure 23 ...
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... Choose DECAY the difference between the ADSP-BF561's output volt- age and the input threshold for the device requiring the hold time. A typical V will be 0 the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line) ...
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... ADSP-BF561 CAPACITIVE LOADING Output delays and holds are based on standard capacitive loads all pins (see Figure 26 on Page graphically how output delays and holds vary with load capaci- tance (Note that this graph or derating does not apply to output disable delays; see ...
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... G11 ADDR03 DATA10 G12 DATA15 DATA8 G13 DATA14 DATA12 G14 GND DATA9 G15 DATA13 DATA11 G16 VDDEXT Rev. PrC | Page April 2004 ADSP-BF561 MBGA Pin Name Pin No. D01 PPI1D13/PF45 D02 PPI1D15/PF47 D03 PPI1SYNC3 D04 ADDR23 D05 GND D06 GND D07 ADDR09 ...
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... ADSP-BF561 Table 31. 256-Lead MBGA Pin Assignments (Continued) MBGA Pin Name MBGA Pin No. Pin No. J01 VROUT0 K01 J02 VROUT1 K02 J03 PPI1D2 K03 J04 PPI1D3 K04 J05 PPI1D1 K05 J06 VDDEXT K06 J07 GND K07 J08 VDDINT K08 J09 VDDINT K09 J10 ...
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... PF13 PF2/SPISEL2/TMR2 AF12 PF15/EXT CLK PF4/SPISEL4/TMR4 AF13 NMI1 PF6/SPISEL6/TMR6 AF14 TCK PF8 AF15 TDI PF10 AF16 TMS Rev. PrC | Page April 2004 ADSP-BF561 MBGA Pin Name Pin No. AF17 SLEEP AF18 NMI0 AF19 SCK AF20 TX/PF26 AF21 RSCLK1/PF30 AF22 DR1PRI AF23 TSCLK1/PF31 ...
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... ADSP-BF561 Table 32. 297-Lead PBGA Pin Assignments (Continued) MBGA Pin Name MBGA Pin No. Pin No. B23 ABE3/SDQM3 G01 B24 ADDR07 G02 B25 GND G25 B26 ADDR05 G26 C01 PPI1SYNC3 H01 C02 PPI1CLK H02 C03 GND H25 C04 GND H26 C05 GND J01 C22 ...
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... U25 DATA24 PPI1D2 U26 DATA27 VDDEXT V01 PPI2SYNC3 VDDEXT V02 PPI1D0 VDDEXT V25 DATA26 VDDEXT V26 DATA29 Rev. PrC | Page April 2004 ADSP-BF561 MBGA Pin Name Pin No. W01 PPI2SYNC1/TMR10 W02 PPI2SYNC2/TMR11 W25 DATA28 W26 DATA31 Y01 PPI2D15/PF39 Y02 PPI2D14/PF38 Y25 DATA30 ...
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... ADSP-BF561 OUTLINE DIMENSIONS Dimensions in the outline dimension figure are shown in millimeters. a 12.00 BSC SQ A1 BALL PAD CORNER TOP VIEW 1.70 1.51 1.36 SIDE VIEW NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-225, WITH NO EXACT PACKAGE SIZE AND EXCEPTION TO PACKAGE HEIGHT. ...
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... DETAIL A 0.20 MAX COPLANARITY BALL DIAMETER Figure 30. 297-Ball PBGA Grid Array Instruction Rate 600 MHz 500 MHz 500 MHz Rev. PrC | Page April 2004 ADSP-BF561 25.00 BSC SQ 8. BOTTOM VIEW 0.40 MIN SEATING PLANE 0.70 DETAIL A 0.60 0.50 Operating Voltage ...
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... ADSP-BF561 Rev. PrC | Page April 2004 Preliminary Technical Data ...