SAA4952WP Philips Semiconductors, SAA4952WP Datasheet
SAA4952WP
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SAA4952WP Summary of contents
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... DATA SHEET SAA4952WP Memory controller Objective specification File under Integrated Circuits, IC02 INTEGRATED CIRCUITS 1997 Jun 10 ...
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... The microcontroller receives commands via the 2 I C-bus. Due to this fact the START and STOP conditions of the main output control signals are programmable and the SAA4952WP can be set in different function modes depending on the TV feature concept that is used. 4) conversion PARAMETER PACKAGE ...
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... MHz) 43 LLD (32, 36 MHz) 1997 Jun 10 ALE WRD MICROCONTROLLER INTERFACE ACQUISITION HORIZONTAL ACQUISITION DEFLECTION TIMING HORIZONTAL LOGIC 2, 10, 23 DD1 to V DD4 Fig.1 Block diagram. 3 Objective specification SAA4952WP SAA4952WP PROCESSING HWE1 TIMING 16 VACQS 8 LOGIC VWE1 VERTICAL TIMING VWE2 DISPLAY 15 VRE1 VERTICAL ...
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... Most Significant Bit) I line-locked clock signal input (deflection part) ground 3 O horizontal reference signal output (deflection part) supply voltage 4 O horizontal synchronization signal output (deflection part) O vertical synchronization signal output (deflection part) I vertical synchronization signal input (acquisition part) 4 Objective specification SAA4952WP DESCRIPTION ...
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... Jun 10 I/O I test input I select single clock system input O reset write signal output (memory 1) I line-locked clock signal input (display part) ground SAA4952WP Fig.2 Pin configuration. 5 Objective specification SAA4952WP DESCRIPTION 39 VACQ 38 VDFL 37 HDFL V DD4 36 35 HRDFL V SS3 34 33 LLDFL MHA723 ...
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... Philips Semiconductors Memory controller FUNCTIONAL DESCRIPTION The SAA4952WP is a memory controller intended to be used for scan conversion in TV receivers. This conversion is performed from 50 to 100 Hz or from 60 to 120 Hz. Besides the doubling of the field frequency a progressive scan conversion can be activated (50 Hz/1250 lines or 60 Hz/1050 lines) ...
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... To obtain this data, the microcontroller sends the address 80H (read mode) which puts the SAA4952WP in output mode for the next address/data cycle. For this one cycle the WRD pin works as a RDN pin. The microcontroller is able to read the length of the incoming fields ...
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... MSB of VDSTO field length to be set by the microcontroller in the generator mode (lower bits); bit 0 = LSB field length to be set by the microcontroller in the generator mode; bit 0: bit 8 of field length bit 1: bit 9 of field length (MSB) 8 Objective specification SAA4952WP FUNCTION ...
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... HD (LSB) bit 7: fine delay of HD (MSB) horizontal pulse 1 for frame synchronization, 8-bit resolution horizontal pulse 2 for frame synchronization, 8-bit resolution horizontal pulse 3 for frame synchronization, 8-bit resolution horizontal pulse 4 for frame synchronization, 8-bit resolution 9 Objective specification SAA4952WP FUNCTION ...
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... BPRW = 0: AND connection HRDFL and HWE2 BPRW = 1: AND connection HRDFLN and HWE2 bit 6: BVRA: Blanking Vertical Reset Acquisition BVRA = 0: reset blanking disabled BVRA = 1: reset blanking enabled bit 7: BVRD: Blanking Vertical Reset Display BVRD = 0: reset blanking disabled BVRD = 1: reset blanking enabled 10 Objective specification SAA4952WP FUNCTION ...
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... LSB of display field count bit 3: field recognition for incoming source bit 4: MSB of display field count result of field length measurement (lower bits) 11 Objective specification SAA4952WP FUNCTION FUNCTION FUNCTION ...
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... IMPIP = 1: MPIP mode active number of PIPs INPIP = MPIP INPIP = MPIP GMOD = 0: normal operation GMOD = 1: generator mode for display; field length measurement is disabled FSA0 FSD0 Objective specification SAA4952WP REMARKS ) a FREQUENCY (MHz) 12.0 13.5 16.0 18.0 FREQUENCY (MHz) 27.0 27.0 32.0 36.0 ...
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... Notes 1. VFS: Vertical Frequency Select; register MODE1; bit 7. 2. SSC: Select Single Clock SAA4952WP input pin 41. 3. DR: Display Raster; register MODE1; bit 0. 1997 Jun 10 display raster stop writing to memory 1; still picture mode; STROBE signal can override still picture mode stop writing to memory 2; still picture mode select mode of display signal at pin 17 ...
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... TDA9141) and the horizontal reference signal (HRA) supplied by the SAA4952WP. SWC1 The acquisition clock input signal LLA is connected via the memory controller circuit SAA4952WP. LLA is internally buffered and output as serial write clock for memory 1. Additionally SWC1 is used as a clock signal for the analog-to-digital converter (e.g. TDA8755). ...
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... CLV = (8Nr + 2)LLA r CLV = (8Nf + 2)LLA f HWE1 = (4Nr + 2)LLA r HWE1 = (4Nf + 2)LLA f (1) HVACQS1 = (8N + 2)LLA (2) HVACQS2 = (8M + 2)LLA 15 Objective specification SAA4952WP PROGRAMMING RANGE 0 Nr < 191 0 Nf < 191 0 Nr < 383 0 Nf < 383 0 N < 191 0 M < 191 0 Nr < 215 0 Nf < 215 0 Nr < 431 0 Nf < ...
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... The Horizontal Reference Display pulse (HRD) has a duty cycle of 50% and a frequency of 32 kHz. HRD is the reference pulse for the horizontal timing of the control signals RE1, RE2, WE2, HD and BLND generated by the display part of the SAA4952WP in the event of a three-clock system with a selected display frequency MHz. HVSP The vertical display counter is incremented with every HVSP pulse (see Fig ...
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... The memory controller supplies a display related output which can generate, depending on the microcontroller initialization, three different signals. The desired mode is activated via microcontroller register MODE1 (control bits SD0 and SD1). Table 14 Mode setting of SAA4952WP output HVCD SD1 SD0 MODE OF OUTPUT PIN horizontal output signal HD ...
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... This is the write/read enable control signal supplied by the microcontroller. The HIGH-to-LOW transition of WRD indicates valid data The SAA4952WP is controlled by the bidirectional parallel port bus microcontroller. Address and data are transmitted sequentially on the parallel bus. TEST The TEST input pin has to be connected to ground. SDP The SDP input pin has to be connected to ground for a three-clock system ...
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... Source for SRC depends on the setting of register MODE0 and the level on the SDP pin. handbook, full pagewidth HRA CLV CLV f HWE1 r HWE1 HVACQS1 HVACQS 1997 Jun Typical case conditions: V amb LOAD t h(min) (pF) (ns CLV r HWE1 f HVACQS2 Fig.4 Horizontal acquisition timing. 19 Objective specification SAA4952WP = 5 V and amb t t h(typ) pd(max) (ns) (ns pd(typ) (ns ...
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... HRD or HRDFL HDSP r (1) HDSP (2) HVSP n (2) HVSP (1) HDSP = BLND, HRE and HWE2. (2) HVSP consists of the 4 pulses HVSP1 to HVSP4 (HVSP 1997 Jun 10 ( (WE1) Fig.5 Vertical acquisition timing. HDSP Fig.6 Programmable horizontal display signals. 20 Objective specification SAA4952WP MHA726 MHA727 ...
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... VACQ VDSP r VDSP RSTW2 Fig.7 Vertical display timing [VDSP = V(WE2) and V(RE1/2)]. handbook, full pagewidth HRDFL HDFL 64 LLDFL Fig.8 Horizontal deflection timing (example for 27 MHz). 1997 Jun 10 VDSP f 1728 LLDFL 864 LLDFL 64 LLDFL 21 Objective specification SAA4952WP MHA728 MHA729 ...
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... T storage temperature stg T operating ambient temperature amb THERMAL CHARACTERISTICS SYMBOL R thermal resistance from junction to case th j-c 1997 Jun Fig.9 Timing diagram. PARAMETER PARAMETER 22 Objective specification SAA4952WP MHA733 MIN. MAX. UNIT 0.5 +6 MHz 40 +125 VALUE UNIT ...
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... MHz for LLDFL, if the data at the microcontroller port P0 to P7, ALE and WRD is supplied from a min microcontroller clocked with 12 MHz. 2. For SRC mA. o APPLICATION INFORMATION Figure 10 illustrates a block diagram of the application environment of the memory controller SAA4952WP. The full option chip set of the new TV feature system 2 controlled by the I C-bus includes the following circuits: TDA8755 ADC. SAA4955TJ 3 Mbit video RAM ...
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... Philips Semiconductors Memory controller Application diagrams dbook, full pagewidth 1997 Jun 10 HVCD RE1 SRC IE2 RSTW1 WE1 IE1 SWC1 CLV 24 Objective specification SAA4952WP ...
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... MEMORY 1 12 PROZONIC 12 SAA4955TJ 1 SAA4990H VERTICAL ZOOM LINE FLICKER REDUCTION NOISE AND CROSS-COLOUR MEMORY 2 12 REDUCTION SAA4955TJ CONTROL MEMORY VCO2 CONTROLLER SAA4952WP DATA 2 8 SNERT-bus MICROCONTROLLER S87C654 MHA731 Y VEDA2 video processor SAA7165 U TDA4780 CTI RGB output stages Y-PEAKING TDA6111 V DAC 2 I C-bus ...
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... SAA4991WP 12 SAA4955TJ 1 MOTION ESTIMATION AND COMPENSATION LINE FLICKER REDUCTION NOISE AND CROSS-COLOUR MEMORY 2 12 REDUCTION SAA4955TJ 1 VERTICAL ZOOM CONTROL MEMORY VCO2 CONTROLLER SAA4952WP DATA 2 8 SNERT-bus MICROCONTROLLER S87C654 MHA732 Y VEDA2 video processor SAA7165 U TDA4780 CTI RGB output stages Y-PEAKING TDA6111 DAC ...
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... EUROPEAN PROJECTION Objective specification SAA4952WP SOT187 (1) ( max. max. 0.10 2.16 2. 0.085 0.085 ISSUE DATE 92-11-17 95-02-25 ...
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... Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 28 Objective specification SAA4952WP ...
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... Philips customers using or selling these products for use in such applications their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Jun 10 29 Objective specification SAA4952WP ...
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... Philips Semiconductors Memory controller 1997 Jun 10 NOTES 30 Objective specification SAA4952WP ...
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... Philips Semiconductors Memory controller 1997 Jun 10 NOTES 31 Objective specification SAA4952WP ...
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... Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...