MC68HC705C8ACS

Manufacturer Part NumberMC68HC705C8ACS
ManufacturerFreescale Semiconductor, Inc
MC68HC705C8ACS datasheet
 
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Freescale Semiconductor, Inc.
11.9.1 SPI Data Register
The SPDR shown in
received by the SPI. Writing a byte to the SPDR places the byte directly
into the SPI shift register.
Address:
Read:
Write:
Reset:
11.9.2 SPI Control Register
Address:
Read:
Write:
Reset:
SPIE — SPI Interrupt Enable Bit
This read/write bit enables SPI interrupts. Reset clears the SPIE bit.
MC68HC705C8A — Rev. 3
MOTOROLA
For More Information On This Product,
Figure 11-7
is the read buffer for characters
$000C
Bit 7
6
5
4
Bit 7
Bit 6
Bit 5
Bit 4
Unaffected by reset
Figure 11-7. SPI Data Register (SPDR)
Enables SPI interrupt requests
Enables the SPI
Configures the SPI as master or slave
Selects serial clock polarity, phase, and frequency
$000A
Bit 7
6
5
4
SPIE
SPE
MSTR
0
0
0
= Unimplemented
Figure 11-8. SPI Control Register (SPCR)
1 = SPI interrupts enabled
0 = SPI interrupts disabled
Serial Peripheral Interface (SPI)
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Serial Peripheral Interface (SPI)
SPI I/O Registers
3
2
1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
3
2
1
Bit 0
CPOL
CPHA
SPR1
SPR0
U
U
U
U
U = Unaffected
Technical Data