W83637HF-AW Winbond, W83637HF-AW Datasheet
W83637HF-AW
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W83637HF-AW Summary of contents
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... Winbond LPC I/O W83637HF W83637HG Revision: 1.6 Date: 2006/03/22 ...
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... ADD Block Digram 1.2 ADD Chapter 4.1 Plug and Play Configuration 1.3 Add Chapter 9 DC Specification 1.4 Add Pb-free package 1.5 Remove 5VSB H/W monitor sensor function. 1.6 Correct GPIO pins to 21-pin, not 40-pin - I - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... FAN Speed Count and FAN Speed Control................................................. 29 6.4.1 Fan speed count..........................................................................................................29 6.4.2 Fan speed control........................................................................................................31 6.5 Smart Fan Control ...................................................................................... 32 6.5.1 Thermal Cruise mode ..................................................................................................32 6.5.2 Fan Speed Cruise mode..............................................................................................33 6.5.3 Manual Control Mode ..................................................................................................34 W83637HF/HG Publication Release Date: March, 2006 - II - Revision 1.6 ...
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... Voltage SMI# mode.....................................................................................................34 6.6.2 Fan SMI# mode...........................................................................................................34 6.6.3 The W83637HF temperature sensor 1(SYSTIN) SMI# interrupt has two modes ........35 6.6.4 The W83637HF temperature sensor 2(CPUTIN) and sensor 3(VTIN) SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. ..............................................36 6.7 OVT# Interrupt Mode .................................................................................. 37 6 ...
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... Logical Device D (MS/SD Card Interface) ..................................................127 9. ELECTRICAL CHARACTERISTICS .....................................................................................129 9.1 Absolute Maximum Ratings .......................................................................129 9.2 DC Characteristics.....................................................................................129 10. ORDERING INSTRUCTION.................................................................................................137 11. HOW TO READ THE TOP MARKING ..................................................................................138 12. PACKAGE DIMENSIONS ....................................................................................................140 13. APPENDIX A: APPLICATION CIRCUITS .............................................................................141 W83637HF/HG Publication Release Date: March, 2006 - IV - Revision 1.6 ...
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... GENERAL DESCRIPTION W83637HF/HG is the new generation of Winbond's LPC I/O products evolving product from Winbond’s most popular LPC I/O chip W83627HF/HG – which integrates the disk driver adapter, serial port (UART), keyboard controller (KBC), SIR, CIR, game port, MIDI port, hardware monitor, ACPI, On Now Wake-Up – ...
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... W83637HF/HG provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O port. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. W83637HF/HG is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide. ...
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... Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation • Programmable baud generator allows division of 1.8461 MHz and 24 MHz • Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz W83637HF/HG Publication Release Date: March, 2006 - -1) Revision 1.6 ...
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... Support two separate Joysticks • Support every Joystick two axis (X, Y) and two button (A, B) controllers MIDI Port • The baud rate is 31.25 K baud • 16-byte input FIFO • 16-byte output FIFO W83637HF/ -2, Phoenix MultiKey/42 Publication Release Date: March, 2006 - customer code Revision 1.6 ...
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... Build in Case open detection circuit • WATCHDOG comparison of all monitored values • Programmable hysteresis and setting points for all monitored items • Over temperature indicate output Windows 2000 TM Specification Version 1.03 TM ” and “Speed Cruise - 5 - W83637HF/HG TM ” TM Publication Release Date: March, 2006 Revision 1.6 II/III/4 ...
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... Automatic Power On voltage detection Beep • Issue SMI#, IRQ, OVT# to activate system protection • Winbond Hardware Doctor TM • Intel LDCM / Acer ADM Package • 128-pin PQFP TM Support TM compatible - 6 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... FDC Port MIDI URA, B GPIO IR KBC CIR HM PRT MS SC ACPI W83637HF/HG Floppy drive interface signals Serial port A, B interface signals IRRX IRTX CIRRX# Printer port interface signals Smart Card interface signals Secure Digital Memory Card interface signals Publication Release Date: March, 2006 ...
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... W83637HF/ W83637HF/ SUSLED/GP35 SUSLED/GP35 63 63 KDAT KDAT 62 62 KCLK KCLK 61 61 VSB VSB 60 60 KBRST KBRST 59 59 GA20M GA20M 58 58 MSRWLED/MSWPRO MSRWLED/MSWPRO 57 57 RIA# RIA DCDA# DCDA VSS VSS 54 54 PENKBC/SOUTA PENKBC/SOUTA 53 53 SINA SINA 52 52 PNPCSV/DTRA# PNPCSV/DTRA HEFRAS/RTSA# HEFRAS/RTSA DSRA# ...
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... TTL level input pin with internal pull up resistor. INc CMOS level input pin. INcd CMOS level input pin with internal pull down resistor. INcsu CMOS level Schmitt-trigger input pin with internal pull up resistor. PIN DESCRIPTION Publication Release Date: March, 2006 - 9 - W83637HF/HG Revision 1.6 ...
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... These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... The read data input signal from the FDD. This input pin is pulled up internally KΩ resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... EXTENSION FDD MODE: MOB2# This pin is for Extension FDD B; its function is the same as the MOB# pin of FDC. EXTENSION 2FDD MODE: MOB2# This pin is for Extension FDD A and B; its function is the same as the MOB# pin of FDC W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... TRAK0# pin of FDC pulled high internally. EXTENSION. 2FDD MODE: TRAK02# This pin is for Extension FDD A and B; its function is the same as the TRAK0# pin of FDC pulled high internally W83637HF/HG Refer to the description of the It is pulled high Refer to the description of the Refer to the description of the ...
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... This pin is for Extension FDD B; its function is the same as the DIR# pin of FDC. EXTENSION 2FDD MODE: DIR2# This pin is for Extension FDD A and B; its function is the same as the DIR# pin of FDC W83637HF/HG Refer to the description of the Publication Release Date: March, 2006 Revision 1.6 ...
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... An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output EXTENSION 2FDD MODE: This pin is a tri-state output W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... During power-on reset, this pin is pulled down internally and is defined as PNPCVS , which provides the power-on value for CR24 bit 0 ( PNPCVS ). A 4.7 kΩ is recommended if intends to pull up. (clear the default value of FDC, UARTs, PRT, Game port and MIDI port W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Gate A20 output. This pin is high after system reset. (KBC P21) Keyboard reset. This pin is high after system reset. (KBC P20) Keyboard Clock. Keyboard Data. PS2 Mouse Clock. PS2 Mouse Data W83637HF/HG A 4.7 kΩ resistor is Publication Release Date: March, 2006 Revision 1.6 ...
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... Battery voltage input. CASE OPEN. An active low input from an external device when t case is opened. This signal can be latched if pin VBAT is connect to battery, even W83637HF is power off 4.096V FSR Analog Inputs 4.096V FSR Analog Inputs 4.096V FSR Analog Inputs. Reference Voltage for temperature maturation. ...
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... Active-low, Joystick II switch input 1. (Default) General purpose I/O port 1 bit 1. Alternate Function Output: KBC P13 I/O port. Active-low, Joystick I switch input 1. (Default) General purpose I/O port 1 bit 0. Alternate Function Output: KBC P12 I/O port W83637HF/HG FUNCTION Publication Release Date: March, 2006 Revision 1.6 ...
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... MS function SD Data Line 0(DAT0) Smart Card C4 PIN General purpose I/O port 2 bit 1 MS card CLK output SD Card CLK output MS function SD Data Line 1(DAT 1) MS function SD Command Line(CMD) MS function SD Data Line 3(CD/DAT3 W83637HF/HG FUNCTION FUNCTION Publication Release Date: March, 2006 Revision 1.6 ...
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... This pin generates the PWROK signal while the VCC come in. (Default) General purpose I/O port 3 bit 2. This pin generates the PWRCTL# signal while the power failure. (Default) General purpose I/O port 3 bit 1. Chip Set sleep state input. General purpose I/O port 3 bit W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Analog VCC input. Internally supplier to all analog circuitry. Internally connected to all analog circuitry. The ground reference for all analog inputs.. Ground W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... The first interface uses LPC Bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and 6h. The other higher bits of these ports are set by W83637HF/HG itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: Index port ...
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... BANK 0 Chip ID Register 58h BANK 0 Temperature Sensor Type Configuration & Fan Divisor Bit2 Registers 59h,5Dh Figure 6.1: LPC interface access diagram - 25 - W83637HF/HG BANK 1 CPUTIN Temperature Control/Staus Registers 50h~56h BANK 2 VTIN Temperature Control/Staus Registers 50h~56h BANK 4 Interrupt Status & SMI Mask Registers ...
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... Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU V-core voltage, +3.3V, battery(pin 74) can directly connected to these analog inputs. The +12V voltage inputs should be reduced a factor with external resistors obtain the input range. As Figure 6.2 shows. W83637HF/HG Figure. 6.2 Publication Release Date: March, 2006 - 26 - ...
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... The Pin 114 is connected to the power supply VCC with +5V. There are two functions in this pin with 5V. The first function is to supply internal analog power in the W83637HF and the second function is that this voltage with 5V is connected to internal serial resistors to monitor the +5V voltage. The W83637HF internal two serial resistors are 34K ohms and 51K ohms so that input voltage to ADC is 3V which is less than 4 ...
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... III D- is connected to pin 111(CPUD-) and the pin D+ is connected to temperature sensor pin in the W83637HF. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the 2N3904 should be tied together to act as a thermal diode ...
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... That provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, PRM, and count. Figure 6.3 6 × 135 Count × RPM Divisor × RPM × Count Divisor Publication Release Date: March, 2006 - 29 - W83637HF/HG Revision 1.6 ...
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... Table 2 Figure 6.4 Publication Release Date: March, 2006 - 30 - W83637HF/HG 70% RPM Time for 70% 6160 9.84 ms 3080 19.48 ms 1540 38.96 ms 770 77.92 ms 385 155.84 ms 192 311. 623. 1246.72 ms ...
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... Fan speed control The W83637HF provides maximum 3 sets for fan PWM speed control. The duty cycle of PWM can be programmed by a 8-bit registers which are defined in the Bank0 Index 01h, Index 03h and Index 11h. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows. − ...
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... Thermal Cruise mode There are maximum 3 pairs of Temperature/FanPWM control at this mode: SYSTIN with FANPWM1, CPUTIN with FANPWM2, VTIN with FANPWM3. At this mode, W83637HF provides the Smart Fan system which can control the fan speed automatically depend on current temperature to keep it with in a specific range. At first a wanted temperature and interval must be set (ex. 55 ° ...
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... Fan Speed Cruise mode There are 3 pairs of FanSpeed/FanPWM control at this mode: FANIN1 with FANPWM1, FANIN2 with FANPWM2, FANIN3 with FANPWM3.At this mode, W83637HF provides the Smart Fan system which can control the fan speed automatically depend on current fan spesed to keep it with in a specific range. A wanted fan speed count and interval must be set (ex. 160 ± ...
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... SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 6.10) Figure 6.9 W83637HF/HG Figure 6.10 Publication Release Date: March, 2006 - 34 - ...
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... The W83637HF temperature sensor 1(SYSTIN) SMI# interrupt has two modes (1) Comparator Interrupt Mode Setting the T (Temperature Hysteresis) limit to 127°C will set temperature sensor 1 SMI# to HYST the Comparator Interrupt Mode. Temperature exceeds T interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an ...
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... The W83637HF temperature sensor 2(CPUTIN) and sensor 3(VTIN) SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. (1) Comparator Interrupt Mode Temperature exceeding T Interrupt Status Register. Once an interrupt event has occurred by exceeding T temperature remains above the T completed interrupt event has occurred by exceeding T occur again ...
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... OVT# output activated until the temperature is less than O causes the OVT# output activated indefinitely until reset by reading the OVT# will not be activated again.(Figure 6.16) HYST Figure 6. W83637HF/HG , then OVT# reset, and then temperature Publication Release Date: March, 2006 Revision 1.6 , then O ...
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... Bit 7-0: Data to be read from written to RAM and Register. Port x5h 00h Bit 6:0 Read/write , Bit 7: Reserved 8 bits Bit 5 Bit 4 Bit 3 Address Pointer (Power On default 00h Port x6h 00h Read/write 8 bits W83637HF/HG Data Bit 2 Bit 1 Bit Data Publication Release Date: March, 2006 Revision 1.6 ...
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... Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit. 40h 01h Read/write 8 bits START SMI#Enable RESERVED INT_Clear RESERVED RESERVED RESERVED INITIALIZATION - 39 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Register Location: Power on Default Value Attribute: Size: 41h 00h Read Only 8 bits 42h 00h Read Only 8 bits W83637HF/HG VCORE VIN1 +3.3VIN +5VIN SYSTIN CPUTIN FAN1 FAN2 VIN2 Resvered Reserved Fan3 CaseOpen VTIN TAR1 TAR2 Publication Release Date: March, 2006 Revision 1.6 ...
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... SMI# Mask Register 1 Index 43h Register Location: Power on Default Value Attribute: Size: Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt 43h FFh Read/Write 8 bits W83637HF/ VCORE VIN1 +3.3VIN +5VIN SYSTIN CPUTIN FAN1 FAN2 Publication Release Date: March, 2006 Revision 1.6 ...
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... Bit 7: Set 1, clear case open event. This bit self clears after clearing case open event. Bit 6-0:Reserved. This bit should be set to 0. 44h FFh Read/Write 8 bits 46h 00h Read/Write 8 bits Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chassis Clear - 42 - W83637HF/HG VIN2 Revered Revered FAN3 CaseOpen VTIN TAR1 TAR2 Publication Release Date: March, 2006 Revision 1.6 ...
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... Bit 3-0: CPU Vcore ID [3:0]. The VID value is written by BIOS if the VID value can be detected. After the VID value is written, Software/AP can use this information to identify the Vcore voltage of the CPU. Note: Please refer to Bank0 CR[5Dh] , Fan divisor table VID[0] VID[1] VID[2] VID[3] FAN1DIV_B0 FAN1DIV_B1 FAN2DIV_B0 FAN2DIV_B1 - 43 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... VIN1 High Limit 2Eh VIN1 Low Limit 2Fh +3.3VIN High Limit 30h +3.3VIN Low Limit 31h +5VIN High Limit 32h +5VIN Low Limit 33h VIN2 High Limit 34h VIN2 Low Limit 35h Reserved Description Publication Release Date: March, 2006 - 44 - W83637HF/HG Revision 1.6 ...
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... Bit 0 : CPU Vcore ID [4]. The VID value is written by BIOS if the VID value can be detected. After the VID value is written, Software/AP can use this information to identify the Vcore voltage of the CPU. Description 49h 03h bit<7:1> Read Only; bit<0> Read/Write 8 bits W83637HF/HG VID[4] DID<6:0> Publication Release Date: March, 2006 Revision 1.6 ...
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... ADC clock select 0.35 Khz. (22.5K/64) Bit 3-2: These two bits should be set to 01h. The default value is 01h. Bit 1-0: Reserved. 4Bh <7:0> 44h. Read/Write 8 bits Reserved Reserved Reserved Reserved ADCOVSEL ADCOVSEL FAN3DIV_B0 FAN3DIV_B1 - 46 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... CPUTIN OVT output through pin OVT#. Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1: Reserved. Bit 0: Reserved. 4Ch 18h Read/Write 8 bits Reserved Reserved OVTPOL DIS_OVT2 DIS_OVT3 EN_T1_ONE T2T3_INTMode Reserved - 47 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Bit 0: FAN 1 Input Control. Set to 1, pin 113 acts as FAN clock input, which is default value. Set to 0, this pin 113 acts as FAN control signal and the output value of FAN control is set by this register bit 1. 4Dh 15h Read/Write 8 bits W83637HF/HG FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 Reserved Reserved Publication Release Date: March, 2006 Revision 1.6 ...
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... Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h. Winbond Test Register -- Index 50h - 55h (Bank 0) 4Eh 80h Read/Write 8 bits BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS 4Fh <15:0> = 5CA3h Read Only 16 bits VIDH VIDL - 49 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Bit 0: BEEP output control for CPUVCORE if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. 56h 00h Read/Write 8 bits EN_VCORE_BP EN_VIN1_BP EN_+3.3VIN_BP EN_+5VIN_BP EN_SYSTIN_BP EN_CPUTIN_BP EN_FAN1_BP EN_FAN2_BP - 50 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Chip ID -- Index 58h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 Bit 7: Winbond Chip ID number. Read this register will return 80h 58h 80h Read Only 8 bits W83637HF/HG EN_VIN2_BP Reserved Reserved EN_FAN3_BP EN_CASO_BP EN_VTIN_BP Reserved EN_GBP CHIPID Publication Release Date: March, 2006 Revision 1.6 ...
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... Pentium II CPU compatible thermal diode. Set this bit to 0, select 2N3904 bipolar diode. Bit 3-0: Reserved Reserved -- Index 5Ah (Bank 0) Reserved -- Index 5Bh (Bank 0) Reserved -- Index 5Ch (Bank 0) 59h 70h Read/Write 8 bits W83637HF/HG 0 Reserved Reserved Reserved Reserved SELPIIV1 SELPIIV2 SELPIIV3 Reserved Publication Release Date: March, 2006 Revision 1.6 ...
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... VBAT reading value register after one monitor cycle time. Fan divisor table: Bit 2 Bit 1 Bit 5Dh 00h Read/Write 8 bits EN_VBAT_MNT DIODES1 DIODES2 DIODES3 Reserved FANDIV1_B2 FANDIV2_B2 FANDIV3_B2 Fan Divisor Bit 2 Bit 1 Bit W83637HF/HG Fan Divisor 128 Publication Release Date: March, 2006 Revision 1.6 ...
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... CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank1) Register Location: 51h Attribute: Read Only Size: 8 bits 7 Bit 7: Temperature <0> of CPUTIN sensor, which is low byte, means 0.5 Bit 6-0: Reserved W83637HF/HG TEMP<8:1> ° C. Reserved TEMP<0> ° C. Publication Release Date: March, 2006 Revision 1.6 ...
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... Power on Default Value Attribute: Size: 7 Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 52h 00h 8 bits STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved 53h 4Bh Read/Write 8 bits W83637HF/HG THYST<8:1> Publication Release Date: March, 2006 Revision 1.6 ...
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... CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1) Register Location: Power on Default Value Attribute: Size: 7 Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. 54h 00h Read/Write 8 bits 55h 50h Read/Write 8 bits W83637HF/HG Reserved THYST<0> TOVF<8:1> Publication Release Date: March, 2006 Revision 1.6 ...
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... VTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2) Register Location: 50h Attribute: Read Only Size: 8 bits 7 Bit 7: Temperature <8:1> of sensor 2, which is high byte, means 1 56h 00h Read/Write 8 bits TOVF<0> W83637HF/HG Reserved TEMP<8:1> ° C. Publication Release Date: March, 2006 Revision 1.6 ...
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... Bit 1: Read/Write - OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor 52h 00h 8 bits W83637HF/HG Reserved TEMP<0> ° C. STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved Publication Release Date: March, 2006 Revision 1.6 ...
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... VTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) Register Location: Power on Default Value Attribute: Size: 7 Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. 53h 4Bh Read/Write 8 bits 54h 00h Read/Write 8 bits W83637HF/HG THYST<8:1> Reserved THYST<0> Publication Release Date: March, 2006 Revision 1.6 ...
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... VTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56(Bank2) Register Location: Power on Default Value Attribute: Size: 7 Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. 55h 50h Read/Write 8 bits 56h 00h Read/Write 8 bits W83637HF/HG TOVF<8:1> Reserved TOVF<0> Publication Release Date: March, 2006 Revision 1.6 ...
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... Bit 0: A one disables the corresponding interrupt status bit for SMI interrupt. 50h 00h Read Only 8 bits 51h 00h Read/Write 8 bits W83637HF/HG Reserved VBAT TAR3 Reserved Reserved Reserved Reserved Reserved . Reserved VBAT Reserved Reserved TAR3 Reserved Reserved Reserved Publication Release Date: March, 2006 Revision 1.6 ...
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... CPUTIN Temperature Sensor Offset Register -- Index 55h (Bank 4) 53h 00h Read/Write 8 bits Reserved EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved 54h 00h Read/Write 8 bits W83637HF/HG OFFSET<7:0> Publication Release Date: March, 2006 Revision 1.6 ...
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... Reserved Register -- Index 57h--58h (Bank4) Real Time Hardware Status Register I -- Index 59h (Bank 4) 55h 00h Read/Write 8 bits 56h 00h Read/Write 8 bits W83637HF/HG OFFSET<7:0> OFFSET<7:0> Publication Release Date: March, 2006 Revision 1.6 ...
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... Bit 0: VCORE Voltage Status. Set 1, the voltage of VCORE is over the limit value. Set 0, the voltage of VCORE is in the limit range. Real Time Hardware Status Register II -- Index 5Ah (Bank 4) 59h 00h Read Only 8 bits VCORE_STS VIN1_STS +3.3VIN_STS +5VIN_STS SYSTIN_STS CPUTIN_STS FAN1_STS FAN2_STS - 64 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Bit 0: Vin2 Voltage Status. Set 1, the voltage of VIN2 is over the limit value. Set 0, the voltage of VIN2 is in the limit range. Real Time Hardware Status Register III -- Index 5Bh (Bank 4) 5Ah 00h Read Only 8 bits W83637HF/HG VIN2_STS Reserved Reserved FAN3_STS CASE_STS VTIN_STS TAR1_STS TAR2_STS TM . Set 0, the TM . Set 0, the Publication Release Date: March, 2006 Revision 1.6 ...
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... VBAT is during the limit range. Bit 0: Reserved. Reserved Register -- Index 5Ch (Bank 4) Reserved Register -- Index 5Dh (Bank 4) 5Bh 00h Read Only 8 bits Reserved VBAT_STS TAR3 Reserved Reserved Reserved Reserved Reserved - 66 - W83637HF/ Set 0, the temperature Publication Release Date: March, 2006 Revision 1.6 ...
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... Bit 6-1: FANPWM1 Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. Description 00h 01h Read/Write 8 bits PWM_CLK_SEL1 SourceCloc k 1 ∗ scaleDivid er 256 - 67 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Bit 6-1: FANPWM2 Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h FFh Read/Write 8 bits 02h 01h Read Only 8 bits PWM_CLK_SEL1 SourceCloc k 1 ∗ scaleDivid er 256 - 68 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Set 10, FANPWM2 is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit3-2: FANPWM1 mode control. Set 00, FANPWM1 is as Manual Mode. (Default). Set 01, FANPWM1 is as Thermal Cruise Mode. 03h FFh Read/Write 8 bits 04h 00h Read/Write 8 bits W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... SYSTIN Target Temperature Register/ Fan 1 Target Speed Register -- Index 05h (Bank 0) Register Location: Power on Default Value Attribute: Size (1). When at Thermal Cruise mode: Bit7: Reserved. Bit6-0: SYSTIN Target Temperature. (2). When at Fan Speed Cruise mode: Bit7-0: Fan 1 Target Speed. 05h 00h Read/Write 8 bits W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Bit7-4: Tolerance of CPUTIN Target Temperature. Bit3-0: Tolerance of SYSTIN Target Temperature. (2). When at Fan Speed Cruise mode: Bit7-4: Tolerance of Fan 2 Target Speed. Bit3-0: Tolerance of Fan 1 Target Speed. 06h 00h Read/Write 8 bits 07h 00h Read/Write 8 bits W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Power on Default Value Attribute: Size When at Thermal Cruise mode, FANPWM2 duty cycle will decreases to below this value. This register should be written a non-zero minimum PWM stop duty cycle. 08h 01h Read/Write 8 bits 09h 01h Read/Write 8 bits W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... Power on Default Value Attribute: Size When at Thermal Cruise mode, FANPWM2 duty cycle will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan. 0Ah 01h Read/Write 8 bits 0Bh 01h Read/Write 8 bits W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
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... When at Thermal Cruise mode, this register determines the time of which FANPWM2 duty is from stop duty cycle to 0 duty cycle. The unit of this register is 0.1 second. The default time is 6 seconds. 0Ch 3Ch Read/Write 8 bits 0Dh 3Ch Read/Write 8 bits W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 80
... Fan PWM Duty Cycle Step Up Time Register -- Index 0Fh (Bank 0) Register Location: Power on Default Value Attribute: Size This register determines the speed of FAN PWM increasing the duty cycle in Smart Fan Control mode. 0Eh 0Ah Read/Write 8 bits 0Fh 0Ah Read/Write 8 bits W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 81
... Bit 7-0: FANPWM3 duty cycle control. Write FF, duty cycle is 100%. Write 00, duty cycle is 0%. FAN Configuration Register II -- Index 12h (Bank 0) 10h 01h Read Only 8 bits PWM_CLK_SEL3 SourceCloc k 1 ∗ scaleDivid er 256 11h FFh Read/Write 8 bits W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 82
... Bit 0: FANPWM3 output mode selection. Set to 0, FANPWM3 pin is as output pin so that it can drive a logical high or low signal. Set to 1, FANPWM3 pin is as open-drain pin which can only drive a logical low signal. 12h 00h Read/Write 8 bits W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 83
... Register Location: Power on Default Value Attribute: Size (1).When at Thermal Cruise mode: Bit3-0: Tolerance of VTIN Target Temperature. (2).When at Fan Speed Cruise mode: Bit3-0: Tolerance of Fan 3 Target Speed. 13h 00h Read/Write 8 bits 14h 00h Read/Write 8 bits W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 84
... Power on Default Value Attribute: Size When at Thermal Cruise mode, FANPWM3 duty cycle will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan. 15h 01h Read/Write 8 bits 16h 01h Read/Write 8 bits W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 85
... Bit 3-1: Reserved. Bit 0: CPUVCORE pin voltage detection method selection. Set to 1, VRM9 formula is selected. Set to 0, VRM8 formula is selected. This bit default value is 1. 17h 3Ch Read/Write 8 bits 18h 43h Read/Write 8 bits W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 86
... Winbond's implementation of Smart Card Reader interface is based on ISO/IEC 7816-3 standard and fully compliant with PC/SC Specifications 1.0. Except for pins specified in ISO/IEC 7816-3, W83637HF/HG's SCI also includes SCPSNT (Smart Card Present) monitoring status of card insertion/extraction, SCLED (Smart Card traffic LED display) which is active high when host is accessing information to/from card, and two general-purpose I/O pins SCC4 and SCC8 (only available in W83637HF/HG) for users to design application-specific functions ...
Page 87
... SCKFS1 SCKFS0 Cold Reserved reset (note) (note Bit 7 Bit 6 Bit 5 Bit Bit 15 Bit 14 Bit 13 Bit W83637HF/ Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 ESCPTI ESCSRI ETBREI ERDRI (note) (note) (note) (note INTS2 INTS1 INTS0 Interrupt pending (note) (note) (note) TxFRST ...
Page 88
... SCPTI – SCPSNT toggle interrupt status. SC_SEL – Smart Card socket selection. TBRE – TBR (write only Transmitter Buffer Register at base address + 0) empty status. TSRE – TSR (Transmitter shift register) empty status. TxFRST – Transmitter FIFO reset. W83637HF/HG Publication Release Date: March, 2006 - 83 - Revision 1.6 ...
Page 89
... SCIODIR (bit 1 of ECR at base address + 7) set to "0". The depth of transmitter FIFO is 16 bytes Bit 7 ~ bit 0: Access port for receiver FIFO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 90
... Bit 3: ESCPTI means SCPSNT toggle interrupt enable bit. A rising/falling edge of SCPSNT signal triggers an interrupt if this bit is set to "1" SCPSNT toggle interrupt is disabled SCPSNT toggle interrupt is enabled ERDRI ETBREI ESCSRI ESCPTI SCC4_IO SCC8_IO SCC4 SCC8 - 85 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 91
... User may also find FIFO enable/disabled status reflecting what is set in bit 0 of SCFR (write only Smart Card FIFO Register at base address + 2 when BDLAB = 0) and SCPSNT line status Interrupt pending INTS0 INTS1 INTS2 SCPTI SCPSNT FIFO enabled FIFO enabled - 86 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 92
... RBR data ready 2. FIFO interrupt active level reached Data present in Rx FIFO for 4-character period of time since last access of Rx FIFO. TBR empty - 87 - W83637HF/HG Clear interrupt condition - Read SCSR 1. Read RBR 2. Read RBR until FIFO is under active level Read RBR 1. Write data to TBR 2 ...
Page 93
... Bit 0: This bit enables FIFO of Smart Card interface. It should be set to a logical "1" before other bits of SCFR are programmed. Default is "0" Enable FIFO RxFRST TxFRST Reserved Reserved Reserved RxTL0 RxTL1 RxTL0 Rx FIFO Interrupt Active Level (Bytes This bit is self-cleared to "0" after being set to "1" W83637HF/ Publication Release Date: March, 2006 Revision 1.6 ...
Page 94
... Bit 3: PBE means parity bit enable. When this bit is set, a parity bit is inserted between last data bit and stop bit for transmission integrity check. Bit Reserved Reserved Reserved Reserved PBE EPE Reserved Reserved BDLAB - 89 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 95
... In FIFO mode, this bit is set to "1" when the transmitter FIFO is empty cleared to "0" when host writes data bytes into TBR or FIFO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit RDR OER PBER NSER SBD TBRE TSRE RxFEI - 90 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 96
... This register specifies number of stop bits appended in the end of data byte Bit Guard time values. Default to be 01h. This bit is set to "1" to indicate previously received data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 97
... Bit 1: SDIODIR means SDIO direction SDIO is in output mode SDIO is in input mode Warm reset SCIODIR CLKSTP CLKSTPL SCKFS0 SCKFS1 Reserved Cold reset SCCLK frequency 00 1.5 MHz 01 3.0 MHz 10 6.0 MHz 11 12 MHz - 92 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 98
... This register combining with BLL and CBR determine internal sampling clock frequency. Refer to section 2.2.8 for example Bit Baud rate divisor latch higher byte values. Default to be 00h Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 99
... SCRST# keeps low initially to reset card but will output high after 512 clock cycles to meet requirement more than 400 clock cycles (specified in ISO/IEC 7816-3 × (f means SCCLK frequency 372 ( ) = = × = BLH , BLL CBR W83637HF/HG × Publication Release Date: March, 2006 Revision 1.6 ...
Page 100
... Writing a "1" to ECR bit 0 triggers a warm reset. This is a self-cleared reset operation unlike cold reset which needs explicit cancellation. Its effect is similar to cold reset except SCPWR# is kept activated and therefore power supply to card stays on. W83637HF/HG Publication Release Date: March, 2006 - 95 - Revision 1.6 ...
Page 101
... Power consumption in this state is similar to active state because one of the two sockets is selected and core circuit is still functioning. There is no idle state for W83637HF/HG because only one Smart Card socket is supported and it is always selected. ...
Page 102
... Users must make sure that all on-going transactions are concluded before putting Smart Card interface into power down state to prevent potential miss-operation of internal state machine. W83637HF/HG Publication Release Date: March, 2006 - 97 - Revision 1.6 ...
Page 103
... Plug and Play Configuration W83637HF/HG uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83637HF/HG, there are eleven Logical Devices (from Logical Device 0 to Logical Device B with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), ...
Page 104
... Extended Functions Enable Registers (EFERs) After a power-on reset, the W83637HF/HG enters the default operating mode. W83637HF/HG enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers PC/AT system, their port addresses are 2Eh or 4Eh (as described in previous section) ...
Page 105
... DX,AL ; select logical device 1 ; MOV DX,2EH MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,2FH MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;------------------------------------------ ; Exit extended function mode ;------------------------------------------ MOV DX,2EH MOV AL,AAH OUT DX, 100 - W83637HF/HG Publication Release Date: March, 2006 Revision 1.6 ...
Page 106
... The PNP ID of the W83637HF/HG Card Reader Device (For BIOS Programming use) SC (smart card reader) MS (memory stick reader) 8.3 Chip (Global) Control Register CR02 (Default 0x00) Bit Reserved. Bit 0 : SWRST --> Soft Reset. CR07 Bit LDNB7 - LDNB0 --> Logical Device Number Bit CR20 Bit DEVIDB7 - DEBIDB0 --> ...
Page 107
... PnP registers if the present value of PNPCVS is 1. The corresponding power-on setting pin is NDTRA (pin 52). CR25 (Default 0x00) Bit Reserved Bit 5 : URBTRI Bit 4 : URATRI Bit 3 : PRTTRI Bit Reserved Bit 0 : FDCTRI. W83637HF/HG When set will put the whole chip into power Publication Release Date: March, 2006 - 102 - Revision 1.6 ...
Page 108
... Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ Bit 0 : DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ W83637HF/HG Publication Release Date: March, 2006 - 103 - Revision 1.6 ...
Page 109
... SUSLED (SUSLED control bits are in CRF3 of Logical Device GP35 Bit 6 : PIN69S = 0 CIRRX GP34 Bit 5 : PIN70S = 0 RSMRST GP33 Bit 4 : PIN71S = 0 PWROK = 1 GP32 Bit 3 : PIN72S = 0 PWRCTL GP31 Bit 2 : PIN 73S = 0 SLP_SX GP30 Bit 1 : Reserved Bit 0 : Reserved W83637HF/HG Publication Release Date: March, 2006 - 104 - Revision 1.6 ...
Page 110
... Bit 7 : PIN92S = 0 Reserved = 1 GP21 Bit 6 : PIN91S = 0 Reserved = 1 GP22 Bit 5 : PIN90S = 0 PLED (PLED0 control bits are in CRF5 of Logical Device GP23 Bit 4 : PIN89S = 0 WDTO (Watch Dog Timer is controlled by CRF5, CRF6, CRF7 of Logical Device GP24 W83637HF/HG Publication Release Date: March, 2006 - 105 - Revision 1.6 ...
Page 111
... CR60 (Default 0x03, 0xf0 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select FDC I/O base address [0x100:0xFF8 byte boundary. CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit These bits select IRQ resource for FDC. W83637HF/HG Publication Release Date: March, 2006 - 106 - Revision 1.6 ...
Page 112
... Drive and Motor select 0 and 1 are swapped. Bit :Interface Mode = 11 AT Mode (Default (Reserved PS Model 30 Bit 1 : FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (Default) Bit 0 : Floppy Mode = 0 Normal Floppy Mode (Default Enhanced 3-mode FDD W83637HF/HG Publication Release Date: March, 2006 - 107 - Revision 1.6 ...
Page 113
... Bit DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A Select Regular drives and 2.88 format = 01 3-mode drive = 10 2 Meg Tape = 11 Reserved Bit 2 : Reserved. Bit 1:0 : DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B). W83637HF/HG Publication Release Date: March, 2006 - 108 - Revision 1.6 ...
Page 114
... DRVDEN1(pin 3) SELDEN DRATE0 DRATE1 DRATE0 DRATE0 SELDEN DRATE0 DRATE1 - 109 - W83637HF/HG SELDEN FM --- 1 250K 1 150K 0 125K 0 --- 1 250K 1 250K 0 125K 0 --- 1 250K 1 --- 0 125K 0 DRIVE TYPE 4/2/1 MB 3.5”“ 2/1 MB 5.25” ...
Page 115
... Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode. W83637HF/HG Publication Release Date: March, 2006 - 110 - Revision 1.6 ...
Page 116
... These two registers select Serial Port 2 I/O base address [0x100:0xFF8 byte boundary. CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit [3:0] : These bits select IRQ resource for Serial Port 2. W83637HF/HG Publication Release Date: March, 2006 - 111 - Revision 1.6 ...
Page 117
... Active pulse 1.6 µ S Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock - 112 - W83637HF/HG IRRX High Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into ...
Page 118
... Bit [3:0] : These bits select IRQ resource for KINT (keyboard). CR72 (Default 0x0C if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit [3:0] : These bits select IRQ resource for MINT (PS2 Mouse) W83637HF/HG Publication Release Date: March, 2006 - 113 - Revision 1.6 ...
Page 119
... CRF0 (Default 0x80) Bit KBC clock rate selection = 00 Select 6 MHz as KBC clock input Select 8 MHz as KBC clock input Select 12 MHz as KBC clock input Select 16 MHz as KBC clock input. (W83637HF-AW can support these 4 kinds of clock input) Bit Reserved. Bit Port 92 disable Port 92 enable. Bit Gate20 software control ...
Page 120
... If a port is programmed input port, then its respective bit can only be read. CRF2 (GP20-GP27 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. W83637HF/HG Publication Release Date: March, 2006 - 115 - Revision 1.6 ...
Page 121
... Counter instead of Watch Dog Timer Time-out value. Bit 0x00 Time-out Disable = 0x01 Time-out occurs after 1 second/minute = 0x02 Time-out occurs after 2 second/minutes = 0x03 Time-out occurs after 3 second/minutes ................................................ = 0xFF Time-out occurs after 255 second/minutes W83637HF/HG Publication Release Date: March, 2006 - 116 - Revision 1.6 ...
Page 122
... Suspend LED pin is a 1Hz toggle pulse with 50 duty cycle Suspend LED pin is a 1/4Hz toggle pulse with 50 duty cycle. This mode selection bit 7-6 keep its settings until battery power loss. Bit Reserved. W83637HF/HG Publication Release Date: March, 2006 - 117 - Revision 1.6 ...
Page 123
... Any button click or any movement x 0 one click of left/right button 0 1 one click of left button 1 1 one click of right button 0 0 two times click of left button 1 0 two times click of right button - 118 - W83637HF/HG Wake up event Publication Release Date: March, 2006 Revision 1.6 ...
Page 124
... Any button click or any movement x 0 One click of left/right button 0 1 One click of left button 1 1 One click of right button 0 0 Two times click of left button 1 0 Two times click of right button - 119 - W83637HF/HG Wake up event Publication Release Date: March, 2006 Revision 1.6 ...
Page 125
... Any button click or any movement x 0 One click of left/right button 0 1 One click of left button 1 1 One click of right button 0 0 Two times click of left button 1 0 Two times click of right button - 120 - W83637HF/HG Wake up event Publication Release Date: March, 2006 Revision 1.6 ...
Page 126
... Reset CIR Power-On function. After using CIR power-on, the software should write logical 1 to restart CIR power-on function. Bit 1 : Invert RX Data Inverting RX Data Not inverting RX Data. Bit 0 : Enable Demodulation Enable received signal to demodulate Disable received signal to demodulate. W83637HF/HG Publication Release Date: March, 2006 - 121 - Revision 1.6 ...
Page 127
... The chip is in the sleeping state The chip is in the working state. Bit Devices' trap status. Bit 4 : Reserved. Return zero when read. Bit Devices' trap status. W83637HF/HG Publication Release Date: March, 2006 - 122 - Revision 1.6 ...
Page 128
... Writing a 0 has no effect. Bit 6 : SCIRQSTS. SC IRQ status. Bit 5 : HMIRQSTS. Hardware monitor IRQ status. Bit 4 : WDTIRQSTS. Watch dog timer IRQ status. Bit 3 : CIRIRQSTS. Consumer IR IRQ status. Bit 1 : IRQIN1STS. IRQIN1 status. Bit 0 : IRQIN0STS. IRQIN0 status. W83637HF/HG Publication Release Date: March, 2006 - 123 - Revision 1.6 ...
Page 129
... SMI / PME interrupt due to UART A's IRQ. Bit 0 : URBIRQEN disable the generation of an SMI / PME interrupt due to UART B's IRQ enable the generation of an SMI / PME interrupt due to UART B's IRQ. W83637HF/HG Publication Release Date: March, 2006 - 124 - Revision 1.6 ...
Page 130
... Enable the generation of an SMI / PME interrupt due to IRQIN1's IRQ. Bit 0 : IRQIN0EN Disable the generation of an SMI / PME interrupt due to IRQIN0's IRQ Enable the generation of an SMI / PME interrupt due to IRQIN0's IRQ. W83637HF/HG Publication Release Date: March, 2006 - 125 - Revision 1.6 ...
Page 131
... CR30 (Default 0x00) Bit Reserved. Bit 0 : Logical device active bit Logical device is inactive Activates the logical device. CR60, CR61 (Default 0x00, 0x00) These two registers select Smart Card interface base address [0x100:0xFFF] on 8-byte boundary. W83637HF/HG Publication Release Date: March, 2006 - 126 - Revision 1.6 ...
Page 132
... Bit These bits select IRQ channel for MS/SD Card interface. CR74 (Default 0x04) Bit Reserved. Bit These Bits Select DMA Channel for MS/SD Card Port. 0x00 = DMA0 0x01 = DMA1 0x02 = DMA2 0x03 = DMA3 0x04 - 0x07 = No DMA active W83637HF/HG Publication Release Date: March, 2006 - 127 - Revision 1.6 ...
Page 133
... CRF0 (Default 0x01) Bit Reserved. Bit 2 : SDDET Polarity Select = 1 Active High = 0 Active Low Bit 1 : External SD Card Detect Pin(SDDET; Pin 69) Enable = 1 Enable = 0 Disable Bit 0 : Internal SD Card Detect Pin(DAT3; Pin 96) Enable = 1 Enable = 0 Disable W83637HF/HG Publication Release Date: March, 2006 - 128 - Revision 1.6 ...
Page 134
... SS SYM. MIN. TYP. MAX. I 2.4 BAT I 2.0 BAT +10 LIH I -10 LIL +10 LIH I -10 LIL - 129 - W83637HF/HG UNIT V +0 ° C ° C UNIT CONDITIONS 2.5 V BAT 5.0 V, All ACPI pins SB are not connected µ µ - µ ...
Page 135
... LIH I -10 LIL +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0 +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0 +10 LIH I -10 LIL - 130 - W83637HF/HG UNIT CONDITIONS - µ µ - µ 3.3V IN µ = - µ µ - µ A ...
Page 136
... V 0 +10 LIH I -10 LIL +10 LIH I -10 LIL +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0 +10 LIH I -10 LIL - 131 - W83637HF/HG UNIT CONDITIONS 3. - µ 3.3V IN µ µ µ µ µ µ µ Publication Release Date: March, 2006 ...
Page 137
... V 1.6 2.0 2 0 +10 LIH I -10 LIL V 1.3 1.5 1 3.2 3 +10 LIH I -10 LIL V 1.3 1.5 1 3.2 3 +10 LIH I -10 LIL - 132 - W83637HF/HG UNIT CONDITIONS µ µ µ µ µ µ Publication Release Date: March, 2006 ...
Page 138
... Output pin with 16mA source-sink capability 16 Output Low Voltage Output High Voltage SYM. MIN. TYP. MAX. V 1.3 1.5 1 3.2 3 +10 LIH I -10 LIL V 1.3 1.5 1 3.2 3 +10 LIH I -10 LIL 133 - W83637HF/HG UNIT CONDITIONS µ µ µ µ - ...
Page 139
... Input Low Leakage SYM. MIN. TYP. MAX +10 LIH I -10 LIL +10 LIH I -10 LIL +10 LIH I -10 LIL - 134 - W83637HF/HG UNIT CONDITIONS - µ µ 3.3V µ µ µ µ Publication Release Date: March, 2006 Revision 1.6 ...
Page 140
... V 1.6 2.0 2 0.5 1 +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0.5 1 +10 LIH I -10 LIL +10 LIH I -10 LIL +10 LIH I -10 LIL - 135 - W83637HF/HG UNIT CONDITIONS V V µ µ µ µ µ 3 µ µ µ A ...
Page 141
... Voltage Hystersis Input High Leakage Input Low Leakage SYM. MIN. TYP. MAX. V 1.3 1 +10 LIH I -10 LIL V 1.3 1.5 1 3.2 3 +10 LIH I -10 LIL - 136 - W83637HF/HG UNIT CONDITIONS µ µ µ µ Publication Release Date: March, 2006 Revision 1.6 ...
Page 142
... ORDERING INSTRUCTION PART NO. W83637HF-AW W83637HG-AW KBC FIRMWARE TM AMIKEY-2 TM AMIKEY-2 - 137 - W83637HF/HG REMARKS Publication Release Date: March, 2006 Revision 1.6 ...
Page 143
... HOW TO READ THE TOP MARKING Example: The top marking of W83637HF-AW S MART @ W83637HF-AW AM. MEGA. 87-96 109G5BASC 1st line: Winbond logo and S 2nd line: part number: W83637HF-AW 3rd line: the source of KBC F/W -- American Megatrends Incorporated 4th line: the tracking code 109 : packages made in '2001, week assembly house ID ...
Page 144
... G : assembly house ID; A means ASE, S means SPIL, G means GR, etc Winbond internal use revision; A means version A, B means version Winbond internal use. W83637HF/HG Publication Release Date: March, 2006 - 139 - Revision 1.6 ...
Page 145
... North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 - 140 - W83637HF/HG Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom A 0.25 0.35 ...
Page 146
... PD4 PD5 PD6 PD7 ACK# BUSY PE SLCT |LINK |637HFD2.SCH |637HFD3.SCH |637HFD4.SCH |637HFD5.SCH |637HFD6.SCH Winbond Electronic Corp. Title W83637HF CIRCUIT (LPC I/O) Size Document Number WINBOND ELECTRONICS CORP. B 637HFD1.SCH Date: , 13, 2002 Sheet Publication Release Date: March, 2006 Revision 1.6 COMA Rev 0.3 1 ...
Page 147
... IO5V L7 R16 R17 R18 R19 R20 FB 100K 2.2K 2.2K 2.2K 2. PRT C14 C19 C20 C21 C22 0.01U 0.01U 0.01U 0.01U 0.01U - 142 - W83637HF/HG F1 VWAKE FUSE R11 R12 4.7K 4. MDAT MCLK HEADER 6 47P 47P PS2 MOUSE VWAKE R13 R14 4.7K 4. KDAT KCLK ...
Page 148
... GND NDSRB 5 6 NRTSB NCTSB 7 8 NRIB 9 10 HEADER 5X2 COMB (UARTB) JP6 1 IO_5V SCPWCTL SCIO 7 SCCLK MEM STICK Publication Release Date: March, 2006 - 143 - W83637HF/ CIRRX VWAKE CN2X5 R31 4. VCC GND 2 7 PWR RST SCRST# R32 3 8 SCRWLED C4 RWLED 4 ...
Page 149
... RP2 RP3 RP4 2.7K 2.7K 2.7K R35 2.7K C31 C32 C33 C34 C35 180P 180P 180P 180P 180P C39 C40 C41 C42 C43 180P 180P 180P 180P 180P - 144 - W83637HF/ NDP2 2 NDP15 15 NDP3 3 16 NDP4 4 17 NDP5 5 18 NDP6 NDP10 10 23 ...
Page 150
... PNP 3906 C44 Q3 JP7 + R42 100 MOSFET N FANPWM2 10u 3 2N7002 FANIN1 2 1 R47 HEADER 3 10K FROM CPU'S THERM DIODE - 145 - W83637HF/HG +12V D5 R40 4.7K R43 FANIN2 27K R46 10K IO5V R50 100 LS1 R51 10K SPEAKER Q5 BEEP NPN R53 IOBAT CASEOPEN# ...
Page 151
... RSMRST IOVSB PWRCTL# 4.7K IO3V RP11 1 8 LDRQ LFRAME SERIRQ 4.7K IO3V RP12 LAD[0.. 4.7K W83637HF/HG POWER ON SETTING PIN S2 R59 4.7K STREN 1 10 R?(8P4RA1 GP42 HEFRAS RTSA# PNPCSV DTRA PENKBC SOUTA PEN48 SOUTB SW DIP-5 4.7K POWER ON SETTING PIN HEFRAS RTSA# ...