PDI1394L40BE Philips Semiconductors, PDI1394L40BE Datasheet
PDI1394L40BE
Available stocks
Related parts for PDI1394L40BE
PDI1394L40BE Summary of contents
Page 1
SEE THE LAST 2 PAGES OF THIS DATASHEET FOR A LIST OF ERRATA RELATED TO THIS PART. PDI1394L40 1394 enhanced AV link layer controller Preliminary specification Supersedes data of 2000 May 15 hilips Semiconductors INTEGRATED CIRCUITS 2000 Dec 15 ...
Page 2
... Philips Semiconductors 1394 enhanced AV link layer controller 1.0 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
... Philips Semiconductors 1394 enhanced AV link layer controller 13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C 13.2.5 Isochronous Transmitter Interrupt Enable (ITXINTE) – Base Address: 0x030 13.2.6 Isochronous Transmitter Control Register (ITXCTL) – Base Address: 0x34 13.2.7 Isochronous Transmitter Memory Status (ITXMEM) – Base Address: 0x038 13.2.8 Isochronous Receiver Unpacking Control (IRXPKCTL) – ...
Page 4
... V tolerant available in the LQFP144 package. CONDITIONS MIN 3.0 Operating 49.147 OUTSIDE NORTH AMERICA PDI1394L40BE NOTE: This datasheet is subject to change. 1 Preliminary specification PDI1394L40 TYP MAX UNIT 3.3 3.6 V 110 200 mA 49.152 49.157 MHz NORTH AMERICA PKG. DWG. # PDI1394L40BE SOT486–1 ...
Page 5
... Philips Semiconductors 1394 enhanced AV link layer controller 5.0 PIN CONFIGURATION Pin Function 1 HIF D15 2 HIF D14 3 HIF D13 4 HIF D12 5 GND HIF D11 8 HIF D10 9 HIF D9 10 HIF D8 11 GND HIF AD7 14 HIF AD6 15 HIF AD5 16 HIF AD4 17 GND HIF AD3 ...
Page 6
... Philips Semiconductors 1394 enhanced AV link layer controller 6.0 FUNCTIONAL DIAGRAM HIF A[7:0] HIF D[15:8] HIF AD[7:0] HIF A8 HIF WRN HIF RDN HIF CSN HIF 16BIT HIF MUX RESETN HIF ALE HIF WAIT HIF INTN PD CYCLEIN CYCLEOUT CLK50 AV1 D[7:0] AV1CLK AV1VALID ...
Page 7
... Philips Semiconductors 1394 enhanced AV link layer controller 8.0 APPLICATION DIAGRAM MPEG OR DVC INTERFACE DECODER MPEG OR DVC INTERFACE DECODER DATA 16/ ADDRESS 9/ INTERRUPT & CONTROL HOST CONTROLLER 9.0 PIN DESCRIPTION 9.1 Host Interface PIN No. PIN SYMBOL I/O 13, 14, 15, 16, 19, HIF AD[7:0] I/O 20, 21, 22 ...
Page 8
... Philips Semiconductors 1394 enhanced AV link layer controller 9.2 AV Interface 1 NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register (0x018)—default is transmit. PIN No. PIN SYMBOL I/O 96 AV1ERR0 O 97 AV1ERR1 O 98 AV1ENDPCK I 99 AV1CLK I/O 100 AV1FSYNC ...
Page 9
... Philips Semiconductors 1394 enhanced AV link layer controller 9.3 AV Interface 2 NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register—default is receive. PIN No. PIN SYMBOL I/O AV2ERR0/ 121 I/O LTLEND AV2ERR1/ 122 I/O DATINV 123 AV2ENDPCK I 124 ...
Page 10
... Philips Semiconductors 1394 enhanced AV link layer controller 9.4 Phy Interface PIN No. PIN SYMBOL I/O Data 0 (MSB) through 7 (NOTE: To preserve compatibility to the specified Link-Phy interface of 82, 81, 80, 79, the IEEE 1394–1995 standard, Annex J, bit 0 is the most significant bit). Data is expected on PHY D[0:7] I/O AV D[0:1] for 100Mb/s, AV D[0:3] for 200Mb/s, and AV D[0:7] for 400Mb/s. See IEEE 1394– ...
Page 11
... Philips Semiconductors 1394 enhanced AV link layer controller 10.0 RECOMMENDED OPERATING CONDITIONS SYMBOL SYMBOL PARAMETER PARAMETER V DC supply voltage CC V Input voltage I V High-level input voltage IH V Low-level input voltage IL I High-level output current OH I Low-level output current OL dT/dV Input transition rise or fall time ...
Page 12
... Philips Semiconductors 1394 enhanced AV link layer controller 12.0 FUNCTIONAL DESCRIPTION 12.1 Overview The PDI1394L40 is an IEEE1394–1995 and IEEE1394.a compliant link layer controller. It provides a direct interface between a 1394 bus and various MPEG–2 and DVC codecs. The AV Link maps and unmaps AV data streams and similar data onto 1394 isochronous packets. Data can be ciphered or deciphered according to the ‘ ...
Page 13
... Philips Semiconductors 1394 enhanced AV link layer controller Port Dir AVxREADY Transmit Out The L40 is prepared to receive a byte. The attached device will not assert AVVALID for any cycle in which AVxRDY is false. Receive In The attached device is prepared to receive a byte. The L40 will not assert AVxVALID for any cycle in which AVxREADY is false ...
Page 14
... Philips Semiconductors 1394 enhanced AV link layer controller DEFAULT BUFFER SIZE Asynchronous Receive Response FIFO Asynchronous Receive Request FIFO Asynchronous Transmit Response FIFO Asynchronous Transmit Request FIFO Isochronous (AV) Transmit Buffer Isochronous (AV) Receive Buffer 12.3 Bushold and Link/PHY single capacitor galvanic isolation 12.3.1 Bushold The PDI1394L40 uses an internal bushold circuit on each of the indicated pins to keep these CMOS inputs from “ ...
Page 15
... Philips Semiconductors 1394 enhanced AV link layer controller 12.3.2 Single capacitor isolation The circuit example (Figure 3) shows the connections required to implement basic single capacitor Link/PHY isolation. NOTE: The isolation enablement pins on both devices are in their “1” states, activating the bushold circuits on each part. The bushold circuits provide local dc ground references to each side of the isolating/coupling capacitors ...
Page 16
... Philips Semiconductors 1394 enhanced AV link layer controller 12.5 The host interface The host interface allows an 8 bit or 16 bit CPU to access all registers and the asynchronous packet queues designed to be easy to use with a wide range of processors, including 8051, MIPS1900, ST20, PowerPC etc. The host interface can work with 8 bit or 16 bit wide data paths, and offers multiplexed or non-multiplexed access ...
Page 17
... Philips Semiconductors 1394 enhanced AV link layer controller 12.5.2 Write accesses To write to an internal register the host interface must collect the 4 byte values (8 bit mode word values (16 bit mode) into a 32 bit value and then write the result to the target register in a single clock tick. This requires a register to hold the 32 bit value being compiled until it is ready to be written to the actual target register ...
Page 18
... Philips Semiconductors 1394 enhanced AV link layer controller are continuous recommend that before the interrupt is acknowledged, the corresponding enable bit should be set to “0”, else the interrupt will immediately happen again.] SWPD is a control bit. There are two ways to affect a power–down of the link chip. Setting SWPD will stop the link chip from transmitting the LPS signal to the phy chip and thus cause the phy to withhold the SCLK, thus powering– ...
Page 19
... Philips Semiconductors 1394 enhanced AV link layer controller In Little Endian mode and DATAINV = 0, the bytes in each quadlet are numbered 3. .0 from the left (most significant) to right (least significant) as shown in Figure 5. To access a register in 8 bit HIF mode, at address N the CPU should use addresses ...
Page 20
... Philips Semiconductors 1394 enhanced AV link layer controller 12.5.6 The CPU bus interface signals The CPU interface is directly compatible with a wide range of microcontrollers, and supports both multiplexed and non-multiplex access. It uses separate HIF RDN, HIF WRN, HIF ALE, and HIF CSN chip select lines. There are 9 address inputs (HIF A0..HIF A8) and data in/out lines HIF D[7:0] or HIF D [15:0] ...
Page 21
... Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N HIF RD_N HIF WR_N HIFA7–A0 HIFD15–D8 HIFAD7–AD0 A8 HIF_WAIT HIF_MUX HIF16BIT NOTE: 1. ALE line is held LOW. 2000 Dec 15 Figure 7. 16 Bit Write Cycle Non-multiplexed 18 Preliminary specification PDI1394L40 SV01089 ...
Page 22
... Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N t ALES HIF ALE AD7–AD0 A7–A0 HIFD15–D8 A8 HIF RD_N HIF WR_N HIF_WAIT HIF_MUX HIF16BIT NOTE: 1. Second write cycle elongated by WAIT signal. 2000 Dec 15 t ALEH t PWALE ADDR DATA ADDR LATCHED DATA Figure 8 ...
Page 23
... Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N t ALES HIF ALE HIF AD7–AD0 HIF A7–A0 HIFD15–D8 A8 HIF RD_N HIF WR_N HIF_WAIT HIF_MUX HIF16BIT 2000 Dec 15 t ALEH t PWALE ADDR DA TA ADDR LATCHED DATA Figure 9. 16 Bit Read Cycle Multiplexed ...
Page 24
... Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N t ALES HIF ALE AD7–AD0 A7–A0 A8 HIF RD_N HIF WR_N HIF_WAIT HIF_MUX HIF16BIT 2000 Dec 15 t ALEH t PWALE ADDR DATA ADDR LATCHED Figure 10. 8 Bit Write Cycle Multiplexed 21 Preliminary specification PDI1394L40 DATA ...
Page 25
... Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N t ALES HIF ALE HIF AD7–AD0 HIF A7–A0 A8 HIF RD_N HIF WR_N HIF_WAIT HIF_MUX HIF16BIT 2000 Dec 15 t ALEH t PWALE ADDR DA TA ADDR LATCHED Figure 11. 8 Bit Read Cycle Multiplexed 22 Preliminary specification ...
Page 26
... Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N HIF RD_N HIF WR_N HIFA7–A0 HIFAD7–AD0 A8 HIF_WAIT HIF_MUX HIF16BIT NOTE: 1. ALE line is held LOW. 2000 Dec 15 Figure 12. 8 Bit Write Cycle Non-multiplexed 23 Preliminary specification PDI1394L40 SV01774 ...
Page 27
... Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N HIF RD_N HIF WR_N HIF A8 HIFA7–A0 HIFAD7–AD0 HIF_WAIT HIF_MUX HIF16BIT NOTE: 1. ALE line is held LOW. 2000 Dec 15 Figure 13. 8 Bit Read Cycle Non-multiplexed 24 Preliminary specification PDI1394L40 SV01775 ...
Page 28
... Philips Semiconductors 1394 enhanced AV link layer controller 12.6 The Asynchronous Packet Interface The PDI1394L40 provides an interface to asynchronous data packets through the registers in the host interface. The format of the asynchronous packets is specified in the following sections. 12.6.1 Reading an Asynchronous Packet Upon reception of a packet, the packet data is stored in the appropriate receive FIFO, either the Request or Response FIFO. The location of the packet is indicated by either the RREQQQAV or RRSPQAV status bit being set in the Asynchronous Interrupt Acknowledge (ASYINTACK) register ...
Page 29
... Philips Semiconductors 1394 enhanced AV link layer controller Table 1. Asynchronous Transmit Fields Field Name spd This field indicates the speed at which this packet sent. 00=100 Mbs, 01=200 Mbs, and 10=400 Mbs undefined tLabel This field is the transaction label, which is used to pair up a response packet with its corresponding request packet. ...
Page 30
... Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.2 No-data Transmit The no-data transmit formats are shown in Figures 14 and 15. The first quadlet contains packet control information. The second and third quadlets contain 16-bit destination ID and either the 48-bit, quadlet aligned destination offset (for requests) or the response code (for responses) ...
Page 31
... Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.3 Quadlet Transmit Three quadlet transmit formats are shown below. In these figures: The first quadlet contains packet control information. The second and third quadlets contain 16-bit destination ID and either the 48-bit quadlet-aligned destination offset (for requests) or the response code (for responses). ...
Page 32
... Philips Semiconductors 1394 enhanced AV link layer controller Figure 18. Block Read Request Transmit Format 2000 Dec 15 0 spd tLabel rt tCode destinationID destinationOffsetHigh destinationOffsetLow data length 29 Preliminary specification PDI1394L40 priority SV01084 ...
Page 33
... Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.4 Block Transmit The block transmit format is shown below, this is the generic format for reads and writes. The first quadlet contains packet control information. The second and third quadlets contain the 16-bit destination node ID and either the 48-bit destination offset (for requests) or the response code and reserved data (for responses) ...
Page 34
... Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.5 Unformatted Transmit The unformatted transmit format is shown in Figure 21. The first quadlet contains packet control information. The remaining quadlets contain data that is transmitted without any formatting on the bus. No CRC is appended on the packet, nor is any data in the first quadlet sent. This is used to send PHY configuration and Link-on packets ...
Page 35
... Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.7 Asynchronous Receive Packet Formats This section describes the asynchronous receive packet formats. Four basic asynchronous data packet formats and one confirmation format exist: Table 2. Asynchronous Data Packet Formats ITEM FORMAT packet data No-packet data ...
Page 36
... Philips Semiconductors 1394 enhanced AV link layer controller Table 4. Acknowledge codes Code Name 0001 ack_complete The node has successfully accepted the packet. If the packet was a request subaction, the destination node has successfully completed the transaction and no response subaction shall follow. 0010 ack_pending The node has successfully accepted the packet ...
Page 37
... Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.8 No-data Receive The no-data receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlet contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for responses) ...
Page 38
... Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.9 Quadlet Receive The quadlet receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlets contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for responses) ...
Page 39
... Philips Semiconductors 1394 enhanced AV link layer controller 2000 Dec 15 destinationID tLabel rt tCode sourceID destinationOffsetHigh destinationOffsetLow data length spd Figure 27. Block Read Request Receive Format 36 Preliminary specification PDI1394L40 priority ackSent SV00261 ...
Page 40
... Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.10 Block receive The block receive format is shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlets contain 16-bit sourceID and either the 48-bit destination offset (for requests) or the response code and reserved data (for responses) ...
Page 41
... Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.11 Asynchronous Stream Receive The Asynchronous streaming receive packet format is shown below. The first quadlet contains dataLength, tag, and Channel number for source identification, and synchronization information. The following quadlets contain (possibly zero) quadlets of block information. The last quadlet contains transmission speed and status information ...
Page 42
... Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.13 Link data confirmation formats After a request, response, or asynchronous stream packet is transmitted, the asynchronous transmitter assembles a Link data confirmation (see Figure 32) which is used to confirm the transmission to the higher layers. Packets transmitted from the Transmit Request FIFO are confirmed by a confirmation written into the Receive Request FIFO and packets transmitted from the Transmit Response FIFO are confirmed by a confirmation written into the Receive Response FIFO ...
Page 43
... Philips Semiconductors 1394 enhanced AV link layer controller 12.7.1.1 Interrupt Hierarchy HIF INT_N GLOBCSR (0x018) NOTE read of the RDI register (0xB0) should be done before looking for an interrupt in the GLOBCSR register. 13.0 REGISTER MAP Registers are 32 bits (quadlet) wide and all accesses are always done on a quadlet basis. This means that it is not possible to write just the lower 8 bits, and leave the other bits unaffected (see Section 12.5.2 for more information). The values written to undefined fields/bits are ignored and thus DON’ ...
Page 44
... Philips Semiconductors 1394 enhanced AV link layer controller REGISTER 31 ADDRESS IDREG BUS ID 0x000 LNKCTL BSYCTRL 0x004 LNKPHYINTACK 0x008 LNKPHYINTE 0x00C CYCTM CYCLE_SECONDS 0x010 PHYACS PHYRGAD 0x014 GLOBCSR 0x018 TIMER 0x01C ITXPKCTL 0x020 ITXHQ1 0x024 ITXHQ2 FMT 0x028 ITXINTACK 0x02C ITXINTE 0x030 2000 Dec 15 ...
Page 45
... Philips Semiconductors 1394 enhanced AV link layer controller 31 REGISTER ADDRESS ITXCTL 0x034 ITXMEM 0x038 <RESERVED> 0x03C IRXPKCTL 0x040 0 0 IRXHQ1 SID 0x044 IRXHQ2 FMT 0x048 IRXINTACK 0x04C IRXINTE 0x050 IRXCTL 0x054 IRXMEM 0x058 <RESERVED> 0x05C . . . <RESERVED> 0x07C 2000 Dec TAG CHANNEL DBS ...
Page 46
... Philips Semiconductors 1394 enhanced AV link layer controller 31 REGISTER ADDRESS ASYCTL 0x080 ASYMEM 0x084 TX_RQ_NEXT 0x088 TX_RQ_LAST 0x08C TX_RP_NEXT 0x090 TX_RP_LAST 0x094 RREQ 0x098 RRSP 0x09C ASYINTACK 0x0A0 ASYINTE 0x0A4 <RESERVED> 0x0A8 0x0AC RDI 0x0B0 0 0 2000 Dec MAXRC TOS FIRST/MIDDLE QUADLET OF PACKET FOR TRANSMITTER REQUEST QUEUE ...
Page 47
... Philips Semiconductors 1394 enhanced AV link layer controller REGISTER 31 ADDRESS <RESERVED> 0x0B4 . . . . 0x0F0 SHADOW_REG byte 0 0x0F4 INDADDR 0x0F8 INDDATA 0x0FC 2000 Dec byte 1 byte RESERVED WINDOW TO THE INDIRECT QUADLET POINTED TO BY INDADDR 44 Preliminary specification PDI1394L40 byte INDADDR SV01033 ...
Page 48
... Philips Semiconductors 1394 enhanced AV link layer controller 13.1 Link Control Registers ID Register (IDREG) – Base Address: 0x000 13.1.1 The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset. 3130 BUS ID Reset Value 0xFFFF0301 Bit 31..22: ...
Page 49
... Philips Semiconductors 1394 enhanced AV link layer controller Bit 22: R Little Endian (LTLEND): Refers to the state of the endianess of the data and address lines connected to the ’L40. This bit reflects the state of the AV2ERR0/LTLEND pin during power reset. The state of this pin is read during reset and that state is latched into this bit position ...
Page 50
... Philips Semiconductors 1394 enhanced AV link layer controller 13.1.3 Link /Phy Interrupt Acknowledge (LNKPHYINTACK) – Base Address: 0x008 The Link/Phy Interrupt Acknowledge register indicates various status and error conditions in the Link and Phy which can be programmed to generate an interrupt. The interrupt enable register (LNKPHYINTE mirror of this register. Acknowledgment of an interrupt is accomplished by writing a ‘ ...
Page 51
... Philips Semiconductors 1394 enhanced AV link layer controller 13.1.4 Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C This register is a mirror of the Link/Phy Interrupt Acknowledge (LNKPHYINTACK) register. Enabling an interrupt is accomplished by writing a ‘1’ to the bit corresponding to the interrupt desired. This register enables the interrupts described in the Link /Phy Interrupt Acknowledge register (LNKPHYINTACK) description. A one in any of the bits enables that function to create an interrupt ...
Page 52
... Philips Semiconductors 1394 enhanced AV link layer controller 13.1.6 Phy Register Access (PHYACS) – Base Address: 0x014 This register provides access to the internal registers on the Phy. There are special considerations when reading or writing to this register. When reading a PHY register, the address of the register is written to the PHYRGAD field with the RDPHY bit set. The PHY data will be valid when the PHYRRX bit (LNKPHYINTACK register bit 14) is set ...
Page 53
... Philips Semiconductors 1394 enhanced AV link layer controller Bit 16: R/W Direction of AVPORT1 (DIRAV1): A ‘1’ enables AVPORT1 as a transmitter, thus AVPORT1 pins are inputs. A ‘0’ configures AVPORT1 as a receiver, AVPORT1 pins are outputs in this configuration. The configuration of AVPORT2 pins is opposite of AVPORT1 pins. When AVPORT1 is set to transmit, AVPORT2 receives and vice versa. ...
Page 54
... Philips Semiconductors 1394 enhanced AV link layer controller 13.2 AV (Isochronous) Transmitter and Receiver Registers 13.2.1 Isochronous Transmit Packing Control and Status (ITXPKCTL) – Base Address: 0x020 This register allows the user to set up the appropriate AV packets from data entered into the AV interface. The packing and control parameters (TRDEL, MAXBL, DBS, FN, QPC, and SPH) should never be changed while the transmitter is operating ...
Page 55
... Philips Semiconductors 1394 enhanced AV link layer controller 13.2.2 Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024 The AV Transmit Packing Control register holds the specification for the packing scheme used on the AV data stream. This information is included in Common Isochronous Packet (CIP) header quadlet 1. ...
Page 56
... Philips Semiconductors 1394 enhanced AV link layer controller 13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C The AV Transmitter Interrupt Control and Status register is the interrupt register for the AV transmitter. Bits 2, 3, and 4 “auto repair” themselves, i.e. AVLINK will detect the situation and attempt to recover on its own. The host controller still needs to clear these interrupts to be alerted the next time ...
Page 57
... Philips Semiconductors 1394 enhanced AV link layer controller 13.2.6 Isochronous Transmitter Control Register (ITXCTL) – Base Address: 0x34 Reset Value 0x00000000 Bit 15..14: R/W Tag: Tag code to insert in isochronous bus packet header. Should be ‘01’ for IEC 61883 International Standard data. Bit 13..8: R/W Channel: Isochronous channel number ...
Page 58
... Philips Semiconductors 1394 enhanced AV link layer controller 13.2.8 Isochronous Receiver Unpacking Control (IRXPKCTL) – Base Address: 0x040 NOTE: When receiver reset is required, first disable receiver (EN_IRX = 0), then wait until Rx FIFO is emptied, then perform the reset. This will allow previously received packets the application instead of being lost. ...
Page 59
... Philips Semiconductors 1394 enhanced AV link layer controller 13.2.9 Common Isochronous Receiver Packet Header Quadlet 1 (IRXHQ1) – Base Address: 0x044 This quadlet represents the last received header value when AV receiver is operating SID Reset Value 0x00000000 Bit 31..30: R E0: End of Header, F0: Format: Always set to 00 for first AV header quadlet. ...
Page 60
... Philips Semiconductors 1394 enhanced AV link layer controller 13.2.11 Isochronous Receiver Interrupt Acknowledge (IRXINTACK) – Base Address: 0x04C Reset Value 0x00000000 Bit 14: R/W SYTOVF: SYT FIFO overflow. The isochronous receiver’s SYT field FIFO has overflowed and has been automatically reset and cleared. This interrupt alerts the host controller that AVFSYNC pulses may be missing due to an SYT field reception error ...
Page 61
... Philips Semiconductors 1394 enhanced AV link layer controller 13.2.13 Isochronous Receiver Control Register (IRXCTL) – Base Address: 0x054 Reset Value 0x00000000 Bit 17..16: R SPD: Speed of last received isochronous packet (S100 .. S400 100 Mbps 01 = 200 Mbps 10 = 400 Mbps 11 = Reserved Bit 15..14: R/W TAG: Isochronous tag value (must match) for AV format, ‘01’ for IEC 61883 International Standard data. ...
Page 62
... Philips Semiconductors 1394 enhanced AV link layer controller 13.3 Asynchronous Control and Status Interface 13.3.1 Asynchronous RX/TX Control (ASYCTL) – Base Address: 0x080 Reset Value 0x00300320 Bit 23: R/W DIS_BCAST: Disable the reception of broadcast packets (async packets address to 0x3F). Bit 22: R/W ARXRST: Asynchronous receiver reset. This bit will auto clear when the link layer state machine is idle. ...
Page 63
... Philips Semiconductors 1394 enhanced AV link layer controller 13.3.3 Asynchronous Transmit Request Next (TX_RQ_NEXT) – Base Address: 0x088 Bit 31..0: W TX_RQ_NEXT: First/middle quadlet of packet for transmitter request queue (write only). Writing this register will clear the TREQQWR flag until the quadlet has been written to its queue. ...
Page 64
... Philips Semiconductors 1394 enhanced AV link layer controller 13.3.7 Asynchronous Receive Request (RREQ) – Base Address: 0x098 3130 Reset Value 0x00000000 Bit 31..0: R RREQ:Quadlet of packet from receiver request queue (transfer register). Reading this register will clear the RREQQQAV flag until the next received quadlet is available for reading. ...
Page 65
... Philips Semiconductors 1394 enhanced AV link layer controller 13.3.10 Asynchronous RX/TX Interrupt Enable (ASYINTE) – Base Address: 0x0A4 Reset Value 0x00000000 Bits16..0 are interrupt enable bits for the Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK). 13.3.11 RDI Register – Base Address: 0x0B0 NOTE: 1. Also refer to Section 12.5.3 for functional descriptions. ...
Page 66
... Philips Semiconductors 1394 enhanced AV link layer controller Bit 3: R/W PLI: PHY – link interface initialized interrupt. This interrupt indicates when the PHY – link initialization routine has been accomplished. This bit will be set upon completion of the initialization; if enabled, it will cause a host interface interrupt in order to inform the host controller of the completed action. Reset of this interrupt requires the writing of a (1) to this bit position. When used as a status bit, it will be necessary to first write a “ ...
Page 67
... Philips Semiconductors 1394 enhanced AV link layer controller 13.4 Indirect Address Registers 13.4.1 The host interface register set has been extended to provide additional control and data registers for FIFO size control and copy protection control registers. These extensions have been implemented via an indirect addressing mechanism. This mechanism allows software written for previous versions of the AV Link (PDI1394L21 and PDI1394L11) to operate on the PDI1394L40 with minimal changes ...
Page 68
... Philips Semiconductors 1394 enhanced AV link layer controller 13.5 Indirect Address Registers The following registers are defined in the indirect address space. Access to these registers must be made through the Indirect Address (INDADDR) and Indirect Data (INDDATA) registers. 13.5.1 Registers for FIFO Size Programming Each FIFO can be programmed to a certain size with a granularity of 64 quadlets ...
Page 69
... Philips Semiconductors 1394 enhanced AV link layer controller 13.5.1.2 Asynchronous Receive Request FIFO Size (RREQSIZE) – Indirect Address: 0x104 Reset Value 0x00000407 Bit 31..14 R/W Unused bits read ‘0’ Bit 13..8 R/W base_fifo: Base address of the FIFO Bit 7, 6 R/W Unused bits read ‘0’ ...
Page 70
... Philips Semiconductors 1394 enhanced AV link layer controller 13.5.1.5 Isochronous Receiver FIFO Size (IRXSIZE) – Indirect Address: 0x120 Reset Value 0x0000101F Bit 31..14 R/W Unused bits read ‘0’ Bit 13..8 R/W base_fifo: Base address of the FIFO Bit 7, 6 R/W Unused bits read ‘0’ ...
Page 71
... Philips Semiconductors 1394 enhanced AV link layer controller 14.0 DC ELECTRICAL CHARACTERISTICS Table 9. DC Electrical Characteristics SYMBOL PARAMETER V LOW input voltage IL V HIGH input voltage Input threshold, rising edge IT1 V – Input threshold, falling edge IT1 V + Input threshold, rising edge IT2 V – Input threshold, falling edge ...
Page 72
... Philips Semiconductors 1394 enhanced AV link layer controller 15.0 AC CHARACTERISTICS GND = SYMBOL PARAMETER t PERIOD (parallel AV clock period mode clock setup time clock input hold time clock output delay time clock pulse width HIGH WHIGH t AV clock pulse width LOW WLOW t AVxFSYNC pulse width HIGH ...
Page 73
... Philips Semiconductors 1394 enhanced AV link layer controller 16.0 TIMING DIAGRAMS 16.1 AV Interface Operation AVCLK MESSAGE AV D[7:0] AVSYNC AVVALID AVERR[0] ASSERTED IN THE EVENT OF A DATA BLOCK SEQUENCE ERROR AVERR[1] Figure 35. AV Parallel Interface Operation Diagram 16.2 AV Interface Critical Timings AVCLK É É É ...
Page 74
... Philips Semiconductors 1394 enhanced AV link layer controller 16.3 PHY-Link Interface Critical Timings SCLK PHY D[0:7], PHY CTL[0:1] Figure 38. PHY D[0:7], PHY CTL[0:1] Input Setup and Hold Timing Waveforms PHY D[0:7], PHY CTL[0:1], LREQ Figure 39. PHY D[0:7], PHY CTL[0:1], and LREQ Output-Delay Timing Waveforms ...
Page 75
... Philips Semiconductors 1394 enhanced AV link layer controller 16.4 Host Interface Critical Timings READ HIF A[7:0] HIF CS_N HIF RD_N HIF D[7: WAIT WAIT WRITE HIF WR_N HIF D[7: WAIT t WAIT NOTE: 1. Wait line asserts only during Read and Write cycles in which A8 is asserted. ...
Page 76
... Philips Semiconductors 1394 enhanced AV link layer controller SCLK CYCLEIN CYCLEOUT 16.6 RESET Timings RESET_N 2000 Dec 15 50 50% Figure 42. CYCLEOUT Waveforms 50% 50% t RESET SV00698 Figure 43. RESET_N Waveform 73 Preliminary specification PDI1394L40 50 50% SV00697 ...
Page 77
... Philips Semiconductors 1394 enhanced AV link layer controller LQFP144: plastic low profile quad flat package; 144 leads; body 1.4 mm 2000 Dec 15 74 Preliminary specification PDI1394L40 SOT486-1 ...
Page 78
... Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no ...
Page 79
... SCLK input of the L40 make the pin go to the LOW state when the clock is not present. The value of the resistor is R= 3.3 KOhms; a 1/10th watt type is sufficient. Errata To the PDI1394L40 1394 AV Link Layer Controller (Data Sheet dated: 2000 December 15). ERRATA FOR THE PHILIPS Philips Semiconductors 15 December 2000 – Page 76 ...
Page 80
... The PLI bit should be ignored by the node operating software when the L40 is operated with a NON–1394A PHY with the L40 1394 MODE pin at 3.3v (high). Errata To the PDI1394L40 1394 AV Link Layer Controller (Data Sheet dated: 2000 December 15). Philips Semiconductors 15 December 2000 – Page 77 ...