CXD3008Q Sony, CXD3008Q Datasheet
CXD3008Q
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CXD3008Q Summary of contents
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... CD Digital Signal Processor with Built-in Digital Servo For the availability of this product, please contact the sales office. Description The CXD3008Q is a digital signal processor LSI for CD players. This LSI incorporates a digital servo. Features • All digital signal processings during playback are performed with a single chip • ...
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... EFM demodurator 32K RAM Sub Code Processor Servo Auto Sequencer SERVO Interface MIRR DFCT FOK SERVO DSP A/D FOCUS SERVO TRACKING SERVO SLED SERVO – 2 – CXD3008Q TES1 37 TEST 36 XRST 2 D/A Interface 63 MD2 Digital OUT 64 DOUT Signal processor block Servo block ...
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... Pin Configuration ASYE 62 MD2 63 DOUT 64 LRCK 65 PCMD 66 BCK 67 EMPH 68 XTSL XTAI 71 XTAO 72 SOUT 73 SOCK 74 XOLT 75 SQSO 76 SQCK 77 SCSY 78 SBSO 79 EXCK – 3 – CXD3008Q TES1 36 TEST FRDR 34 FFDR 33 32 TRDR 31 TFDR 30 SRDR SFDR FSTO 26 SSTP MDP 25 LOCK 24 23 PWMI FOK 22 21 DFCT ...
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... Disc innermost track detection signal input. 27 FSTO 2/3 frequency division output for XTAI pin. 28 Digital power supply — — Sled drive output. SFDR Sled drive output. SRDR TFDR Tracking drive output. 32 TRDR Tracking drive output. 33 Focus drive output. FFDR Description – 4 – CXD3008Q ...
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... Asymmetry circuit on/off (low = off, high = on). 63 MD2 I Digital Out on/off control (low = off, high = on). 64 DOUT Digital Out output. 65 LRCK D/A interface. LR clock output PCMD D/A interface. Serial data output (two's complement, MSB first). 67 BCK D/A interface. Bit clock output. Description ) DD – 5 – CXD3008Q ...
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... XROF is generated when the 32K RAM exceeds the ±28F jitter margin. Combination of Monitor Pin Outputs Command bit MTSL0 MTSL1 0 0 XUGF MNT0 0 1 RFCK 1 0 Description Output data XPCK GFS C2PO MNT1 MNT2 MNT3 XPCK XROF GTOP – 6 – CXD3008Q ...
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... DD DD Conditions Min. Typ. V ( (2) 0. Schmitt input V ( (3) Analog input ( –2mA V – 4mA ( –6mA V – 4mA ( –0.28mA V – 0.36mA ( – ( – ( 1.5 to 3.5V – ( 5.0V – – 7 – CXD3008Q Applicable Max. Unit pins µ µ µA 7 600 µA 8 ...
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... V Item Symbol Min. Input amplitude V 2 5.0V ± 5 Typ. Max. Unit 34 MHz = AV = 5.0V ± 5 Typ. Max. Unit 500 ns ns 500 1000 WLX V IHX V 0.9 IHX 0.1 IHX V ILX = AV = 5.0V ± 5 Typ. Max. Unit + 0.3 Vp – 8 – CXD3008Q ...
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... Only when $44 and $45 are executed. 1 WCK CLOK DATA XLAT EXCK SQCK COUT t WT 1/f T SBSO SQSO 0V, Topr = –20 to +75° Min. Typ. Max. 0.65 CK 750 WCK 300 SU 300 H 300 D 750 WL 0.65 T 750 7 WCK – 9 – CXD3008Q Unit MHz MHz ns kHz µs ...
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... When settings related to DFCT signal generation are Typ. t SPW 1/f SCLK MSB Unit Min. Typ. Max. 16 MHz 31 µ 5.0V ± 5 Symbol Min. Typ COUT f 40 MIRR f 5 DFCTH B – 10 – CXD3008Q · · · · · · LSB = 0V, Topr = –20 to +75°C) SS Max. Unit Conditions kHz 1 kHz 2 kHz 3 ...
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... List of Servo Filter Coefficients...................................................................................................... 121 § 5-20. Filter Composition.......................................................................................................................... 123 § 5-21. TRACKING and FOCUS Frequency Response ............................................................................ 129 [6] Application Circuit .................................................................................................................................. 130 Explanation of abbreviations AVRG: Average AGCNTL: Auto gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect – 11 – CXD3008Q ...
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... CPU Interface Command Table Total bit length for each register Register Total bit length 8 bits bits bits 20 bits 7 28 bits 8 28 bits bits B 24 bits 28 bits C 20 bits D 20 bits E D18 D19 D20 D21 D22 D23 – 12 – CXD3008Q 750ns or more Valid ...
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... FOCUS GAIN DOWN PHASE COMPENSATE FILTER A K2B 44 FOCUS GAIN DOWN DEFECT HOLD GAIN K2C 4E FOCUS GAIN DOWN PHASE COMPENSATE FILTER B K2D 1B FOCUS GAIN DOWN OUTPUT GAIN K2E 00 NOT USED K2F 00 NOT USED Fix indicates that normal preset values should be used. CONTENTS – 28 – CXD3008Q ...
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... FOCUS HOLD FILTER INPUT GAIN K49 7F FOCUS HOLD FILTER A-H K4A 7F FOCUS HOLD FILTER A-L K4B 79 FOCUS HOLD FILTER B-H K4C 17 FOCUS HOLD FILTER B-L K4D 54 FOCUS HOLD FILTER OUTPUT GAIN K4E 00 NOT USED K4F 00 NOT USED CONTENTS – 29 – CXD3008Q ...
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... FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg Reg. FBIAS Count STOP SSTP XBUSY FOK 0 GFS COMP COUT OV64 0 – 30 – CXD3008Q Output data length — — — — — — 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits — — — ...
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... High when Reg.B is latched, toggles each time the Reg.B number is counted through COUT. While $44 and $45 are being executed, toggles with each COUT 8-count instead of the Reg.B number. Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing OV64 through the sync detection filter. – 31 – CXD3008Q ...
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... Brake (B) Data 2 MAX timer value AS0 MT3 MT2 MT1 AS2 MT0 LSSL 2.9ms 0 0.18s 1 TR3 TR2 0.18ms 0.09ms 0.36ms 0.18ms – 32 – CXD3008Q Data 3 Timer range MT0 LSSL AS1 AS0 RXF RXF 1 RXF 0 RXF 1 RXF RXF = 0 Forward RXF = 1 Reverse Timer range ...
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... MIRR signal is counted. For fine search, the COUT signal is counted. Data 2 KICK (F) KF2 KF1 SD0 KF3 SD3 SD2 23.2ms 11.6ms 11.6ms 5.8ms KF3 KF2 0.72ms 0.36ms Data 1 Data – 33 – CXD3008Q KF0 SD1 SD0 5.8ms 2.9ms 2.9ms 1.45ms KF1 KF0 0.09ms 0.18ms Data 3 Data ...
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... See mute conditions (1), (2), and (4) to (6) under $AX commands for other mute conditions. Data 2 D20 D19 D18 D17 VCO WSEL ASHS SOCT0 SEL1 Processing Processing Processing DOUT Mute D.out Mute F DOUT output OFF 0dB – – 34 – CXD3008Q D16 VCO SEL2 DA output for 48-bit slot 0dB – dB 0dB – dB 0dB – dB ...
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... Output of multiplier PLL VCO1 is 1/4 frequency-divided Output of multiplier PLL VCO1 is 1/8 frequency-divided. Application Anti-rolling is enhanced. Sync window protection is enhanced. Function Processing Data VCO KSL3 KSL2 KSL1 KSL0 SEL2 See the previous page. Processing Processing – 35 – CXD3008Q —: Don't care ...
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... C2 error quadruple correction is performed even when DSPB = 1. Command bit SCOR SEL = 0 WDCK signal is output. SCOR SEL = 1 GRSCOR (protected SCOR) is output. Used when outputting GRSCOR from the WDCK pin. Processing Processing Data SCOR 0 ERC4 SCSY SOCT1 TXON TXOUT OUTL1 OUTL0 SEL Processing Processing Processing – 36 – CXD3008Q Data ...
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... WFCK, XPCK C4M, WDCK and FSTO outputs are set to low. OUTL1 = 1 The V16M output is low when VCO2 THRU = 0. Command bit OUTL0 = 0 PCMD, BCK, LRCK and EMPH are output. OUTL0 = 1 PCMD, BCK, LRCK and EMPH outputs are low. Processing Processing Processing Processing Processing – 37 – CXD3008Q ...
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... The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels for STEREO. D21 D20 D19 D18 A.SEQ BiliGL BiliGL 1 ON-OFF MAIN SUB Processing BiliGL MAIN = 1 MAIN Mute – 38 – CXD3008Q Data 2 D17 D16 FLFC 1 ...
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... D19 D18 Mute ATT PCT1 PCT2 Processing Processing Command bit ATT = 0 ATT = 1 PCM Gain ECC error correction ability 0dB C1: double; C2: quadruple 0dB C1: double; C2: quadruple Mute C1: double; C2: double 0dB C1: double; C2: double – 39 – CXD3008Q Data 2 D17 D16 0 SOC2 Meaning Attenuation off. –12dB ...
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... Data 6 Command EFM playability reinforcement function Command bit ARDTEN = 0 Normal playback is performed. ARDTEN = 1 EFM playability reinforcement function is turned on. Note) Set these command bits when the disc is not played back. Processing Data 2 Data ARDTEN Data Processing – 40 – CXD3008Q Data 4 Data ...
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... When the command bit is used in the existing state, set to the $CX commands. When the command bit is used with the $AC address, make the settings same as for SFP3 to SFP0 set with the $CX commands. Data AVW 0 SFP5 SFP4 SFP3 SFP2 SFP1 SFP0 Processing Processing – 41 – CXD3008Q Data ...
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... Traverse monitor 0 count setting Command bit MTSL1 MTSL0 0 0 XUGF 0 1 MNT0 1 0 RFCK VARI VARI USE Processing Processing Data 1 Data Data MTSL1 MTSL0 Output data XPCK GFS C2PO MNT1 MNT2 MNT3 XPCK XROF GTOP – 42 – CXD3008Q Data Data 3 Data ...
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... This command controls the VPCO pin signal. The VPCO output can be controlled with this setting. Data Gain Gain Gain Gain PCC1 PCC0 MDS1 MDS0 DCLV0 DCLV1 Gain CLVS 0dB 0dB Gain Gain MDS1 MDS0 Processing – 43 – CXD3008Q D0 GMDS –6dB 0dB +6dB ...
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... Sets the frame sync backward protection times. The setting range (Hex). See "§ 4-2. Frame Sync Protection" regarding frame sync protection. • The CXD3008Q can serially output the 40 bits (10 BCD codes) of error monitor data selected by EDC0 to 7 from the SQSO pin and monitor this data using a microcomputer. ...
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... Bottom hold at a cycle of RFCK/32 in CLVS mode Bottom hold at a cycle of RFCK/16 in CLVS mode Peak hold at a cycle of RFCK/4 in CLVS mode Peak hold at a cycle of RFCK/2 in CLVS mode. Processing 1 when 1. 2 when 0. D0 Gain CLVS See "$CX commands". Description – 45 – CXD3008Q ...
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... Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high. 2. The values in parentheses are for when DSPB 3.5 3 2.5 2 1.5 1 0.5 F0 VP0 to VP7 setting value [HEX] Data VP4 VP3 VP2 VP1 Processing Processing speed speed speed – 46 – CXD3008Q Data VP0 0 0 CTL1 CTL0 ...
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... The crystal is the reference to the internal clock.) Processing Example of command Setting value of pitch [%] setting +51.2 $D60080 : +25.7 $D6FF80 +25.6 $D600C0 : +0.1 $D6FFC0 0.0 $D60000 : –25.5 $D6FF00 –25.6 $D60040 : –48.7 $D6E740 – 47 – CXD3008Q : : : : ...
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... HIFC LPWR VPON VPCO CLV CLV CAV CAV VCO-C – 48 – CXD3008Q Data VC2C HIFC LPWR VPON Description 1 Description Crystal reference CLV servo. Used for playback in CLV-W 2 mode. Spindle control with VP0 to 7. Spindle control with the external PWM. 3 VCO control ...
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... Timing chart 1-11 1-12 1-13 Data Gain 0 0 CAV0 • This sets the gain when controlling the spindle with the phase comparator in CAV-W mode. – 49 – CXD3008Q ...
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... MDP L (b) BRAKE BRAKE Z MDP L (b) BRAKE BRAKE MDP Z (b) BRAKE BRAKE MDP L (b) BRAKE BRAKE MDP Z (b) BRAKE – 53 – CXD3008Q STOP MDP Z (c) STOP STOP MDP Z (c) STOP STOP MDP Z (c) STOP STOP Z MDP (c) STOP STOP MDP Z (c) STOP ...
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... CAV-W mode EPWM = LPWR = 0 Acceleration MDP 264kHz 3.8µs Timing Chart 1-15 CAV-W mode EPWM = LPWR = 1 Acceleration MDP 264kHz 3.8µs n · 236 (ns The BRAKE pulse is masked when LPWR = 1. The BRAKE pulse is masked when LPWR = 1. – 54 – CXD3008Q Z Deceleration Z Deceleration Z Z Deceleration Z ...
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... Timing Chart 1-16 CAV-W mode EPWM = 1, LPWR = 0 H PWMI L H MDP L Timing Chart 1-17 CAV-W mode EPWM = LPWR = 1 H PWMI MDP Acceleration Acceleration The BRAKE pulse is masked when LPWR = 1. – 55 – CXD3008Q Deceleration ...
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... As a result, the 96-bit clock must be input in peak meter mode. • The absolute time after peak is stored in the memory in peak meter mode. (See Timing Chart 2-3.) • The high and low intervals for SQCK should be between 750ns and 120µs. – 56 – CXD3008Q ...
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... Timing Chart 2-1 Internal PLL clock 4.3218 ± MHz WFCK SCOR EXCK SBSO WFCK SCOR EXCK · SBSO S0 Same 750ns max S0 · · Same Subcode P.Q.R.S.T.U.V.W Read Timing – 57 – CXD3008Q ...
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... VF0 the result obtained by counting V16M/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTAI, XTAO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). Load m – 61 – CXD3008Q ...
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... Therefore, the cycles for the Fs system clock, PCM data and others output from this LSI change according to the rotational velocity of the disc. Note) The capture range for this mode is theoretically up to the signal processing limit. Note) Set FLFC to 1 for this mode – 63 – CXD3008Q ...
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... V16M = 32 The VCO1 oscillation frequency is determined by V16M. The VCO1 frequency can be expressed by the following equation. • When DSPB = 0 49 VCO1 = V16M 24 • When DSPB = 1 49 VCO1 = V16M 16 n: VP0 to 7 setting value l: VPCTL0, 1 setting value – 64 – CXD3008Q ...
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... Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode CLV-W Mode CLV-W CLVP CLV-W MODE START KICK $E8000 Mute OFF $A00XXXX CAV-W $E665X (CLVA) NO ALOCK = H ? YES CLV-W $E60CX (CLVA) (WFCK PLL) YES ALOCK = Fig. 3-2. CLV-W Mode Flow Chart – 65 – CXD3008Q Operation mode Spindle mode Time ...
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... Switch to VCO control mode. $E00510 EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0 HIFC = VPON = 1 Transfer Transfer VP0 to VP7. ( $DX XX Track Jump Subroutine Transfer Switch to normal-speed playback mode. $E66500 EPWM = SFSL = VC2C = LPWR = 0 SPDC = ICAP = HIFC = VPON = 1 Access END – 66 – CXD3008Q corresponds to VP0 to VP7.) ...
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... EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD3008Q has a built-in three-stage PLL. • The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are necessary. ...
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... Digital PLL Spindle rotation information 1/2 1/32 1/2 1/l 1 256 (VPCTL0, 1) (VP7 to 0) 1/K (KSL1, 0) VPON 1/M 1/N 1/K (KSL3, 2) RFPLL – 68 – CXD3008Q CLV-W CAV-W VPCO CLV-N CLV-W /CLV-N LPF CAV-W VCOSEL2 VCTL VCO2 V16M PCO FILI FILO CLTV VCO1 VCOSEL1 ...
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... For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. • The CXD3008Q uses refined super strategy to achieve double correction for C1 and quadruple correction for C2. • In addition, to prevent C2 miscorrection pointer is attached to data after C1 correction according to the C1 error status, the playback status of the EFM signal, and the operating status of the player. • ...
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... MNT1 MNT0 § 4-4. DA Interface • The CXD3008Q supports the 48-bit slot interface as the DA interface. 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. ...
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... There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD3008Q supports type 2 form 1. The channel status clock accuracy is automatically set to level II when using the crystal clock and to level III in CAV-W mode or variable pitch mode ...
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... COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. – 73 – CXD3008Q ...
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... COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator has stabilized. 16 tracks. After kicking the actuator and sled, the traverse for the traverse monitor counter which is set with register B, and 16 tracks. Like the 2N-track jump, COUT is used for counting – 74 – CXD3008Q 16 tracks, ...
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... Command for $03 DSSP Fig. 4-6-(b). Auto Focus Timing Chart Auto focus Focus search up FOK = H NO YES Check whether FZC is FZC = H NO continuously high for the period of time E set with register 5. YES FZC = L NO YES Focus servo ON END Blind E – 75 – CXD3008Q $08 ...
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... Fig. 4-7-(b). 1-Track Jump Timing Chart 1 Track Track FWD kick (REV kick for REV jump) sled servo OFF WAIT (Blind A) COUT = NO YES Track REV (FWD kick for REV jump) kick WAIT (Brake B) Track, sled servo ON END Brake B $2C ($28) – 76 – CXD3008Q $25 ...
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... Fig. 4-8-(b). 10-Track Jump Timing Chart 10 Track Track, sled FWD kick WAIT (Blind A) (Counts COUT COUT = YES Track, REV kick Checks whether the COUT cycle is longer than overflow Overflow ? NO YES Track, sled servo ON END COUT 5 count $2E ($2B) – 77 – CXD3008Q 5) Overflow C $25 ...
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... Track Track, sled FWD kick WAIT (Blind A) Counts COUT for the first 16 times COUT (MIRR and MIRR for more times. NO YES Track REV kick C = Overflow NO YES Track servo ON WAIT (Kick D) Sled servo ON END Overflow C $2E ($2B) $26 ($27) – 78 – CXD3008Q Kick D $25 ...
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... FWD Kick WAIT (Kick F) Traverse Speed Ctrl (Overflow G) COUT = N? NO YES Track Servo ON Sled REV Kick WAIT (Kick D) Track Sled Servo ON END Fig. 4-10-(a). Fine Search Flow Chart Traverse Speed Control (Overflow G) & COUT N count – 79 – CXD3008Q Kick D $27 ($26) $25 ...
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... Command for DSSP $22 ($23) Fig. 4-11-(b). M-Track Move Timing Chart M Track Move Track Servo OFF Sled FWD Kick WAIT (Blind A) Counts COUT for M Counts MIRR for M COUT (MIRR YES Track, Sled Servo OFF END COUT (MIRR) M count – 80 – CXD3008Q 16. 16. $20 ...
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... LPWR MDP Up/down signal from CLVS servo Frequency error for CLVP servo Phase error for CLVP servo Spindle drive signal from the microcomputer for CAV servo Fig. 4-12. Block Diagram – 81 – CXD3008Q MDP Error Measure Over Sampling Filter-1 Gain MDP ...
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... Playback Speed In the CXD3008Q, the following playback modes can be selected through different combinations of XTAI, XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode. XTSL ...
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... Asymmetry Correction Fig. 4-13 shows the block diagram and circuit example. ASYE R1 RFAC R1 BIAS Fig. 4-15. Asymmetry Correction Application Circuit ASYO R1 R2 ASYI – 83 – CXD3008Q ...
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... LSB first. • Data which can be stored in the LSI is 1 packet (4 packs). Subcode Decoder Fig. 4-14. Block Diagram of CD TEXT Demodulation Circuit TXON CD TEXT Decoder – 84 – CXD3008Q EXCK SBSO SQCK SQSO TXOUT ...
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... MCK = 128Fs) Input range: 0.3V DD Output format: 7-bit PWM Other: Sled move FOK, MIRR, DFCT signal generation RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 0.43V DD Other: RF zero level automatic measurement – 86 – CXD3008Q : Supply voltage) ...
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... XT4D XT2D XT1D Frequency division ratio Table 5-1. – 87 – CXD3008Q MCK 1 256Fs 1/2 128Fs 1/2 128Fs 1 512Fs 1/2 256Fs 1/4 128Fs 1/4 128Fs Fs = 44.1kHz, : Don’t care ...
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... DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.) The CXD3008Q can measure the average of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD3008Q, and is able to cancel the DC offset. ...
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... The number of steps by which the count value changes can be selected from steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 A: Register mode B: Counter mode C: Counter mode (when stopped) – 89 – CXD3008Q V 0.4. DD ...
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... TLC2 · TLD2 To TRK In register – – TRVSC register TLC2 To FCS In register – + FBIAS register FBON To FZC register – register – To SLD In register – TLC2 · TLD2 To TRK In register – TRVSC register TLC2 To FCS In register + FBIAS register FBON To FZC register – CXD3008Q ...
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... The default settings aim for 0dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. Max. 11.4µs Timing Chart 5-4. – 91 – CXD3008Q AGCNTL completion ...
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... AGCNTL coefficient reaches the appropriate value and stops changing, the CXD3008Q confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self stop mode) This self-stop mode can be canceled by setting AGS to 0 ...
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... FOCUS SERVO OFF, 0V OUT 0 1 FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP Table 5-6. $02 $03 and performing only FCS search operation. $00 $02 $03 FCSDRV RF FOK FE 0 FZC – 93 – CXD3008Q : Don't care $08 Fig. 5-8. ...
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... The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD3008Q has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 5-17.) ...
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... Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 – Peak Hold1 DFCT MIRR Comp (Mirror comparator level Fig. 5-11. SDF (Defect comparator level Fig. 5-12. – 95 – CXD3008Q ...
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... It also can be monitored from the ATSK pin by setting the ASOT command of $ Anti Shock TE Filter TRK Gain Up Filter TRK Gain Normal Filter Hold Filter DFCT Servo Filter Fig. 5-13. ATSK Comparator TRK PWM Gen Fig. 5-14. – 96 – CXD3008Q Hold register EN SENS ...
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... D19 to D16 ANTI SHOCK ANTI SHOCK OFF 1 BRAKE ON 0 BRAKE OFF TRACKING GAIN NORMAL 0 TRACKING GAIN TRACKING GAIN UP FILTER SELECT 1 0 TRACKING GAIN UP FILTER SELECT 2 Table 5-17. – 97 – CXD3008Q Outer track Inner track FWD Servo ON JMP Fig. 5-16. : Don't care ...
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... TRK AGCNTL coefficient result $391C: TRVSC adjustment result $391D: FBIAS register value t SPW · · · 1/f SCLK MSB · · · Fig. 5-18. Symbol Min. Typ. f SCLK t 31.3 SPW t 15 DLS Table 5-19. – 98 – CXD3008Q LSB Max. Unit MHz 16 ns µs ...
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... TRDR 180ns MCK 5.6448MHz Output value –A 64t MCK At MCK 32t 32t 32t MCK MCK MCK MCK MCK 2 2 Timing Chart 5-20 DRV RDR FDR Fig. 5-21. Drive Circuit – 99 – CXD3008Q Output value 0 64t MCK 32t 32t MCK MCK MCK ...
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... When MRS = 1, the time constant is delayed compared to the normal state. The duration of MIRR = high, which is caused by the affection of the RFDC signal pulse-formed noise and the like, is suppressed by setting MRS to 1. D10 KA2 KA1 KA0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D10 Processing Processing – 100 – CXD3008Q MRS ...
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... BK7, BK8 and BK9. (See Table 5-25c.) An example of characteristics is shown in Fig. 5-26c. This booster is used exclusively for the TRK filter. The sampling frequency is 88.2kHz (when MCK = 128Fs). Note 44.1kHz D10 D10 FLB1 TLB2 FHB TLB1 0 HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 – 101 – CXD3008Q ...
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... Table 5-25b. LowBooster-2 setting LB2S1 LB2S0 BK7 — –255/256 1023/1024 0 0 –511/512 2047/2048 1 1 –1023/1024 4095/4096 1 Table 5-25c. – 102 – CXD3008Q BK2 BK3 96/128 2 112/128 2 120/128 2 BK5 BK6 1/4 1/4 1/4 BK8 BK9 1/4 1/4 1/4 ...
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... Fig. 5-26a. Servo HighBooster Characteristics [FCS, TRK] (MCK = 128Fs) HBST1 = 0 HBST1 = 1, HBST0 = 100 1k Frequency [Hz 100 1k Frequency [Hz] HBST1 = 1, HBST0 = 1 3 – 103 – CXD3008Q 10k 10k ...
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... Fig. 5-26b. Servo LowBooster1 Characteristics [FCS, TRK] (MCK = 128Fs) LB1S1 = 0 LB1S1 = 1, LB1S0 = 100 1k Frequency [Hz] 100 1k Frequency [Hz] LB1S1 = 1, LB1S0 = 1 3 – 104 – CXD3008Q 10k 10k ...
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... Fig. 5-26c. Servo LowBooster2 Characteristics [FCS, TRK] (MCK = 128Fs) LB2S1 = 0 LB2S1 = 1, LB2S0 = 100 1k Frequency [Hz] 100 1k Frequency [Hz] LB2S1 = 1, LB2S0 = 1 3 – 105 – CXD3008Q 10k 10k ...
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... After DFCT in §5-9 is switched to low, the time when the new DFCT output is enabled (output prohibit time) is set. IDFT1 IDFT0 D10 IDFT1 IDFT0 DFCT pin L DFCT in §5-9 DFCT in §5 New DFCT H DFCT in §5-9 New DFCT signal output prohibit time 204.08µs 294.78µs 408.16µs 612.24µs : preset – 106 – CXD3008Q ...
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... FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 D10 FB9 FB8 FB7 FB6 FB5 V /5 respectively D10 TV9 TV8 TV7 TV6 TV5 V /5 respectively – 107 – CXD3008Q — FB4 FB3 FB2 FB1 — and DD : supply voltage TV4 TV3 TV2 TV1 TV0 ...
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... FTZ Focus search speed [V/ 0.673 0.449 0.336 1. 1. 0.897 0.769 preset PWM driver supply voltage PWM driver supply voltage D10 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 PWM driver supply voltage – 108 – CXD3008Q ...
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... AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs) Default value: 0 (256ms) D10 0. supply voltage); FE input conversion DD DD Slice level 1/4 V 0.4 DD 1/8 V 0.4 DD 1/16 V 0.4 DD 1/ preset 16/ PWM driver supply voltage FE/TE input conversion 1/32 V 0.4 DD 1/16 V 0.4 DD 1/16 V 0.4 DD 1 preset – 109 – CXD3008Q ...
Page 110
... Focus zero level compensation for FCS In register (on/off) TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with are accepted every 2.9ms. (when MCK = 128Fs) All commands are on when 1. D10 – 110 – CXD3008Q ...
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... RFDC envelope (bottom) RFDC envelope (peak) RFDC envelope (peak) – (bottom) VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal – 111 – CXD3008Q Readout data length 8 bits 16 bits 8 bits $399F $399E 8 bits 9 bits $399D $399C 9 bits ...
Page 112
... Relative gain TPS1 0dB 0 +6dB 0 +12dB 1 +18dB 1 – 112 – CXD3008Q SJHD INBK MTI0 The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step 9 is approximately 1 ...
Page 113
... V 0. 24/256 V 0. 28/256 V 0. 32/256 V 0. 40/256 V 0. 48/256 V 0. 56/256 V 0. preset V 1.14V) DD Slice level 0.0156 V 1.14 DD 0.0234 V 1.14 DD 0.0313 V 1.14 DD 0.0391 V 1. supply voltage DD DFCT maximum time No timer limit 2.00ms 2.36 2.72 – 113 – CXD3008Q ...
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... V 1.14 22.05 DD 0.0861 V 1.14 44.1 DD 0.172 V 1.14 88.2 DD 0.344 V 1.14 176 preset supply voltage DD 1.14V/ms, 352.8kHz) DD Count-down speed [V/ms] [kHz] 0.344 V 1.14 176.4 DD 0.688 V 1.14 352.8 DD 1.38 V 1.14 705.6 DD 2.75 V 1.14 1411 preset supply voltage DD – 114 – CXD3008Q ...
Page 115
... Number of count-up steps per cycle D10 BTS1 BTS0 MRC1 MRC0 TZC STZC HPTZC DTZC COUT pin output STZC HPTZC COUT : preset, —: don't care – 115 – CXD3008Q MRC1 MRC0 Setting time [µ 5.669 0 1 11.338 1 0 22.675 1 1 45.351 : preset (when MCK = 128Fs) ...
Page 116
... TLD0 — D10 Traverse center correction TRK filter SLD filter OFF OFF OFF Tracking zero level correction TRK filter SLD filter OFF OFF OFF VC level correction TRK filter SLD filter OFF OFF OFF : preset, —: don't care – 116 – CXD3008Q ...
Page 117
... Input coefficient sign inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, the CXD3008Q outputs the servo drives which have the reversed phase to the error inputs.. Negative input coefficient ...
Page 118
... XT2D and XT4D. D10 MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source. – 118 – CXD3008Q LKIN COIN MDFI MIRI XT1D : preset, —: don't care ...
Page 119
... V 0 1/8 V 0.4 DD XT4D Frequency division ratio 0 According to XTSL — 1/1 — 1/2 1 1/4 – 119 – CXD3008Q AGHF 0 See $37 for AGGF and AGGT. The presets are AGG4 = 0, AGGF = 1 and AGGT = 1. : preset, —: don't care 0.4 : preset, —: don't care ...
Page 120
... Clock input Offset adjustment, gain adjustment Latch enable input Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. – 120 – CXD3008Q ··· ··· MSB ··· LSB To the 7-segment LED To the 7-segment LED ...
Page 121
... FOCUS GAIN DOWN PHASE COMPENSATE FILTER A K2B 44 FOCUS GAIN DOWN DEFECT HOLD GAIN K2C 4E FOCUS GAIN DOWN PHASE COMPENSATE FILTER B K2D 1B FOCUS GAIN DOWN OUTPUT GAIN K2E 00 NOT USED K2F 00 NOT USED Fix indicates that normal preset values should be used. CONTENTS – 121 – CXD3008Q ...
Page 122
... FOCUS HOLD FILTER INPUT GAIN K49 7F FOCUS HOLD FILTER A-H K4A 7F FOCUS HOLD FILTER A-L K4B 79 FOCUS HOLD FILTER B-H K4C 17 FOCUS HOLD FILTER B-L K4D 54 FOCUS HOLD FILTER OUTPUT GAIN K4E 00 NOT USED K4F 00 NOT USED CONTENTS – 122 – CXD3008Q ...
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... K02 K04 Note) Set the MSB bit of the K02 and K04 coefficients to 0. Slice M09 –1 –1 Z K14 K15 – 127 – CXD3008Q TRK AUTO Gain 2 –7 M02 K05 K07 PWM SLD MOV TZC Reg M0A AUTO Gain Slice Reg – ...
Page 128
... Note) Set the MSB bit of the K42 and K44 coefficients to 0. M10 M11 – K49 K4B –7 – K4A K4C Note) Set the MSB bit of the K4A and K4C coefficients to 0. – 128 – CXD3008Q M0A Anti Shock Comp K35 Reg –1 Z K33 K34 AVRG Reg M19 TRK K45 Hold Reg Z – ...
Page 129
... When using the preset coefficients with the boost function off. FOCUS frequency response NORMAL GAIN DOWN 10 100 1k f – Frequency [Hz] When using the preset coefficients with the boost function off. – 129 – CXD3008Q 180° 90° G 0° –90° –180° 20k 180° 90° ...
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... CXD3008Q ...
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... QFP (PLASTIC) 16.0 ± 0.2 1.6MAX 14.0 ± 0.1 1 0. 0.32 ± 0.1 DETAIL B : SOLDER PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING QFP-80P-L052 P-QFP80-14X14-0.65 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 1.6g – 131 – CXD3008Q 0 ...