K9F1208U0A-VCB0 Samsung, K9F1208U0A-VCB0 Datasheet
K9F1208U0A-VCB0
Related parts for K9F1208U0A-VCB0
K9F1208U0A-VCB0 Summary of contents
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... Improvement schedule : The components without this restriction will Workaround : Relax the relevant timing parameters according to the table. Table Parameters Specification Relaxed Condition Sincerely, chwoosun@sec.samsung.com Product Planning & Application Eng. Memory Division Samsung Electronics Co. be available from work week 23 or after. tWC tWH tWP ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Document Title 64M x 8 Bit , 32M x 16 Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 0.1 TBGA(K9F12XXX0A-DCB0/DIB0) size information is changed. (before /0.8mm pitch , Width 1.0 mm (after ) To Be Decided. 0.2 TBGA(K9F12XXX0A-DCB0/DIB0) size information is changed. (before /0.8mm pitch , Width 1.0 mm, to (after) 8 ...
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... Command Register Operation Intelligent Copy-Back Unique ID for Copyright Protection Package - K9F12XXU0A-YCB0/YIB0 48 - Pin TSOP I ( 0.5 mm pitch) - K9F12XXX0A-DCB0/DIB0 63- Ball TBGA - K9F1208U0A-VCB0/VIB0 48 - Pin WSOP I (12X17X0.7mm) - K9F12XXU0A-PCB0/PIB0 48 - Pin TSOP I ( 0.5 mm pitch)- Pb-free Package - K9F12XXX0A-HCB0/HIB0 63- Ball TBGA - Pb-free Package - K9F1208U0A-FCB0/FIB0 48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package * K9F1208U0A-V,F(WSOPI ) is the same device as K9F1208U0A-Y,P(TSOP1) except package type ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 PIN CONFIGURATION (TSOP1) X16 X8 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C R/B R N.C N.C N.C N.C Vcc Vcc Vss Vss N.C N.C N.C N.C CLE CLE ALE ALE N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 ¡Æ 0~8 0.45~0.75 0.018~0.030 K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 PIN CONFIGURATION (TBGA N.C N.C N.C A /WP ALE Vss / /RE CLE I/ I/O1 NC VccQ I/O5 H Vss I/O2 I/O3 I/O4 N.C N.C N.C N.C Top View K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 K9F12XXX0A-DCB0,HCB0/DIB0,HIB0 5 6 N.C N.C N.C N.C N.C N.C N.C A /WE R ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 63-Ball TBGA (measured in millimeters) Top View 8.50 0.10 #A1 0.10MAX K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 6 (Datum (Datum 63- 0.45 0.05 0. Side View 15.00 0.10 5 FLASH MEMORY Bottom View #A1 INDEX MARK(OPTIONAL) 8.50 A 0.10 0. 7.20 0. 4.00 0. 2.00 0.45 0.05 B ...
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... CE DNU N.C Vcc Vss N.C DNU CLE ALE WE WP N.C N.C DNU N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F #1 #24 K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-VCB0,FCB0/VIB0,FIB0 ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The 0 7 (K9F1208X0A) I/O pins float to high-z when the chip is deselected or when the outputs are disabled. I/O ~ I/O I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper- ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Figure 1-1. K9F1208X0A (X8) FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-1. K9F1208X0A (X8) ARRAY ORGANIZATION 128K Pages 1st half Page Register ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Figure 1-2. K9F1216X0A (X16) FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-2. K9F1216X0A (X16) ARRAY ORGANIZATION 128K Pages ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Product Introduction The K9F1208X0A is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Memory Map The device is arranged in four 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte(X8 device) or 264 word(X16 device) page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F12XXX0A-XCB0 Temperature Under Bias K9F12XXX0A-XIB0 K9F12XXX0A-XCB0 Storage Temperature K9F12XXX0A-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 VALID BLOCK Parameter Valid Block Number NOTE : K9F12XXX0A 1. The may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits program factory-marked bad blocks ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time NOTE : 1 ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Pointer Operation of K9F1208X0A(X8) Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’ 00h’ command sets the pointer to ’ A’ area(0~255byte), ’ 01h’ command sets the pointer to ’ B’ area(256~511byte), and ’ 50h’ command sets the pointer to ’ ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Pointer Operation of K9F1216X0A(X16) Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’ 00h’ command sets the pointer to ’ A’ area(0~255word), and ’ 50h’ command sets the pointer to ’ B’ area(256~263word). With these commands, the starting column address can be set to any of a whole page(0~263word). ’ ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 System Interface Using CE don’ t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte 1264word page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addi- tion, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Device K9F1208X0A(X8 device) K9F1216X0A(X16 device) NOTE: 1. I/O8~15 must be set to "0" during command or address input. 2. I/O8~15 are used only for data bus. * Command Latch Cycle CLE CE WE ALE I Address Latch Cycle t CLS CLE ALS ALE I/O X K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 * Input Data Latch Cycle CLE CE t ALS ALE I/Ox * Serial access Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 DIN 0 ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 * Status Read Cycle CLE I/O X READ1 OPERATION (READ ONE PAGE) CLE ALE RE N Address 00h or 01h I Column Address R/B X8 device : m = 528 , Read CMD = 00h or 01h X16 device : m = 264 , Read CMD = 00h ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Read1 Operation (Intercepted by CE) CLE CE WE ALE I/O 00h or 01h Column Address R/B Read2 Operation (Read One Page) CLE CE WE ALE RE I/O 50h R/B M Address K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Sequential Row Read Operation ( Within a Block ) CLE CE WE ALE RE 00h I R/B M Page Program Operation CLE ALE RE 80h I Sequential Data Column Input Command Address R/B K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 Dout ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 BLOCK ERASE OPERATION CLE ALE RE I/O 60h Page(Row) Address R/B Auto Block Erase Setup Command K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 (ERASE ONE BLOCK DOh Erase Command 26 FLASH MEMORY t BERS 70h I/O 0 Busy I/O =0 Successful Erase 0 Read Status ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 27 FLASH MEMORY ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Multi-Plane Block Erase Operation CLE ALE RE I/O 60h Page(Row) Address R/B Block Erase Setup Command Max. 4 times repeatable * For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command. Ex.) Four-Plane Block Erase Operation ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Read ID Operation CLE CE WE ALE RE I/O 90h X Read ID Command ID Defintition Table Access command = 90H Value 1 st Byte ECh 2 nd Byte 76h 3 rd Byte A5h C0h 4 th Byte K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 t REA 00h ECh Address. 1cycle Maker Code Device Code ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Copy-Back Program Operation CLE ALE RE 00h I Column Page(Row) Address Address R/B K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 On K9F1208U0A-Y,P or K9F1208U0A-V,F CE must be held low during 8Ah Column Address Busy ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Device Operation PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis- ter along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Figure 7. Read1 Operation CLE CE WE ALE R/B RE 00h Start Add.(4Cycle) I device : X16 device : NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Figure 8. Read2 Operation CLE CE WE ALE R/B RE 50h Start Add.(4Cycle) I device : X16 device : device : Don’ t care 4 7 X16 device : are "L" Figure 9. Sequential Row Read1 Operation (only for K9F1208U0A-Y,P and K9F1208U0A-V,F valid within a block) ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Figure 10. Sequential Row Read2 Operation (only for K9F1208U0A-Y,P and K9F1208U0A-V,F valid within a block ) R/B I/O Start Add.(4Cycle) X 50h & Don’ t Care) PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 bytes(x8 device) or 264words(x16 device single page program cycle ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 BLOCK ERASE The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Restriction in addressing with Multi Plane Page Program While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for the selected pages at one operation must be the same. Figure 14 shows an example where 2nd page of each addressed block is selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure15. Figure 14. Multi-Plane Program & ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Copy-Back Program The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Multi-Plane Copy-Back Program Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is equipped with four memory planes, activating the four sets of 528 bytes(x8 device) or 264words(x16 device)page registers enables a simultaneous Multi-Plane Copy-Back programming of four pages. Partial activation of four planes is also permitted. ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216U0A-YCB0,YIB0,PCB0,PIB0 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 39 FLASH MEMORY ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacture code(ECh), and the device code (76h), Reserved(A5h), Multi plane oper- ation code(C0h) respectively. A5h must be don’ t-cared. C0h means that device supports Multi Plane operation. The command regis- ter remains in Read ID mode until further commands are issued to it ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... K9F1208U0A-VCB0,VIB0,FCB0,FIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 Data Protection & Power-up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device) or 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down. A recovery time of minimum required before internal cir- IL cuit gets ready for any command sequences as shown in Figure 24 ...