K9F4008W0A-TCB0 Samsung, K9F4008W0A-TCB0 Datasheet
K9F4008W0A-TCB0
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K9F4008W0A-TCB0 Summary of contents
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... Initial issue. 1.0 1. Changed Operating Voltage 2.7V ~ 5.5V 1.1 Data Sheet 1999 1. Added CE don’t care mode during the data-loading and reading 1.2 1. Changed device name - KM29W040AT -> K9F4008W0A-TCB0 - KM29W040AIT -> K9F4008W0A-TIB0 1.3 1.Powerup sequence is added : Recovery time of minimum required before internal circuit gets ready for any command sequences ~ 2.5V V ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 512K x 8 Bit NAND Flash Memory FEATURES Voltage Supply: 3.0V~5.5V Organization - Memory Cell Array : 512K x 8 bit - Data Register : bit Automatic Program and Erase (Typical) - Frame Program : 32 Byte in 500 s - Block Erase : 4K Byte in 6ms 32-Byte Frame Read Operation - Random Access : 15 s(Max.) - Serial Frame Access : 120ns(Min ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 Figure 1. FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE WP Figure 2. ARRAY ORGANIZATION The 1st Block (4KB) 4K Rows 1 2 (=128 Blocks) 128Bytes ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 PRODUCT INTRODUCTION The K9F4008W0A bit memory organized as 4096 rows by 1024 columns. A 256-bit data register is connected to memory cell arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. The memory array is composed of unit NAND structures in which 8 cells are connected serially. ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 PIN DESCRIPTION Command Latch Enable(CLE) The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the activating path for address to the internal address registers ...
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... Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, K9F4008W0A-TCB0 Parameter Symbol ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 VALID BLOCK Parameter Symbol Valid Block Number N NOTE : K9F4008W0A 1. The may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits or program factory-marked bad blocks ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Set-up Time Data Hold Time Write Cycle Time WE High Hold Time AC Characteristics for Operation ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The informa- tion regarding the invalid block(s) is called as the invalid block information. The invalid block information is written to the 1st or the 2nd page of the invalid block(s) with 00h data ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 K9F4008W0A Technical Notes(Continued) Error in program or erase operation Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 System Interface Using CE don’t-care. For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 32byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 * Command Latch Cycle CLE t CLS ALS ALE I Address Latch Cycle CLE ALE I CLH ALH Command t CLS ALS ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 * Input Data Latch Cycle CLE ALS WC ALE I/O ~ DIN Burst Read Cycle After Frame Access CE t REA RE I R/B NOTES : Transition is measured 200mV from steady state voltage with load ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 * Status Read Cycle CLE I READ OPERATION (READ ONE FRAME) CLE CE WE ALE 00h I Column Row Address Address R/B t CLR t CLH t REA CSTO t WHR 70h t WB tAR2 ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 READ OPERATION (INTERCEPTED BY CE) CLE CE WE ALE 00h I Column Row Address Address R/B PROGRAM OPERATION CLE ALE RE I/O ~ 80h Sequential Data Column Input Command Address Address R tAR2 Dout N ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 BLOCK ERASE OPERATION CLE CE WE ALE RE I/O ~ 60h Block Address R/B Auto Block Erase Setup Command FLASH MEMORY BERS DOh Busy Erase Command 16 ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 DEVICE OPERATION FRAME READ Upon initial device power up or after excution of Reset(FFh) command, the device defaults to Read mode. This operation is also ini- tiated by writing 00h to the command register along with three address cycles. The three cycle address input must be given for access to each new frame ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 FRAME PROGRAM The device is programmed on a frame basis. The addressing may be done in random order in a block. A frame program cycle consist of a serial data loading period in which bytes of data must be loaded into the device, and a nonvolatile programming period in which the loaded data is programmed into the appropriate cells. ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 BLOCK ERASE The Erase operation is done 4K Bytes(1 block time. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during the read, program or erase mode, the reset operation will abort these operation. In the case of Reset during Program or Erase operations, the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The device enters the Read mode after completion of Reset operation as shown Table 3 ...
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... K9F4008W0A-TCB0, K9F4008W0A-TIB0 Figure 9. Read ID Operation CLE CE WE ALE RE I Add. Input(1Cycle) 90h CLR t CEA t WHR t AR1 t REA Dout(ECh) :"0" Maker code 7 21 FLASH MEMORY A4H Dout( ) Device code ...
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Package Dimensions READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a frame program, erase or read seek completion. The R/B pin is normally high but transitions to low after program or ...
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Package Dimensions DATA PROTECTTION The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be ...
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Package Dimensions PACKAGE DIMENSIONS 44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 44(40) - TSOP2 - 400F #44(40) #1 18.81 Max. 0.741 18.41 0.10 0.725 0.004 0.805 0.35 0.10 0.032 0.014 0.004 FLASH MEMORY 0.25 0.010 #23(21) #22(20) 0.15 0.006 ...