SC3200UFH-266 Advanced Micro Devices, SC3200UFH-266 Datasheet
SC3200UFH-266
Related parts for SC3200UFH-266
SC3200UFH-266 Summary of contents
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AMD Geode™ SC3200 Processor Data Book March 2004 Publication ID: Revision 5.1 AMD Geode™ SC3200 Processor Data Book ...
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... Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice ...
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Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Revision 5.1 6.0 Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1-1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Revision 5.1 Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer . . . . . . . . . . . . . . . . . . 333 Figure 7-6. Capture Video Mode Weave Example ...
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List of Figures Figure 9-46. ECP Reverse Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Revision 5.1 8 List of Figures AMD Geode™ SC3200 Processor Data Book ...
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List of Tables Table 2-1. SC3200 Memory Controller Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Revision 5.1 Table 5-27. Banks 0 and 1 - Common Control and Status Register Map . . . . . . . . . . . . . . . . . . . . . . . . 133 ...
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List of Tables Table 6-20. F2: PCI Header Registers for IDE Controller Support Summary . . . . . . . . . . . . . . . . . . . . . 198 Table 6-21. F2BAR4: IDE ...
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Revision 5.1 Table 9-17. PCI AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD Geode™ SC3200 Processor 1.1 General Description The AMD Geode™ SC3200 processor is a member of the AMD Geode family of fully integrated x86 system chips. The SC3200 processor includes: • The Geode GX1 processor module combines advanced CPU performance ...
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Revision 5.1 1.2 Features General Features 32-Bit x86 processor 266 MHz, with MMX instruc- tion set support Memory controller with 64-bit SDRAM interface 2D graphics accelerator CCIR-656 video input port with direct video for full screen display PC/AT ...
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AMD Geode™ SC3200 Processor PCI Bus Interface: — PCI v2.1 compliant with wakeup capability — 32-Bit data path MHz — Glueless interface for an external PCI device — Fixed priority — 3.3V signal support only Sub-ISA Bus ...
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Revision 5.1 16 AMD Geode™ SC3200 Processor AMD Geode™ SC3200 Processor Data Book ...
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Architecture Overview As illustrated in Figure 1-1 on page 13, the SC3200 pro- cessor contains the following modules in one integrated device: • GX1 Module: — Combines advanced CPU performance with MMX support, fully accelerated 2D graphics, a 64-bit synchronous ...
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Revision 5.1 Table 2-1. SC3200 Memory Controller Register Summary GX_BASE+ Width Memory Offset (Bits) Type 8400h-8403h 32 R/W 8404h-8407h 32 R/W 8408h-840Bh 32 R/W 840Ch-840Fh 32 R/W 8414h-8417h 32 R/W 8418h-841Bh 32 R/W 841Ch-841Fh 32 R/W Table 2-2. SC3200 Memory ...
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Architecture Overview Table 2-2. SC3200 Memory Controller Registers (Continued) Bit Description 4 RFSHTST (Test Refresh). This bit, when set high, generates a refresh request. This bit is only used for testing purposes. 3 XBUSARB (X-Bus Round Robin). When round robin ...
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Revision 5.1 Table 2-2. SC3200 Memory Controller Registers (Continued) Bit Description GX_BASE+8408h-840Bh 31:16 RSVD (Reserved). Write as 0070h 15 RSVD (Reserved). Write SODIMM_MOD_BNK (SODIMM Module Banks - Banks 0 and 1). Selects number of module banks installed ...
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Architecture Overview Table 2-2. SC3200 Memory Controller Registers (Continued) Bit Description 11 RSVD (Reserved). Write as 0. 10:8 RRD (ACT(0) to ACT(1) Command Period, tRRD). Minimum number of SDRAM clocks between ACT and ACT command to two different component banks ...
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Revision 5.1 2.1.2 Fast-PCI Bus The GX1 module communicates with the Core Logic mod- ule via a Fast-PCI bus that can work MHz. The Fast-PCI bus is internal for the SC3200 and is connected to the ...
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Architecture Overview • Sub-ISA: See Section 3.4.7 "Sub-ISA Interface Signals" on page 73, Section 6.2.5 "Sub-ISA Bus Interface" on page 163, and Section 4.2 "Multiplexing, Interrupt Selec- tion, and Base Address Registers" on page 88 • GPIO: See Section 3.4.16 ...
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Revision 5.1 24 Architecture Overview AMD Geode™ SC3200 Processor Data Book ...
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Signal Definitions This section defines the signals and describes the external interface of the SC3200. Figure 2-1 shows the signals organized by their functional groups. Where signals are multiplexed, the default signal name is listed first and is POR# X32I ...
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Revision 5.1 POWER_EN OVER_CUR# DPOS_PORT1 USB DNEG_PORT1 Interface DPOS_PORT2 DNEG_PORT2 DPOS_PORT3 DNEG_PORT3 SIN1 SIN2+SDTEST3 SOUT1+CLKSEL1 SOUT2+CLKSEL2 Serial Ports GPIO7+RTS2#+IDE_DACK1#+SDTEST0 (UARTs)/IDE GPIO8+CTS2#+IDE_DREQ1+SDTEST4 GPIO18+DTR1#/BOUT1 Interface GPIO6+DTR2#/BOUT2+IDE_IOR1#+SDTEST5 GPIO11+RI2#+IRQ15 GPIO9+DCD2#+IDE_IOW1#+SDTEST2 GPIO10+DSR2#+IDE_IORDY1+SDTEST1 IR Port IRRX1+SIN3 Interface IRTX+SOUT3 BIT_CLK SDATA_OUT+TFT_PRSNT SDATA_IN AC97 Audio SDATA_IN2 Interface SYNC+CLKSEL3 ...
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Signal Definitions 3.1 Ball Assignments The SC3200 is highly configurable as illustrated in Figure 3-1 on page 25. Strap options and register programming are used to set various modes of operation and specific signals on specific balls. This section describes ...
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Revision 5 AD29 AD26 AD22 AD19 ...
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Signal Definitions Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number I/O 1 Ball (PU/ Buffer No. Signal Name PD) Type A1 V GND --- PWR --- IO A3 AD29 I PCI O PCI ...
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Revision 5.1 Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) I/O 1 Ball (PU/ Buffer No. Signal Name PD) Type B9 PERR# I PCI ( 22.5 PCI B10 AD15 I PCI ...
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Signal Definitions Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) I/O 1 Ball (PU/ Buffer No. Signal Name PD) Type C21 IDE_IOR0 1/4 TFTD10 O O 1/4 C22 IDE_DATA6 I TS1 TS 1/4 ...
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Revision 5.1 Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) I/O 1 Ball (PU/ Buffer No. Signal Name PD) Type F3 RD 3/5 CLKSEL0 I IN STRP (PD ) 100 F4 AD23 I ...
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Signal Definitions Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) I/O 1 Ball (PU/ Buffer No. Signal Name PD) Type N3 V GND --- PWR --- CORE N28 V PWR --- CORE N29 WEA# ...
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Revision 5.1 Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) I/O 1 Ball (PU/ Buffer No. Signal Name PD) Type 3 MD35 I V30 T 2/5 3 MD34 I V31 T ...
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Signal Definitions Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) I/O 1 Ball (PU/ Buffer No. Signal Name PD) Type AD1 NC --- --- AD2 NC --- --- AD3 NC --- --- AD4 NC --- --- AD28 ...
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Revision 5.1 Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) I/O 1 Ball (PU/ Buffer No. Signal Name PD) Type AJ2 GPIO8 I ( 22.5 CTS2 (PU ...
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Signal Definitions Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) I/O 1 Ball (PU/ Buffer No. Signal Name PD) Type 3 MD30 I AK23 T 2/5 3 MD53 I AK24 T ...
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Revision 5.1 Table 3-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name Signal Name Ball No. A0 A17 A1 D16 A2 A18 A3 A15 A4 A16 A5 A14 A6 C15 A7 B14 A8 C14 A9 B13 A10 C13 A11 ...
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Signal Definitions Table 3-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. F_TRDY# AL14 FP_VDD_ON B23, AL16 FPCI_MON D3 FPCICLK U3 FRAME# E1 GNT0# D4 GNT1# D2 GPIO0 H1 GPIO1 H2, AL12 GPIO6 AH3 ...
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Revision 5.1 Table 3-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. MD35 V30 MD36 V29 MD37 W31 MD38 W30 MD39 W29 MD40 AC31 MD41 AB29 MD42 AB30 MD43 AB31 MD44 AA29 MD45 AA31 ...
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Signal Definitions Table 3-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. V (Total of 35) A2, A30, B1, B6, IO B11, B16, B20, B25, B31, C3, C29, G2, G30, L3, M1, M2, M30, ...
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Revision 5 AD30 PCK0 REQ1# ...
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Signal Definitions Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number 1 Ball I/O Buffer Power No. Signal Name (PU/PD) Type A1 V GND --- PWR --- IO A3 AD30 I PCI O PCI ...
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Revision 5.1 Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer Power No. Signal Name (PU/PD) Type B6 AD23 I PCI O PCI A23 O O PCI B7 V GND --- SS ...
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Signal Definitions Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer Power No. Signal Name (PU/PD) Type C15 V GND --- SS C16 AV GND --- SSPLL2 SLCT I IN 5,2 C17 T TFTD15 ...
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Revision 5.1 Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer Power No. Signal Name (PU/PD) Type D10 GPIO1 I ( 22.5 IOCS1 3/5 (PU ...
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Signal Definitions Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer Power No. Signal Name (PU/PD) Type F29 TDI I IN PCI (PU ) 22.5 F30 GTEST (PD ) 22.5 F31 ...
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Revision 5.1 Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer Power No. Signal Name (PU/PD) Type L29 GPIO35 I PCI ( 22.5 PCI LAD3 I PCI (PU ...
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Signal Definitions Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer Power No. Signal Name (PU/PD) Type R18 V GND --- SS R19 V GND --- SS R28 V GND --- SS R29 V ...
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Revision 5.1 Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer Power No. Signal Name (PU/PD) Type W30 V GND --- SS W31 V PWR --- IO Y1 IDE_DATA10 I TS1 TS ...
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Signal Definitions Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer Power No. Signal Name (PU/PD) Type AF2 IDE_CS0 1/4 TFTD5 O O 1/4 AF3 SOUT1 O O 8/8 CLKSEL1 I IN ...
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Revision 5.1 Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer Power No. Signal Name (PU/PD) Type 5 MD32 I AJ15 T TS 2/5 5 MD33 I AJ16 T TS ...
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Signal Definitions Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer Power No. Signal Name (PU/PD) Type 5 MD40 I AL21 T TS 2/5 AL22 CKEA O O 2/5 AL23 MA7 O ...
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Revision 5.1 Table 3-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name Signal Name Ball No A10 L3 A11 ...
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Signal Definitions Table 3-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. F_STOP# U29 F_TRDY# U30 FP_VDD_ON V30, AB1 FPCI_MON A4 FPCICLK B18 FRAME# D8 GNT0# C5 GNT1# C6 GPIO0 D11 GPIO1 D10, N30 ...
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Revision 5.1 Table 3-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. MD33 AJ16 MD34 AH16 MD35 AK17 MD36 AJ17 MD37 AH17 MD38 AL17 MD39 AL18 MD40 AL21 MD41 AH20 MD42 AJ20 MD43 AK20 ...
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Signal Definitions Table 3-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. V (Total of 46) A2, A12, A30, B2, IO B13, B16, B19, B31, C3, C7, C10, C13, C22, C25, C29, D14, D15, ...
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Revision 5.1 3.2 Strap Options Several balls are read at power-up that set up the state of the SC3200. These balls are typically multiplexed with other functions that are outputs after the power-up sequence is complete. The SC3200 must read ...
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Signal Definitions 3.3 Multiplexing Configuration The tables that follow list multiplexing options and their configurations. Certain multiplexing options may be chosen per signal; others are available only for a group of signals. Where ever a GPIO pin is multiplexed with ...
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Revision 5.1 Table 3-7. Two-Signal/Group Multiplexing (Continued) EBGA TEPBGA Signal Ball No. AJ12 N29 GPIO12 AL11 M29 GPIO13 Ball No. A28 AG1 GPIO18 Ball No. J3 C11 IRTX J28 AK8 IRRX1 Ball No. AJ11 M28 GPIO32 AL10 L31 GPIO33 AK10 ...
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Signal Definitions Table 3-8. Three-Signal/Group Multiplexing (Continued) Default EBGA TEPBGA Signal AL15 V31 GPIO16 PMR[ and FPCI_MON = 0 Ball No. GPIO H4 C9 GPIO19 PMR[ and PMR[ Ball No. Parallel Port U3 B18 ...
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Revision 5.1 Table 3-9. Four-Signal/Group Multiplexing Default Signal Configuration Ball No. GPIO AH4 C30 GPIO7 PMR[17 and AJ2 C31 GPIO8 PMR[ AH3 D28 GPIO6 PMR[18 and AG4 C28 GPIO9 PMR[ AJ1 B29 ...
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Signal Definitions 3.4 Signal Descriptions Information in the tables that follow may have duplicate information in multiple tables. Multiple references all contain identi- cal information. 3.4.1 System Interface Ball No. Signal Name EBGA TEPBGA CLKSEL1 B27 AF3 CLKSEL0 F3 B8 ...
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Revision 5.1 3.4.1 System Interface (Continued) Ball No. Signal Name EBGA TEPBGA FPCI_MON D3 A4 DID1 D2 C6 DID0 D4 C5 POR# J29 AH9 X32I C30 AJ2 X32O D29 AJ3 X27I A29 AG3 X27O D27 AH2 CLK27M A23 AA4 PCIRST# ...
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Signal Definitions 3.4.2 Memory Interface Signals Ball No. Signal Name EBGA TEPBGA MD[63:0] See See Table 3-3 Table 3-5 on page on page 38. 54. MA[12:0] See See Table 3-3 Table 3-5 on page on page 38. 54. BA1 P31 ...
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Revision 5.1 3.4.2 Memory Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA SDCLK3 AJ16 V29 SDCLK2 AL20 AA28 SDCLK1 AH16 W29 SDCLK0 AC29 AJ21 SDCLK_IN AJ30 AJ27 SDCLK_OUT AH28 AK28 3.4.3 Video Port Interface Signals Ball No. Signal Name ...
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Signal Definitions 3.4.4 TFT Interface Signals Ball No. Signal Name EBGA TEPBGA HSYNC J1 A11 VSYNC J2 B11 TFTDCK A22 AA1 J4 A10 TFTDE C16 P2 U3 B18 FP_VDD_ON B23 AB1 AL16 V30 TFTD[17:0] See See Table 3-3 Table 3-5 ...
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Revision 5.1 3.4.6 PCI Bus Interface Signals BalL No. Signal Name EBGA TEPBGA PCICLK E2 A7 PCICLK0 D3 A4 PCICLK1 E4 D6 AD[31:24] See See Table 3-3 Table 3-5 AD[23:0] on page on page 38. 54. C/BE3 C/BE2# ...
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Signal Definitions 3.4.6 PCI Bus Interface Signals (Continued) BalL No. Signal Name EBGA TEPBGA PAR C10 J4 FRAME IRDY AMD Geode™ SC3200 Processor Data Book Type Description I/O Parity. Parity generation is required by all PCI ...
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Revision 5.1 3.4.6 PCI Bus Interface Signals (Continued) BalL No. Signal Name EBGA TEPBGA TRDY STOP Type Description I/O Target Ready. TRDY# is asserted to indi- cate that the target agent is able to complete ...
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Signal Definitions 3.4.6 PCI Bus Interface Signals (Continued) BalL No. Signal Name EBGA TEPBGA LOCK DEVSEL PERR AMD Geode™ SC3200 Processor Data Book Type Description I/O Lock Operation. LOCK# indicates an atomic operation that ...
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Revision 5.1 3.4.6 PCI Bus Interface Signals (Continued) BalL No. Signal Name EBGA TEPBGA SERR REQ1 REQ0 GNT1 GNT0 Type Description I/O System Error. SERR# can be asserted by ...
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Signal Definitions 3.4.7 Sub-ISA Interface Signals Ball No. Signal Name EBGA TEPBGA A[23:0] See See Table 3-3 Table 3-5 on page on page 38. 54. D15 See See Table 3-3 Table 3-5 D14 on page on page D13 38. 54. ...
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Revision 5.1 3.4.7 Sub-ISA Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA IRQ9 C22 AA3 IOCHRDY H4 C9 3.4.8 Low Pin Count (LPC) Bus Interface Signals Ball No. Signal Name EBGA TEPBGA LAD3 AJ10 L29 LAD2 AK10 L30 LAD1 ...
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Signal Definitions 3.4.9 IDE Interface Signals Ball No. Signal Name EBGA TEPBGA IDE_RST# A22 AA1 IDE_ADDR2 C17 U2 IDE_ADDR1 C26 AE1 IDE_ADDR0 A26 AD3 IDE_DATA[15:0] See See Table 3-3 Table 3-5 on page on page 38. 54. IDE_IOR0# C21 Y4 ...
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Revision 5.1 3.4.9 IDE Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA IRQ14 D25 AF1 IRQ15 H30 AJ8 3.4.10 Universal Serial Bus (USB) Interface Signals Ball No. Signal Name EBGA TEPBGA POWER_EN B28 AH1 OVER_CUR# C27 AF4 DPOS_PORT1 AH2 ...
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Signal Definitions 3.4.11 Serial Ports (UARTs) Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA RTS2# AH4 C30 CTS2# AJ2 C31 DTR1#/BOUT1 A28 AG1 DTR2#/BOUT2 AH3 D28 RI2# H30 AJ8 DCD2# AG4 C28 DSR2# AJ1 B29 AMD Geode™ SC3200 Processor ...
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Revision 5.1 3.4.12 Parallel Port Interface Signals Ball No. Signal Name EBGA TEPBGA ACK# U3 B18 AFD#/DSTRB# AB2 D22 BUSY/WAIT# T1 B17 ERR# AA3 D21 INIT# Y3 B21 PD7 U1 A18 PD6 V3 A20 PD5 V2 C19 PD4 V1 C18 ...
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Signal Definitions 3.4.12 Parallel Port Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA STB#/WRITE# AB1 A22 3.4.13 Fast Infrared (IR) Port Interface Signals Ball No. Signal Name EBGA TEPBGA IRRX1 J28 AK8 IRRX2/GPIO38 AJ9 K28 IRTX J3 C11 AMD ...
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Revision 5.1 3.4.14 AC97 Audio Interface Signals Ball No. Signal Name EBGA TEPBGA BIT_CLK AL14 U30 SDATA_OUT AK13 P29 SDATA_IN AK14 U31 SDATA_IN2 H31 AL8 SYNC AL13 P30 AC97_CLK AJ14 P31 AC97_RST# AJ15 U29 PC_BEEP AL15 V31 3.4.15 Power Management ...
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Signal Definitions 3.4.15 Power Management Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA PWRBTN# E29 AH5 PWRCNT1 F31 AK6 PWRCNT2 G31 AL7 THRM# F28 AK4 AMD Geode™ SC3200 Processor Data Book Type Description I Power Button. Input used by ...
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Revision 5.1 3.4.16 GPIO Interface Signals Ball No. Signal Name EBGA TEPBGA GPIO0 H1 D11 GPIO1 H2 D10 AL12 N30 GPIO6 AH3 D28 GPIO7 AH4 C30 GPIO8 AJ2 C31 GPIO9 AG4 C28 GPIO10 AJ1 B29 GPIO11 H30 AJ8 GPIO12 AJ12 ...
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Signal Definitions 3.4.17 Debug Monitoring Interface Signals Ball No. Signal Name EBGA TEPBGA FPCICLK U3 B18 F_AD7 U1 A18 F_AD6 V3 A20 F_AD5 V2 C19 F_AD4 V1 C18 F_AD3 W2 C20 F_AD2 W3 D20 F_AD1 Y1 A21 F_AD0 AA1 C21 ...
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Revision 5.1 3.4.18 JTAG Interface Signals Ball No. Signal Name EBGA TEPBGA TCK AL4 E31 TDI AK5 F29 TDO AH6 E30 TMS AJ5 F28 TRST# AK4 E29 3.4.19 Test and Measurement Interface Signals Ball No. Signal Name EBGA TEPBGA GXCLK ...
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Signal Definitions 3.4.19 Test and Measurement Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA SDTEST5 AH3 D28 SDTEST4 AJ2 C31 SDTEST3 AJ4 E28 SDTEST2 AG4 C28 SDTEST1 AJ1 B29 SDTEST0 AH4 C30 TDP AH5 D30 TDN AL3 D31 AMD ...
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Revision 5.1 3.4.20 Power, Ground and No Connections Ball No. Signal Name EBGA AV R3 SSPLL2 AV E28 SSPLL3 V R1 PLL2 V C31 PLL3 AV AF4 CCUSB AV AG1 SSUSB V D30 BAT V F29 SB V H28 SBL ...
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General Configuration Block The General Configuration block includes registers for: • Pin Multiplexing and Miscellaneous Configuration • WATCHDOG Timer • High-Resolution Timer • Clock Generators A selectable interrupt is shared by all these functions. 4.1 Configuration Block Addresses Registers of ...
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Revision 5.1 4.2 Multiplexing, Interrupt Selection, and Base Address Registers The registers described inTable 4-2 are used to determine general configuration for the SC3200. These registers also indicate which multiplexed signals are issued via balls from which more than one ...
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General Configuration Block Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 26 Reserved. Always write 0. 25 AC97CKEN (Enable AC97_CLK Output). This bit enables the output drive of AC97_CLK (EBGA ball AJ14 / TEPBGA ball P31). ...
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Revision 5.1 Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 23 TFTPP (TFT/Parallel Port). Determines whether certain balls are used for TFT or PP/ACB1/FPCI. This bit is set power-on if the TFT_PRSNT strap ...
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General Configuration Block Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 21 IOCSEL (Select I/O Commands). Selects ball functions. Ball # 0: I/O Command Signals EBGA / TEPBGA Name IOR# DOCR ...
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Revision 5.1 Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 12 TRDESEL (Select TRDE#). Selects ball function. Ball # 0: Sub-ISA Signal EBGA / TEPBGA Name H1 / D11 TRDE# 11 EIDE (Enable IDE Outputs). This ...
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General Configuration Block Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 16 Delay HSYNC. HSYNC delay by two TFT clock cycles. 0: There is no delay on HSYNC. 1: HYSNC is delayed twice by rising edge ...
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Revision 5.1 Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 0 SDBE0 (Slave Disconnect Boundary Enable). Works in conjunction with the GX1 module’s PCI Control Function 2 Regis- ter (Index 41h), bit 1 (SDBE1). Sets boundaries ...
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General Configuration Block 4.3 WATCHDOG The SC3200 includes a WATCHDOG function to serve as a fail-safe mechanism in case the system becomes hung. When triggered, the WATCHDOG mechanism returns the system to a known state by generating an interrupt, an ...
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Revision 5.1 WATCHDOG Interrupt The WATCHDOG interrupt (if configured and enabled) is routed to an IRQ signal. The IRQ signal is programmable via the INTSEL register (Offset 38h, described in Table 4-2 "Multiplexing, Interrupt Selection, and Base Address Regis- ters" ...
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General Configuration Block Table 4-3. WATCHDOG Registers (Continued) Bit Description Offset 04h This register contains WATCHDOG status information. 7:4 Reserved. Write as read. 3 WDRST (WATCHDOG Reset Asserted). (Read Only) This bit is set to 1 when WATCHDOG Reset is ...
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Revision 5.1 Table 4-4. High-Resolution Timer Registers Bit Description Offset 08h-0Bh This register contains the current value of the High-Resolution Timer. 31:0 Current Timer Value. Offset 0Ch This register supplies the High-Resolution Timer status information. 7:1 Reserved. 0 TMSTS (TIMER ...
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General Configuration Block 4.5 Clock Generators and PLLs This section describes the registers for the clocks required by the GX1 module, Core Logic module, and the Video Processor, and how these clocks are generated. See Fig- ure 4-2 for a ...
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Revision 5.1 4.5.1 27 MHz Crystal Oscillator The internal oscillator employs an external crystal con- nected to the on-chip amplifier. The on-chip amplifier is accessible on the X27I input and X27O output signals. See Figure 4-3 for the recommended external ...
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General Configuration Block 4.5.2 GX1 Module Core Clock The core clock is generated by an Analog Delay Loop (ADL) clock generator from the internal Fast-PCI clock. The clock can be any whole-number multiple of the input clock between 4 and ...
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Revision 5.1 4.5.4 SuperI/O Clocks The SuperI/O module requires a 48 MHz input for Fast infrared (FIR), UART, and other functions. This clock is sup- plied by PLL4 using a multiplier value of 576/(108x3) to generate 48 MHz. 4.5.5 Core ...
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General Configuration Block 4.5.7 Clock Registers Table 4-8 describes the registers of the clock generator and PLL. Table 4-8. Clock Generator Configuration Bit Description Offset 10h Maximum Core Clock Multiplier Register - MCCM (RO) This register holds the maximum core ...
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Revision 5.1 Table 4-8. Clock Generator Configuration (Continued) Bit Description Offset 1Eh-1Fh Core Clock Frequency Control Register - CCFC (R/W) This register controls the configuration of the core clock multiplier and the reference clocks. 15:14 Reserved. 13 Reserved. Must be ...
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SuperI/O Module The SuperI/O (SIO) module is a PC98 and ACPI compliant SIO that offers a single-cell solution to the most commonly used ISA peripherals. The SIO module incorporates: two Serial Ports, an Infrared Communication Port that supports FIR, MIR, ...
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Revision 5.1 5.1 Features PC98 and ACPI Compliant • PnP Configuration Register structure • Flexible resource allocation for all logical devices: — Relocatable base address — 9 Parallel IRQ routing options — 3 optional 8-bit DMA channels (where applicable) Parallel ...
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SuperI/O Module 5.2 Module Architecture The SIO module comprises a collection of generic func- tional blocks. Each functional block is described in detail later in this chapter. The beginning of this chapter describes the SIO structure and provides all device ...
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Revision 5.1 5.3 Configuration Structure / Access This section describes the structure of the configuration register file, and the method of accessing the configuration registers. 5.3.1 Index-Data Register Pair The SIO configuration access is performed via an Index- Data register ...
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SuperI/O Module Write accesses to unimplemented registers (i.e., accessing the Data register while the Index register points to a non- existing register or the LDN is 07h or higher than 08h), are ignored and a read returns 00h on all ...
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Revision 5.1 5.4 Standard Configuration Registers As illustrated in Figure 5-4, the Standard Configuration reg- isters are broadly divided into two categories: SIO Control and Configuration registers and Logical Device Control and Configuration registers (one per logical device, some are ...
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SuperI/O Module Table 5-3 provides the bit definitions for the Standard Con- figuration registers. • All reserved bits return 0 on reads, except where noted otherwise. They must not be modified as such modifica- tion may cause unpredictable results. Use ...
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Revision 5.1 Table 5-3. Standard Configuration Registers (Continued) Bit Description Index 75h Indicates selected DMA channel for DMA 1 of the logical device (1 - the second DMA channel in case of using more than one DMA channel). 7:3 Reserved. ...
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SuperI/O Module 5.4.1 SIO Control and Configuration Registers Table 5-4 lists the SIO Control and Configuration registers and Table 5-5 provides their bit formats. Table 5-4. SIO Control and Configuration Register Map Index Type Name 20h RO SID. SIO ID ...
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Revision 5.1 5.4.2 Logical Device Control and Configuration As described in Section 5.3.2 "Banked Logical Device Reg- isters" on page 108, each functional block is associated with a Logical Device Number (LDN). This section provides the register descriptions for each ...
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SuperI/O Module Bit Description Index F0h When any non-reserved bit in this register is set can be cleared only by hardware reset. 7 Block Standard RAM effect on Standard RAM access. (Default) 1: Read and ...
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Revision 5.1 5.4.2.2 LDN 01h - System Wakeup Control Table 5-8 lists registers that are relevant to the configura- tion of System Wakeup Control (SWC). These registers are Index Type Configuration Register or Action 30h R/W Activate. When bit 0 ...
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SuperI/O Module 5.4.2.3 LDN 02h - Infrared Communication Port or Serial Port 3 Table 5-9 lists the configuration registers which affect the Infrared Communication Port or Serial Port 3 (IRCP/SP3). Index Type Configuration Register or Action 30h R/W Activate. See ...
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Revision 5.1 5.4.2.4 LDN 03h and 08h - Serial Ports 1 and 2 Serial Ports 1 and 2 are identical, except for their reset val- ues. Serial Port 1 is designated as LDN 03h and Serial Port 2 as LDN ...
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SuperI/O Module 5.4.2.5 LDN 05h and 06h - ACCESS.bus Ports 1 and 2 ACCESS.bus ports 1 and 2 (ACB1 and ACB2) are identi- cal. Each ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer. ACB1 and ...
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Revision 5.1 5.4.2.6 LDN 07h - Parallel Port The Parallel Port supports all IEEE 1284 standard commu- nication modes: Compatibility (known also as Standard or SPP), Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP ...
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SuperI/O Module 5.5 Real-Time Clock (RTC) The RTC provides timekeeping and calendar management capabilities. The RTC uses a 32.768 KHz signal as the basic clock for timekeeping. It also includes 242 bytes of battery-backed RAM for general-purpose use. The RTC ...
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Revision 5.1 External Elements Choose C and C capacitors (see Figure 5-5 on page 1 2 121) to match the crystal’s load capacitance. The load capacitance C “seen” by crystal Y is comprised series with C and ...
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SuperI/O Module 5.5.2.4 Timekeeping Data Format Time is kept in BCD or binary format, as determined by bit 2 (DM) of Control Register B (CRB), and in either 12 or 24- hour format, as determined by bit 1 of this ...
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Revision 5.1 5.5.2.6 Power Supply The device is supplied from two supply voltages, as shown in Figure 5-8: • System standby power supply voltage, V • Backup voltage, from low capacity Lithium battery A standby voltage from the ...
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SuperI/O Module 5.5.2.7 System Power States The system power state may be No Power, Power On, Power Off or Power Failure. Table 5-18 indicates the power-source combinations for each state. No other power-source combinations are valid. In addition, the power ...
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Revision 5.1 5.5.2.9 Interrupt Handling The RTC has a single Interrupt Request line which handles the following three interrupt conditions: • Periodic interrupt. • Alarm interrupt. • Update end interrupt. The interrupts are generated if the respective enable bits in ...
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SuperI/O Module 5.5.3 RTC Registers The RTC registers can be accessed (see Section 5.4.2.1 "LDN 00h - Real-Time Clock" on page 114) at any time dur- ing normal operation mode (i.e.,when V ommended operation range). This access is disabled during ...
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Revision 5.1 Bit Description Index 03h 7:0 Minutes Alarm Data. Values can BCD format binary format. When bits 7 and 6 are both set to 1, unconditional match is selected. ...
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SuperI/O Module Bit Description 3 Reserved. This bit is defined as “Square Wave Enable” by the MC146818 and is not supported by the RTC. This bit is always read Data Mode. This bit is reset at V ...
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Revision 5.1 Table 5-21. Divider Chain Control / Test Selection DV2 DV1 DV0 CRA6 CRA5 CRA4 Configuration Oscillator Disabled Normal Operation Test Divider Chain Reset ...
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SuperI/O Module 5.5.3.1 Usage Hints 1) Read bit 7 of CRD at each system power-up to vali- date the contents of the RTC registers and the CMOS RAM. When this bit is 0, the contents of these regis- ters and ...
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Revision 5.1 5.6 System Wakeup Control (SWC) The SWC wakes up the system by sending a power-up request to the ACPI controller in response to the following maskable system events: • Modem ring (RI2#) • Audio Codec event (SDATA_IN2) • ...
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SuperI/O Module 5.6.2 SWC Registers The SWC registers are organized in two banks. The offsets are related to a base address that is determined by the SWC Base Address Register in the logical device configu- ration. The lower three registers ...
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Revision 5.1 Table 5-29. Banks 0 and 1 - Common Control and Status Registers Bit Description Offset 00h Wakeup Events Status Register - WKSR (R/W1C) This register is set to 00h on power- 6.2.9.4 "Power Management Events" on ...
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SuperI/O Module Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers Bit Description Bank 1, Offset 03h This register is set to 00h on power- 7:6 Reserved. 5:4 CEIR Protocol Select. 00: RC5 01: NEC/RCA 1x: ...
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Revision 5.1 Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers (Continued) Bit Description These two registers (IRWTR1L and IRWTR1H) define the low and high limits of time range 1 (see Table 5-26 on page 132). The values ...
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SuperI/O Module 5.7 ACCESS.bus Interface The SC3200 has two ACCESS.bus (ACB) controllers. ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer, Intel's SMBus, and Philips’ C™. The ACB can be configured as a bus ...
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Revision 5.1 5.7.3 Acknowledge (ACK) Cycle The ACK cycle consists of two signals: the ACK clock pulse sent by the master with each byte transferred, and the ACK signal sent by the receiving device (see Figure 5-15). The master generates ...
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SuperI/O Module 5.7.4 Acknowledge After Every Byte Rule According to this rule, the master generates an acknowl- edge clock pulse after each byte transfer, and the receiver sends an acknowledge signal after every byte received. There are two exceptions to ...
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Revision 5.1 Sending the Address Byte When the device is the active master of the ACCESS.bus (ACBST[1] is set), it can send the address on the bus. The address sent should not be the device’s own address, as defined by ...
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SuperI/O Module Master Error Detection The ACB detects illegal Start or Stop Conditions (i.e., a Start or Stop Condition within the data transfer, or the acknowledge cycle) and a conflict on the data lines of the ACCESS.bus illegal ...
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Revision 5.1 5.7.10 ACB Registers Each functional block is associated with a Logical Device Number (LDN) (see Section 5.3.2 "Banked Logical Device Registers" on page 108). ACCESS.Bus Port 1 is assigned Offset Type 00h R/W 01h R/W 02h R/W 03h ...
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SuperI/O Module Bit Description 2 NMATCH (New Match). (R/W1C) Writing 0 to this bit is ignored. If ACBCTL1[2] is set, an interrupt is sent when this bit is set. 0: Software writes 1 to this bit. 1: Address byte follows ...
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Revision 5.1 Bit Description 4 ACK (Acknowledge). This bit is ignored in transmit mode. When the device acts as a receiver (slave or master), this bit holds the stop transmitting instruction that is transmitted during the next acknowledge cycle. 0: ...
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SuperI/O Module 5.8 Legacy Functional Blocks This section briefly describes the following blocks that pro- vide legacy device functions: • Parallel Port. (Similar to Parallel Port in the National Semiconductor PC87338.) • Serial Port 1 and Serial Port 2 (SP1 ...
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Revision 5.1 Table 5-35. Parallel Port Bit Map for First Level Offset Offset Name 7 000h DATAR AFIFO 001h DSR Printer Status 002h DCR RSVD 003h ADDR 004h DATA0 005h DATA1 006h DATA2 007h DATA3 400h CFIFO 400h DFIFO 400h ...
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SuperI/O Module 5.8.2 UART Functionality (SP1 and SP2) Both SP1 and SP2 provide UART functionality. The generic SP1 and SP2 support serial data communication with remote peripheral device or modem using a wired inter- face. The functional blocks can function ...
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Revision 5 Offset Type 00h R/W 01h R/W 02h --- 03h W R/W 04h-07h --- 1. When bit 7 ...
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SuperI/O Module Register Offset Name 7 00h RXD TXD 01h 1 IER 2 RSVD IER 02h 1 FEN[1:0] EIR 2 RSVD EIR FCR RXFTH[1:0] 03h 5 BKSE LCR 5 BKSE BSR 04h 1 MCR 2 MCR 05h LSR ER_INF 06h ...
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Revision 5.1 Register Offset Name 7 00h BGD(L) 01h BGD(H) 02h EXCR1 BTEST 03h BSR BKSE 04h EXCR2 LOCK 05h RSVD 06h RXFLV 07h TXFLV Register Offset Name 7 00h MRID 01h SH_LCR BKSE 02h SH_FCR RXFTH[1:0] 03h BSR BKSE ...
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SuperI/O Module 5.8.3 IR Communications Port (IRCP) / Serial Port 3 (SP3) Functionality This section describes the IRCP/SP3 support registers. The IRCP/SP3 functional block provides advanced, versa- tile serial communications features with IR capabilities. The IRCP/SP3 also supports two DMA ...
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Revision 5.1 BSR Bits ...
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SuperI/O Module Offset Type 00h RO 01h RO 02h RO 03h R/W 04h-07h --- Offset Type 00h RO 01h RO 02h R/W 03h R/W 04h R/W RO 05h R/W RO 06h R/W RO 07h R/W RO Offset Type 00h R/W ...
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Revision 5.1 Offset Type 00h R/W 01h R/W 02h R/W 03h R/W 04h R/W 05h-07h --- Offset Type 00h R/W 01h R/W 02h R/W 03h R/W 04h R/W 05h-06h --- 07h R/W Register Offset Name 7 00h RXD TXD 01h ...
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SuperI/O Module Register Offset Name 7 00h LBGD(L) 01h LBGD(H) 02h RSVD 03h LCR BKSE BSR BKSE 04h-07h RSVD Register Offset Name 7 00h BGD(L) 01h BGD(H) 02h EXCR1 BTEST 03h BSR BKSE 04h EXCR2 LOCK 05h RSVD 06h TXFLV ...
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Revision 5.1 Register Offset Name 7 06h RFRML(L)/ RFRCC(L) 07h RFRML(H)/ RFRCC(H) Register Offset Name 7 00h SPR2 01h SPR3 02h RSVD 03h BSR BKSE 04h IRCR2 RSVD 05h FRM_ST VLD LOST_FR 06h RFRL(L)/ LSTFRC 07h RFRL(H) Register Offset Name ...
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Core Logic Module The Core Logic module is an enhanced PCI-to-Sub-ISA bridge (South Bridge), this module is ACPI-compliant, and provides AT/Sub-ISA functionality. The Core Logic module also contains state-of-the-art power management. Two bus mastering IDE controllers are included for support ...
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Revision 5.1 Integrated Audio • AC97 Version 2.0 compliant interface to audio codecs • Secondary codec support • AMC97 codec support Video Processor Interface • Synchronous serial interface to the Video Processor • Translates video and clock control register accesses ...
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Core Logic Module 6.2.1 Fast-PCI Interface to External PCI Bus The Core Logic module provides a PCI bus interface that is both a slave for PCI cycles initiated by the GX1 module or other PCI master devices, and a non-preemptive ...
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Revision 5.1 6.2.2.1 Video Retrace Interrupt Bit 7 of the “Serial Packet” can be used to generate an SMI whenever a video retrace occurs within the GX1 module. This function is normally not used for power management but for SoftVGA ...
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Core Logic Module For example channel had one Mode 4 device and one Mode 0 device, then the Mode 4 device would have com- mand timings for Mode 0 and data timing for Mode 4. The Mode 0 ...
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Revision 5.1 6.2.3.4 UltraDMA/33 Mode The IDE controller of the Core Logic module supports UltraDMA/33. It utilizes the standard IDE Bus Master func- tionality to interface, initiate and control the transfer. UltraDMA/33 definition also incorporates a Cyclic Redun- dancy Checking ...
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Core Logic Module 6.2.4 Universal Serial Bus The Core Logic module provides three complete, indepen- dent USB ports. Each port has a Data "Negative" and a Data "Positive" signal. The USB ports are Open Host Controller Interface (Open- HCI) compliant. ...
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Revision 5.1 6.2.5.1 Sub-ISA Bus Cycles The ISA bus controller issues multiple ISA cycles to satisfy PCI transactions that are larger than 16 bits. A full 32-bit read or write results in two 16-bit ISA transactions or four 8- bit ...
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Core Logic Module REQ# GNT# FRAME# Fast-PCI 1 IRDY# TRDY# STOP# BALE ISA RD#, IOR GX1 transaction 2 - IDE bus master - starts and completes 3 - End of ISA cycle Figure 6-3. PCI to ISA Cycles ...
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Revision 5.1 6.2.5.5 ISA DMA DMA transfers occur between ISA I/O peripherals and sys- tem memory (i.e., not available externally). The data width can be either bits. Out of the seven DMA channels available, four are used ...
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Core Logic Module 6.2.5.6 ROM Interface The Core Logic module positively decodes memory addresses 000F0000h-000FFFFFh FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory cycles cause the Core Logic module to claim the cycle, and generate an ISA bus memory cycle with ...
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Revision 5.1 PCI FRAME# TRDY#, IRDY# GNT[x] ROMCS#, DOCCS#, IOCS0#, IOCS1# PAR, DEVSEL#,STOP# AD[31:0], C/BE[3:0]# Figure 6-6. PCI Change to Sub-ISA and Back 6.2.6 AT Compatibility Logic The Core Logic module integrates: • Two 8237-equivalent DMA controllers with full 32-bit ...
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Core Logic Module DMA Transfer Modes Each DMA channel can be programmed for single, block, demand or cascade transfer modes. In the most commonly used mode, single transfer mode, one DMA cycle occurs per DRQ and the PCI bus is ...
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Revision 5.1 DMA Addressing Capability DMA transfers occur over the entire 32-bit address range of the PCI bus. This is accomplished by using the DMA con- troller’s 16-bit memory address registers in conjunction with an 8-bit DMA Low Page register ...
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Core Logic Module 6.2.6.3 Programmable Interrupt Controller The Core Logic module contains two 8259A-equivalent programmable interrupt controllers, with eight interrupt request lines each, for a total of 16 interrupts. The PCI device supports all x86 modes of operation except Special ...
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Revision 5.1 PIC Interrupt Sequence A typical AT-compatible interrupt sequence is as follows. Any unmasked interrupt generates the internal INTR signal to the CPU. The interrupt controller then responds to the interrupt acknowledge (INTA) cycles from the CPU. On the ...
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Core Logic Module 6.2.7.1 I/O Port 092h System Control I/O Port 092h allows for a fast keyboard assertion of an A20# SMI and a fast keyboard CPU reset. Decoding for this register may be disabled via F0 Index 52h[3]. The ...
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Revision 5.1 6.2.9 Power Management Logic The Core Logic module integrates advanced power man- agement features including idle timers for common system peripherals, address trap registers for programmable address ranges for I/O or memory accesses, four program- mable general purpose ...
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Core Logic Module 6.2.9.2 Sleep States The SC3200 supports four Sleep states (SL1-SL3) and the Soft Off state (G2/S5). These states are fully compliant with the ACPI specification, revision 1.0. When the SLP_EN bit (F1BAR1+I/O Offset 0Ch[13]) is set to ...
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Revision 5.1 6.2.9.3 Power Planes Control The SC3200 supports up to three power planes. Three sig- nals are used to control these power planes. Table 6-6 describes the signals and when each is asserted. Table 6-6. Power Planes Control Signals ...
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Core Logic Module Power Button The power button (PWRBTN#) input provides two events: a wake request, and a sleep request. For both these events, the PWRBTN# signal is debounced (i.e., the signal state is transferred only after ...
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Revision 5.1 6.2.10 Power Management Programming The power management resources provided by a com- bined GX1 module and Core Logic module based system supports a high efficiency power management implementa- tion. The following explanations pertain to a full-featured “notebook” power ...
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Core Logic Module The automatic speedup events (video and IRQ) for Sus- pend Modulation should be used together with software- controlled speedup registers for major I/O events such as any access to the FDC, HDD, or parallel/serial ports, since these ...
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Revision 5.1 6.2.10.3 Peripheral Power Management The Core Logic module provides peripheral power man- agement using a combination of device idle timers, address traps, and general purpose I/O pins. Idle timers are used in conjunction with traps to support powering ...
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Core Logic Module Power Management SMI Status Reporting Registers The Core Logic module updates status registers to reflect the SMI sources. Power management SMI sources are the device idle timers, address traps, and general purpose I/O pins. Power management events ...
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Revision 5.1 6.2.10.4 Power Management Programming Summary Table 6-9 provides a programming register summary for the power management timers, traps, and functions. For Table 6-9. Device Power Management Programming Summary Device Power Management Resource Enable Global Timer Enable 80h[0] Keyboard ...
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Core Logic Module 6.2.11 GPIO Interface GPIOs in the in the Core Logic module are pro- vided for system control. For further information, see Sec- tion 4.2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 88 ...
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Revision 5.1 Physical Region Descriptor Table Address Before the bus master starts a master transfer it must be pro- grammed with a pointer (PRD Table Address register Physical Region Descriptor Table. This pointer sets the start- ing memory ...
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Core Logic Module 4) Read the SMI Status register to clear the Bus Master Error and End of Page bits (bits 1 and 0). Set the correct direction to the Read or Write Control bit (Command register bit 3). Note ...
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Revision 5.1 6.2.12.2 AC97 Codec Interface The AC97 codec (e.g., LM4548) is the master of the serial interface and generates the clocks to Core Logic module. Figure 6-13 shows the signal connections between two codecs and the SC3200: • Codec1 ...
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Core Logic Module 6.2.12.3 VSA Technology Support Hardware The Core Logic module incorporates the required hard- ware in order to support the Virtual System Architecture (VSA) technology for capture and playback of audio using an external codec. This eliminates much ...
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Revision 5.1 In Fast Path Write, the Core Logic module responds to writes to the following addresses: 388h, 38Ah, 38Bh, 2x0h, 2x2h, and 2x8h. SMI# Asserted If Bit (External SMI) GX1 Module Core Logic Module F1BAR0+Memory Offset ...
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Core Logic Module 6.2.12.4 IRQ Configuration Registers The Core Logic module provides the ability to set and clear IRQs internally through software control. If the IRQs are configured for software control, they do not respond to external hardware. There are ...
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Revision 5.1 6.2.12.6 LPC Interface Signal Definitions The LPC specification lists seven required and six optional signals for supporting the LPC interface. Many of the sig- nals are the same signals found on the PCI interface and do not require ...
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Core Logic Module - PCI Configuration Space and Access Methods 6.3 Register Descriptions The Core Logic module is a multi-function module. Its reg- ister space can be broadly divided into three categories in which specific types of registers are located: ...
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Revision 5.1 6.3.2 Register Summary The tables in this subsection summarize the registers of the Core Logic module. Included in the tables are the regis- ter’s reset values and page references where the bit for- mats are found. Table 6-14. ...
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Core Logic Module - Register Summary Table 6-14. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support Summary (Continued) Width F0 Index (Bits) Type Name 6Ch-6Fh 32 R/W ROM Mask Register 70h-71h 16 R/W IOCS1# Base Address Register 72h ...
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Revision 5.1 Table 6-14. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support Summary (Continued) Width F0 Index (Bits) Type Name B8h 8 RO DMA Shadow Register B9h 8 RO PIC Shadow Register BAh 8 RO PIT Shadow Register ...
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Core Logic Module - Register Summary Table 6-15. F0BAR0: GPIO Support Registers Summary F0BAR0+ Width I/O Offset (Bits) Type Name 00h-03h 32 R/W GPDO0 — GPIO Data Out 0 Register 04h-07h 32 RO GPDI0 — GPIO Data In 0 Register ...
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Revision 5.1 Table 6-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary Width F1 Index (Bits) Type Name 00h-01h 16 RO Vendor Identification Register 02h-03h 16 RO Device Identification Register 04h-05h 16 R/W PCI Command Register 06h-07h ...
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Core Logic Module - Register Summary Table 6-19. F1BAR1: ACPI Support Registers Summary F1BAR1+ Width I/O Offset (Bits) Type Name 00h-03h 32 R/W P_CNT — Processor Control Register 04h 8 RO Reserved, do not read 05h 8 RO P_LVL3 — ...
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Revision 5.1 Table 6-20. F2: PCI Header Registers for IDE Controller Support Summary Width F2 Index (Bits) Type Name 00h-01h 16 RO Vendor Identification Register 02h-03h 16 RO Device Identification Register 04h-05h 16 R/W PCI Command Register 06h-07h 16 RO ...
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Core Logic Module - Register Summary Table 6-21. F2BAR4: IDE Controller Support Registers Summary F2BAR4+ Width I/O Offset (Bits) Type 00h 8 R/W IDE Bus Master 0 Command Register — Primary 01h --- --- Not Used 02h 8 R/W IDE ...
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Revision 5.1 Table 6-23. F3BAR0: Audio Support Registers Summary F3BAR0+ Memory Width Offset (Bits) Type Name 00h-03h 32 R/W Codec GPIO Status Register 04h-07h 32 R/W Codec GPIO Control Register 08h-0Bh 32 R/W Codec Status Register 0Ch-0Fh 32 R/W Codec ...