CXA3256R Sony, CXA3256R Datasheet
CXA3256R
Related parts for CXA3256R
CXA3256R Summary of contents
Page 1
... ECL, PECL or TTL can be selected as the digital input level in accordance with the application. The TTL digital output level allows 1: 2 demultiplexed output. The CXA3256R is easier to be used by adding the new functions to the CXA3246Q and adopting a ultra-small package. Features • ...
Page 2
... 1 2 DGND1 IL DGND1 + 2.4 /E – N/E|) 0.4 0.8 100 120 –20 VID – 2 – CXA3256R Unit °C W 50mm, 1.6mm thick) With dual power supply Unit Max. Min. ...
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... DGND1 or Open or DVcc1 DGND1 or Open or DVcc1 Clamp voltage TTL +5V 0V TTL 0V +5V +5V 0V TTL 0V +5V TTL TTL TTL TTL PECL PECL – 3 – CXA3256R Typical voltage level with dual power supply –5.0V 1.4 to 2.6V 0V — + — +5V — 0V 2.9 to 4.1V 0V ECL ECL ...
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... AGND INV 6bit 8bit 6bit 6bit 8bit 6bit D Q Select SELECT1 DGND1 DGND2 – 4 – CXA3256R DGND3 12 (MSB) PBD7 40 PBD6 39 PBD5 38 PBD4 37 PBD3 36 PBD2 35 PBD1 34 PBD0 33 (LSB) (MSB) PAD7 28 PAD6 27 PAD5 26 PAD4 25 PAD3 ...
Page 5
... PA side high impedance. TTL output high level clamp The TTL high level voltage is clamped to the approximately same 3k value as the voltage applied to this pin. 17 Even if this pin is left open, the TTL high level is clamped to 3.5k approximately 2.8V. DGND2 – 5 – CXA3256R Description ...
Page 6
... DGND1 – 6 – CXA3256R Description Power saving. When left open, this pin goes to high level. When set to low level, the power saving state is established. Clock input. CLK/E complementary input. When left open, this pin goes to the threshold voltage. ...
Page 7
... DGND2 D 3 VEE DGND1 – 7 – CXA3256R Description Top reference voltage. By-pass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. Reference voltage mid point. By-pass to AGND with a 0.1µF chip capacitor. Reference voltage mid point. By-pass to AGND with a 0.1µF chip capacitor ...
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... DMUX mode CLK CLK RESETN – CLK RESETN – CLK (C = 5pF) L DMUX mode (C = 5pF 5pF) L 0 5pF) L 0 5pF) L – 8 – CXA3256R 25° Min. Typ. Max. Unit 8 bits ±0.5 LSB ±0.5 LSB 100 285 µ ...
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... Error > 16LSB Fc = 120MSPS, { fin = 29.999MHz Fs DMUX mode Error > 16LSB Fc = 100MSPS, { fin = 24.999MHz Fs Straight mode Error > 16LSB and – 9 – CXA3256R Min. Typ. Max. Unit MHz 250 –12 TPS 10 –9 TPS 10 –9 TPS 98 140 mA ...
Page 10
... Table 1. I/O Correspondence Table INV – 10 – CXA3256R ...
Page 11
... Taj is: Taj = / 8 Latch CLK + Latch 16LSB 1/8 – 11 – CXA3256R Amp Logic CXA3256R Analizer CLK 1024 samples ECL Buffer 129 128 t (LSB) ...
Page 12
... When using the multiple CXA3256R in DMUX mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example on the next page countermeasure, the CXA3256R has a function that resets the 1/2 frequency-divided clocks ...
Page 13
... PECL 0V TTL 0V Table 3. Logic Input Level and Power Supply Settings Description of SELECT2 pin The CXA3256R has the two systems of data output. The SELECT2 pin is used to select the port where the data is output. SELECT2 pin Open Output possible to both PA and PB Vcc1 Output possible to PA, and PB output is high impedance. ...
Page 14
... PAD0 to PAD7 8 bit Digital Data +5V(D) – 14 – CXA3256R 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch ...
Page 15
... Digital Data PECL TTL DG DG +5V(D) +5V( PAD0 to PAD7 8 bit Digital Data 25 DG +5V(D) +5V(D) – 15 – CXA3256R 8 bit Digital Data Latch 8 bit Digital Data Latch 8 bit Digital Data Latch ...
Page 16
... A/D converter. See the Notes on Operation. is the chip capacitor of 0.1µF. Also important to suppress the noise generated during the TTL output circuit is operating. Place C at the fixed position between the pins with the shortest distance. – 16 – CXA3256R ...
Page 17
... CLK OUT (Pin 43) T_rh T_rs T_rh RESETN (Pin 48 Td_clk; 4.5ns (typ.) 7.0ns (max) 3.0ns (min) 2.0V 2.0V (Reset period) 0.8V 0.8V T_rs – 17 – CXA3256R Tdo2; 5.0ns (typ.) 3.5ns (min) 7.5ns (max) 2. 0.8V 2. 0.8V Tdo1 0.5ns (typ.) 2.0V 0.8V ...
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... PAD0 to D7 2.0V N – 4 (Pins 21 to 28) 0.8V PBD0 to D7 2.0V N – 3 (Pins 33 to 40) 0.8V Td_clk; 4.5ns (typ.) 3.0ns (min) 7.0ns (max) CLK OUT 2.0V (CLK is inverted and output.) 0.8V (Pin 43 – – – – 1 – 18 – CXA3256R – ...
Page 19
... Notes on Operation • The CXA3256R has the PECL and TTL input pins for the clock and reset input pins. When the clock is input in PECL level, inputting the reset signal in PECL level is recommended. Also, when the clock is input in TTL level, inputting the reset signal in TTL is recommended. ...
Page 20
... VOCLP pin and the TTL high level. • The CXA3026Q has the output pins and this time, the P1 side of the CXA3026Q is changed to the PB side for the CXA3256R; the P2 side of the CXA3026Q to the PA side for the CXA3256R. • The pipeline delay of the CXA3256R is smaller by one clock, compared to that of CXA3026Q. ...
Page 21
... Analog input voltage [V] Current consumption vs. Conversion rate characteristics 110 105 100 – Conversion rate [MSPS] Reference current vs. Ambient temperature characteristics –25 Ta – Ambient temperature [°C] – 21 – CXA3256R f CLK fin = – 1kHz 4 DMUX mode C = 5pF L 60 120 25 75 ...
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... Error rate vs. Conversion rate characteristics – CLK fin = – 1kHz 4 –7 10 Error > 16LSB –8 10 –9 10 – 120 Fc – Conversion rate [MSPS] TTL output high level vs. VOCLP pin 0.5 1 VOCLP pin voltage [V] – 22 – CXA3256R 140 160 TTL high level when VOCLP is open ...
Page 23
... This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). 48PIN LQFP (PLASTIC (0.22 0.2 1.5 – 0.1 0.13 M 0.1 ± 0.1 NOTE: Dimension “ ” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS – 23 – CXA3256R + 0.05 0.127 – 0.02 0.1 S EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g ...