CXD3021R Sony, CXD3021R Datasheet
CXD3021R
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CXD3021R Summary of contents
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... CD Digital Signal Processor with Built-in Digital Servo and DAC For the availability of this product, please contact the sales office. Description The CXD3021R is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter and 1-bit DAC. Features • All digital signal processing during playback is performed with a single chip • ...
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... The Maximum Operating Speed graph shows the playback speed V The playback conditions are that the high-speed VCO1 selects No.4 and VCO2 selects high speed in CAV-W mode with DSPB = 1. 3.2 3.3 3.4 3.5 3.6 3.7 [V] (min.) at various temperatures. DD – 2 – CXD3021R +25°C +55°C +75°C 3.8 3.9 4.0 ...
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... Interface MIRR DFCT FOK SERVO DSP FOCUS SERVO TRACKING SERVO SLED SERVO 102 11 116 – 3 – CXD3021R : Asymmetry Correction DAC Block 74 PWMLP 75 PWMLN 8Fs Digital Filter + 67 PWMRP 1 bit DAC 66 PWMRN 20 PSSL 24 DA16 (48PCM) 26 DA15 (48BCK) ...
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... TE 120 – 4 – CXD3021R XRST 59 SCSY 58 SQCK 57 SQSO 56 EXCK 55 SBSO 54 SCOR WFCK 53 MUTE 52 51 ...
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... DA12 output when PSSL = 1, 32-bit/64-bit slot LR clock output when PSSL = 0. 31 DA11 output when PSSL = 1, GTOP output when PSSL = 0. DA11 DA10 output when PSSL = 1, XUGF output when PSSL = 0. DA10 DA09 output when PSSL = 1, XPLCK output when PSSL = 0. DA09 Description , high = – 5 – CXD3021R ...
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... Audio DAC left channel zero detection flag Digital GND Analog GND PWMRN Audio DAC PWM output. Right channel, reversed phase. PWMRP Audio DAC PWM output. Right channel, forward phase. Description – 6 – CXD3021R ...
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... MDS Spindle motor servo control output. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. 100 LOCK I/O If GFS is low eight consecutive samples, this pin outputs low. Input when 1, 0 LKIN = high. (See $3E.) Description – 7 – CXD3021R ...
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... The GFS signal goes high when the frame sync and the insertion protection timing match. (See $348.) • RFCK is derived from the crystal accuracy, and has a cycle of 136µs. (during normal speed) • C2PO represents the data error status. • XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin. Description – 8 – CXD3021R ...
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... ( 0.36mA ( 5.5V – 0.25V (2) – 0.75V 3.6V – – 9 – CXD3021R Applicable Typ. Max. Unit pins ...
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... V Item Symbol Min. Input amplitude V 2 3.3V ± 10 Typ. Max. Unit 34 MHz = AV = 3.3V ± 10 Typ. Max. Unit 500 ns ns 500 1000 WLX V IHX V 0.9 IHX 0.1 IHX V ILX = AV = 3.3V ± 10 Typ. Max. Unit + 0.3 Vp – 10 – CXD3021R ...
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... WCK CLOK DATA XLAT EXCK SQCK CNIN t WT 1/f T SBSO SQSO 0V, Topr = –20 to +75° Min. Typ. Max. Unit 16 MHz 750 ns 0.65 MHz ns 750 65 kHz 7.5 µs t WCK – 11 – CXD3021R ...
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... When settings related to DFCT signal generation are Typ. t SPW 1/f SCLK MSB Min. Typ. Max. Unit 16 MHz ns 31.3 µ 3.3V ± 10 Symbol Min. Typ COUT f 40 MIRR f 5 DFCTH B – 12 – CXD3021R … … LSB = 0V, Topr = –20 to +75°C) SS Conditions Max. Unit kHz 1 kHz 2 kHz 3 ...
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... Input data hold time IDH Input LRCK setup time t ILRH Input LRCK hold time t ILRS BCKI PCMDI LRCKI (V = 3.3V ± 10%, Topr = –20 to +75°C) DD Min. Typ. Max. 4.5 100 WIB WIB t t IDS IDH t t ILRH ILRS – 13 – CXD3021R Unit MHz ns 50% ...
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... V (rms) dB 0.1 47k 8.2k 100p 8.2k 8.2k 1000p 15k 15k 39k 100p 15k 15k PWMLP PWMLN CXD3021R Audio Circuit PWMRP PWMRN – 14 – CXD3021R 220p 100 10µ 100k 0.1µ SHIBASOKU (AM51A) Analog 1ch Audio Analyzer 2ch ...
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... Topr = –20 to +75° via a 33k resistor.) DD Typ. Max. Unit Applicable pins V V FAO, TAO, SAO 0.97V DD DD 0.1V V FAO, TAO, SAO 0.03V DD DD Typ. Max. Unit Applicable pins V FAO, TAO, SAO 0.90V DD 0.1V 0.03V V FAO, TAO, SAO DD DD – 15 – CXD3021R ...
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... Description of Commands and Data Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 § 5-19. List of Servo Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 § 5-20. Filter Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 § 5-21. TRACKING and FOCUS Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 [6] Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Explanation of abbreviations AVRG: Average AGCNTL: Auto gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect – 16 – CXD3021R ...
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... Total bit length for each register Register Total bit length 8 bits bits 16 bits bits 7 32 bits 8 32 bits bits 20 bits B 28 bits C 20 bits D 20 bits E D18 D19 D20 D21 D22 D23 – 17 – CXD3021R 750ns or more Valid ...
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... FOCUS GAIN DOWN PHASE COMPENSATE FILTER A K2B 44 FOCUS GAIN DOWN DEFECT HOLD GAIN K2C 4E FOCUS GAIN DOWN PHASE COMPENSATE FILTER B K2D 1B FOCUS GAIN DOWN OUTPUT GAIN K2E 00 NOT USED K2F 00 NOT USED Fix indicates that normal preset values should be used. CONTENTS – 32 – CXD3021R ...
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... K47 00 NOT USED K48 02 FOCUS HOLD FILTER INPUT GAIN K49 7F FOCUS HOLD FILTER A-H K4A 7F FOCUS HOLD FILTER A-L K4B 79 FOCUS HOLD FILTER B-H K4C 17 FOCUS HOLD FILTER B-L K4D 54 FOCUS HOLD FILTER OUTPUT GAIN K4E 00 NOT USED K4F 00 NOT USED CONTENTS – 33 – CXD3021R ...
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... FBIAS Count STOP SSTP TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg Reg. XBUSY FOK 0 GFS COMP COUT OV64 0 – 34 – CXD3021R Output data length — — — — — — — — 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits — ...
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... High when Reg.B is latched, toggles each time the Reg.B number is input by CNIN. While $44 and $45 are being executed, toggles with each CNIN 8-count instead of the Reg.B number. Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing OV64 through the sync detection filter. – 35 – CXD3021R ...
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... MT0 LSSL 2.9ms 0 0.18s 1 TR3 TR2 0.18ms 0.09ms 0.36ms 0.18ms – 36 – CXD3021R Data 3 Timer range MT0 LSSL AS1 AS0 RXF RXF 1 RXF 0 RXF 1 RXF RXF = 0 Forward RXF = 1 Reverse Timer range ...
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... SD3 SD2 23.2ms 11.6ms 11.6ms 5.8ms KF3 KF2 0.72ms 0.36ms Data 1 Data – 37 – CXD3021R KF0 SD1 SD0 5.8ms 2.9ms 2.9ms 1.45ms KF1 KF0 0.18ms 0.09ms Data 3 Data ...
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... OFF 0dB – – 38 – CXD3021R D0 VCO SEL2 DA output for DA output for 48-bit slot 64-bit slot 0dB 0dB – dB – dB 0dB 0dB – dB 0dB – dB – dB ...
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... Each output signal is output from the SQSO pin. Input the readout clock to SQCK (See Timing Chart 2-4.) The error rate is output from the SQSO pin. Input the readout clock to SQCK (See Timing Chart 2-6.) Application Anti-rolling is enhanced. Sync window protection is enhanced. Function Processing – 39 – CXD3021R —: Don't care ...
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... Output of wide-band PLL VCO2 selected by VCO2CS is 1/2 frequency-divided Output of wide-band PLL VCO2 selected by VCO2CS is 1/4 frequency-divided Output of wide-band PLL VCO2 selected by VCO2CS is 1/8 frequency-divided. Data VCO KSL3 KSL2 KSL1 KSL0 SEL2 See the previous page. Processing Processing Processing Processing – 40 – CXD3021R ...
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... Block Diagram of VCO Internal Path VCO1SEL No.1 VCO1 No.2 VCO1 No.3 VCO1 No.4 VCO1 VCO2SEL Low-speed VCO2 High-speed VCO2 1/1 1/2 1/4 1/8 VCO1CS1, 0 KSL3, 2 VCO1 internal path 1/1 1/2 1/4 1/8 VCO2CS KSL1, 0 VCO2 internal path – 41 – CXD3021R To DSP interior To DSP interior ...
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... No.3 (High-speed VCO for CXD3005R No.4 The CXD3021R has four multiplier PLL VCO1s, and this command selects one of these VCO1s. Four VCOs are No.3, No.4, No.2 and No.1 in order of the maximum frequency. Command bit VCO2 THRU = 0 V16M output is connected internally to VCKI. VCO2 THRU = 1 V16M output is not connected internally. Input the clock from VCKI. ...
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... Clock switching for servo block; externally input. FSTIN = 1 The FSTIO pin serves as the input pin. The clock for the servo block is input from the FSTIO pin. Data OUTL 0 Processing Processing Processing Processing Processing – 43 – CXD3021R Data FSTIN ...
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... CAV-W modes) MDS = Z When DCLV MDP = ternary PWM output, carrier PWM and and fc = 140Hz when T B Processing Meaning BiliGL MAIN = 1 MAIN Mute – 44 – CXD3021R Data FLFC XWOC = 0 and 460Hz frequency of 132kHz carrier frequency of 132kHz frequency of 132kHz = 1. ...
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... Command bit SYCOF = 1 LRCK asynchronous mode. SYCOF = 0 Normal operation. Set SYCOF = 0 in advance in order to resynchronize the DAC using $9 command XWOC or the external pin XWO. Processing DAC sync window is open. DAC sync window is not open SYCOF 0 Processing Processing Processing – 45 – CXD3021R ...
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... Left channel output Right channel output 0 Mute Mute Mute Mute – 46 – CXD3021R Remarks Mute Mute Mute Mute Mute Reverse Stereo R R Mono ...
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... Zero detection mute is off. Command bit ZDPL = 1 LMUTO and RMUTO are high during mute. ZDPL = 0 LMUTO and RMUTO are low during mute. See the description of "Mute flag output" for the mute flag output conditions ZMUT ZDPL Processing Processing Processing Processing – 47 – CXD3021R ...
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... Normal operation DAC block clock is halted. DAC SLEEP = 1 Power consumption can be reduced. Command writing related to the audio DAC is invalid when DAC SLEEP=1. Data DSP 0 SLBS DIV4 SLEEP Processing Processing Processing Processing Processing – 48 – CXD3021R D1 D0 DSSP DAC SLEEP SLEEP ...
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... Then maximum value measuring continues until the next readout Mute ATT PCT1 PCT2 Command bit ATT = 0 ATT = 1 PCM Gain ECC error correction ability 0dB C1: double; C2: quadruple 0dB C1: double; C2: quadruple Mute C1: double; C2: double 0dB C1: double; C2: double – 49 – CXD3021R Data MCSL SOC2 Meaning Attenuation off. –12dB ...
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... When SOC2 = 0, SENS output is performed as usual. See "§ 1-4. Description of SENS Signals". When SOC2 = 1, the SQSO pin signal is output from the SENS pin. At this time, the readout clock is input to the SCLK pin. Note) SOC2 should be switched when SQCK = SCLK = high. Processing Processing – 50 – CXD3021R ...
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... Set DC offset to off when zero detection mute is on. Command bit FMUT = 1 Forced mute is on. FMUT = 0 Forced mute is off. Command bit BSBST = 1 Bass boost on. BSBST = 0 Bass boost off. Command bit BBSL = 1 Bass boost MAX. BBSL = 0 Bass boost MID BSBST BBSL Processing Processing Processing Processing – 51 – CXD3021R ...
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... The audio output, from 001H to 400H, is determined according to the following equation: 0dB Audio output = 20log : – Data 1 Data – 52 – CXD3021R Data Attenuation data [dB] 1024 Data 3 Data ...
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... Note) When DCLV = 0, the CLVS gain is as follows. When Gain CLVS = 0, GCLVS = –12dB. When Gain CLVS = 1, GCLVS = 0dB. 0dB 0dB Gain Gain MDS1 MDS0 Processing – 53 – CXD3021R Description D0 Valid only when DCLV = 1. Valid when DCLV = GMDS –6dB 0dB +6dB ...
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... The VPCO1 pin output is high and the VPCO2 pin is high impedance. The VPCO1 and 2 signals are output. The VPCO1 and 2 pin outputs are high impedance. The VPCO1 and 2 pin outputs are low. The VPCO1 and 2 pin outputs are high. Data Processing Processing – 54 – CXD3021R ...
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... The CXD3021R can serially output the 40 bits (10 BCD codes) of error rate data selected by EDC0 to 7 from the SQSO pin and monitor this data using a microcomputer. In order to output error rate data, set $C commands for C1 and C2 individually, and set SOCT0 and SOCT1 = command ...
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... Bottom hold at a cycle of RFCK/32 in CLVS and CLVH modes Bottom hold at a cycle of RFCK/16 in CLVS and CLVH modes Peak hold at a cycle of RFCK/4 in CLVS mode Peak hold at a cycle of RFCK/2 in CLVS mode. D0 Gain CLVS See "$CX commands". Description Description – 56 – CXD3021R ...
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... The rotational velocity R of the spindle can be expressed with the following equation. 256 – Relative velocity at normal speed = 1 n: VP0 to 7 setting value 1: Multiple set by VPCTL0, 1 Data VP4 VP3 VP2 VP1 VP0 Processing Processing – 57 – CXD3021R Data CTL1 CTL0 ...
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... Notes) 1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high. 2. Regarding the values in parentheses, the former ones are for when DSPB is 1 and VPCTL0 and the latter ones are for when DSPB is 1, VPCTL0 = 1 and VPCTL1 = 0. – 58 – CXD3021R ...
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... DSPB = 1 DSPB0 = VP0 to 7 setting value [H] DSPB = 1 DSPB = VP0 to 7 setting value [H] – 59 – CXD3021R When VPCTL0 = VPCTL1 = When VPCTL0 = 1, VPCTL1 = 0 ...
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... CLV CAV CAV VCO-C – 60 – CXD3021R Data VC2C HIFC LPWR VPON Description 1 Description Crystal reference CLV servo. Used for playback in CLV-W 2 mode. Spindle control with VP0 to 7. Spindle control with the external PWM ...
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... BRAKE 1-6 (b) STOP 1-6 (c) KICK 1-7 (a) 0 BRAKE 1-7 (b) STOP 1-7 (c) KICK 1-8 (a) 0 BRAKE 1-8 (b) STOP 1-8 (c) KICK 1-9 (a) 0 BRAKE 1-9 (b) STOP 1-9 (c) KICK 1-10 (a) 1 BRAKE 1-10 (b) STOP 1-10 (c) KICK 1-11 (a) 0 BRAKE 1-11 (b) STOP 1-11 (c) KICK 1-12 (a) 1 BRAKE 1-12 (b) STOP 1-12 (c) Timing chart 1- 1-15 1 1-16 1-17 (EPWM = 0) 0 1-18 (EPWM = 0) 1 1-19 (EPWM = 1-20 (EPWM = 1) – 61 – CXD3021R ...
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... The VPCO2 pin is used and the pin signal is the same as VPCO1. Data Gain INV FCSW CAV0 VPCO • This sets the gain when controlling the spindle with VP7 CAV-W mode. Note) Gain CAV1, 0 commands are invalid for spindle control with the external PWM. Processing – 62 – CXD3021R ...
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... CLV-N mode DCLV = 1, DCLV PWM MD = LPWR = 0 KICK Z MDS H MDP Z FSW L H MON (a) KICK BRAKE Z MDS MDP L FSW L H MON (b) BRAKE BRAKE Z MDS Z MDP L FSW L H MON (b) BRAKE – 66 – CXD3021R STOP Z MDS MDP L FSW L MON L (c) STOP STOP Z MDS Z MDP FSW L MON L (c) STOP ...
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... MDP L FSW L H MON (b) BRAKE BRAKE Z MDS Z MDP L FSW L H MON (b) BRAKE Other than when following the velocity, the timing is the same as Timing Chart 1-6 (b). – 67 – CXD3021R STOP MDS MDP L FSW L MON L (c) STOP STOP Z MDS Z MDP FSW L MON L (c) STOP ...
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... CAV-W mode DCLV = 1, DCLV PWM MD = LPWR = 0 KICK Z MDS H MDP FSW L H MON (a) KICK BRAKE MDS Z Z MDP FSW L H MON (b) BRAKE BRAKE Z MDS MDP L FSW L H MON (b) BRAKE – 68 – CXD3021R STOP MDS Z Z MDP FSW L MON L (c) STOP STOP Z MDS Z MDP FSW L H MON (c) STOP ...
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... CLV-N mode DCLV PWM LPWR = 0 MDS MDP 132kHz 7.6µs BRAKE Z MDS Z MDP FSW L H MON (b) BRAKE Z n 236 (ns • Acceleration n 236 (ns • Output Waveforms with DCLV = 1 – 69 – CXD3021R STOP Z MDS Z MDP FSW L H MON (c) STOP Z Deceleration Deceleration ...
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... CAV-W mode EPWM = DCLV PWM MD = LPWR = 0 Acceleration MDP 264kHz 3.8µs Timing Chart 1-18 CAV-W mode EPWM = DCLV PWM LPWR=1 Acceleration MDP 264kHz 3.8µs Z Deceleration Z The BRAKE pulse is maked when LPWR = 1. Deceleration The BRAKE pulse is maked when LPWR = 1. – 70 – CXD3021R ...
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... CAV-W mode EPWM = 1, DCLV PWM LPWR = 1 H PWMI MDP Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set DCLV PWM CLV-W and CAV-W modes. Acceleration Acceleration The BRAKE pulse is masked when LPWR = 1. – 71 – CXD3021R Deceleration ...
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... As a result, the 96-bit clock must be input in peak meter mode. • The absolute time after peak is stored in the memory in peak meter mode. (See Timing Chart 2-3.) • The high and low intervals for SQCK should be between 750ns and 120µs. – 72 – CXD3021R ...
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... Timing Chart 2-1 Internal PLL clock 4.3218 ± MHz WFCK SCOR EXCK SBSO WFCK SCOR EXCK SBSO · Same 750ns max S0 · · Same Subcode P.Q.R.S.T.U.V.W Read Timing – 73 – CXD3021R ...
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... VF0 the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTLI, XTLO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). Load – 77 – CXD3021R m ...
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... Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc. Note) The capture range for this mode is theoretically up to the signal processing limit. Note) Set FLFC to 1 for this mode. – 79 – CXD3021R ...
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... V16M = 32 The VCO1 oscillation frequency is determined by V16M. The VCO1 frequency can be expressed by the following equation. • When DSPB = 0 49 VCO1 = V16M 24 • When DSPB = 1 49 VCO1 = V16M 16 n: VP0 to VP7 setting value 1: VPCTL0, 1 setting value – 80 – CXD3021R ...
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... Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode CLV-W Mode CLV-W CLVP CLV-W MODE START KICK $E8000 Mute OFF $A00XXXX CAV-W $E665X (CLVA) NO ALOCK = H ? YES CLV-W $E6C00 (CLVA) (WFCK PLL) YES ALOCK = Fig. 3-2. CLV-W Mode Flow Chart – 81 – CXD3021R Operation mode Spindle mode Time ...
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... Switch to VCO control mode. $E00510 EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0 HIFC = VPON = 1 Transfer Transfer VP0 to VP7. ( $DX XX Track Jump Subroutine Transfer Switch to normal-speed playback mode. $E66500 EPWM = SFSL = VC2C = LPWR = 0 SPDC = ICAP = HIFC = VPON = 1 Access END – 82 – CXD3021R corresponds to VP0 to VP7.) ...
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... EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD3021R has a built-in three-stage PLL. • The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are necessary. ...
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... MUX Digital PLL Spindle rotation information 1/2 1/32 1/2 1/l 1 256 (VPCTL0, 1) (VP7 to VP0) VCOSEL2 1/K (KSL1, 0) VPON 1/M 1/N 1/K (KSL3, 2) VCOSEL1 RFPLL – 84 – CXD3021R CLV-W CAV-W VPCO1, 2 CLV-N CLV-W CAV-W /CLV-N LPF VCTL VCO2 V16M VCKI PCO FILI FILO CLTV VCO1 ...
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... For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. • The CXD3021R uses refined super strategy to achieve double correction for C1 and quadruple correction for C2. • In addition, to prevent C2 miscorrection pointer is attached to data after C1 correction according to the C1 error status, the playback status of the EFM signal, and the operating status of the player. • ...
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... C1 correction MNT2 MNT1 MNT0 § 4-4. DA Interface Output • The CXD3021R has two DA interface output modes. 1) 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. ...
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... There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD3021R supports type 2 form 1. This LSI supports 2 kinds of Digital Out generation methods; one is to generate the Digital Out using the PCM data read out from the disc and the other is to generate it using the DA interface input (PCMDI, LRCKI and BCKI) ...
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... Note) In this method, DOUT can be set to off by making the MD pin to 0 and $34A command DOUT CAT Table 4-6-2. – 91 – CXD3021R ...
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... WIN invalidate the automatic synchronization circuit. Clock System of DOUT Circuit For the DOUT block, the master clock is set using the clock control command MCSL ($A) employed by the DAC block. Set MCSL to 1 for 768fs and to 0 for 384fs. – 92 – CXD3021R ...
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... COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. – 94 – CXD3021R ...
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... COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator has stabilized. 16 tracks. After kicking the actuator and sled, the traverse for the traverse monitor counter which is set with register B, and 16 tracks. Like the 2N-track jump, COUT is used for counting – 95 – CXD3021R 16 ...
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... BUSY Command for $03 SSP Fig. 4-8-(b). Auto Focus Timing Chart Auto focus Focus search up FOK = H NO YES Check whether FZC is FZC = H NO continuously high for the period of time E set with register 5. YES FZC = L NO YES Focus servo ON END Blind E – 96 – CXD3021R $08 ...
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... Track Track FWD kick (REV kick for REV jump) sled servo OFF WAIT (Blind A) COUT = NO YES Track REV (FWD kick for REV jump) kick WAIT (Brake B) Track, sled servo ON END Fig. 4-9-(a). 1-Track Jump Flow Chart $2C ($28) – 97 – CXD3021R Brake B $25 ...
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... Fig. 4-10-(b). 10-Track Jump Timing Chart 10 Track Track, sled FWD kick WAIT (Blind A) (Counts COUT 5) COUT = YES Track, REV kick Checks whether the COUT cycle is longer than overflow Overflow ? NO YES Track, sled servo ON END COUT 5 count $2E ($2B) – 98 – CXD3021R Overflow C $25 ...
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... Track, sled FWD kick WAIT (Blind A) Counts COUT for the first 16 times and MIRR for more times. COUT (MIRR YES Track REV kick C = Overflow NO YES Track servo ON WAIT (Kick D) Sled servo ON END Overflow C $2E ($2B) $26 ($27) – 99 – CXD3021R Kick D $25 ...
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... Sled FWD Kick WAIT (Kick D) Track Sled FWD Kick WAIT (Kick F) Traverse Speed Ctrl (Overflow G) COUT = N? NO YES Track Servo ON Sled REV Kick WAIT (Kick D) Track Sled Servo ON END Traverse Speed Control (Overflow G) & COUT N count – 100 – CXD3021R Kick D $27 ($26) $25 ...
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... Command for servo $22 ($23) Fig. 4-13-(b). M-Track Move Timing Chart M Track Move Track Servo OFF Sled FWD Kick WAIT (Blind A) Counts COUT for M Counts MIRR for M COUT (MIRR YES Track, Sled Servo OFF END COUT (MIRR) M count – 101 – CXD3021R 16. 16. $20 ...
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... Mode Select MDS MDP Up/down signal from CLVS servo Frequency error for CLVP servo Phase error for CLVP servo Spindle drive signal from the microcomputer for CAV servo Fig. 4-14. Block Diagram – 102 – CXD3021R MDP Error Measure Filter-1 Gain MDP ...
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... Playback Speed In the CXD3021R, the following playback modes can be selected through different combinations of XTLI, XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode. XTLI XTSL ...
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... DAC Block Input Timing The DAC input timing chart is shown below. Audio data is not transferred from the CD signal processor block to the DAC block inside the CXD3021R. This enables to send data to the DAC block via the external audio DSP, etc. When the data is input to the DAC block without using the audio DSP, the data must be connected outside the LSI ...
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... Y2. And, when the command X3 is sent before the audio output rteaches the figure), the audio output approaches Y3 from the value ( the figure) at that point. 0dB 400(H) Approx. 370ms when crystal = 16.9344MHz Approx. 185ms when crystal = 33.8688MHz 23.2 [ms] – 105 – CXD3021R – 000(H) ...
Page 106
... For resynchronization, set the $9X command XWOC the external pin XWO to low, wait for one LRCK cycle or more, and then set XWOC to 1 and XWO to high. When setting XWOC the external pin XWO to low, be sure to set the $9X command SYCOF to 0 beforehand. Soft mute on 23.2 [ms] – 106 – CXD3021R Soft mute off 23.2 [ms] ...
Page 107
... The bass boost is set using BSBST and BBSL of address A. See Graph 4-15 for the digital bass boost frequency response. 10.00 8.00 6.00 4.00 2.00 0.00 –2.00 –4.00 –6.00 –8.00 –10.00 –12.00 –14. 100 300 1k 3k Digital bass boost frequency response [Hz] Graph 4-15. – 107 – CXD3021R Normal DBB MID DBB MAX 10k 30k ...
Page 108
... Asymmetry Correction Fig. 4-16 shows the block diagram and circuit example. ASYE R1 RFAC R1 BIAS Fig. 4-16. Asymmetry Correction Application Circuit CXD3021R + – – R1 – 108 – CXD3021R ASYO ASYI ...
Page 109
... OSC 768fs XTLO XTSL XT1D XT2D XT4D (Commands $3E, $3F) To DAC block 1 signal processor block 2/3 Selector FSTIN (Command $8X. "0" for preset; internally connected) 1/2 To digital servo block 1/4 – 109 – CXD3021R MCKO To exterior FSTIO FSTIN = 0: Output pin (Preset) FSTIN = 1: Input pin ...
Page 110
... MCK = 128Fs) Input range: 1/4V DD Output format: 8-bit DAC Other: Sled move FOK, MIRR, DFCT signal generation RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 1/4V DD Other: RF zero level automatic measurement 3/4V DD – 110 – CXD3021R : Supply voltage) ...
Page 111
... XT4D XT2D XT1D Table 5-1. – 111 – CXD3021R Frequency division ratio MCK 1 256Fs 1/2 128Fs 1/2 128Fs 1 512Fs 1/2 256Fs 1/4 128Fs 1/4 128Fs Fs = 44.1kHz, : Don't care ...
Page 112
... DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.) The CXD3021R can measure the averages of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD3021R, and is able to cancel the DC offset. ...
Page 113
... The number of steps by which the count value changes can be selected from steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 A: Register mode B: Counter mode C: Counter mode (when stopped) – 113 – CXD3021R V /2. DD ...
Page 114
... TLC2 • TLD2 to TRK In register – – TRVSC register TLC2 to FCS In register – + FBIAS register FBON to FZC register – register – to SLD In register – TLC2 • TLD2 to TRK In register – TRVSC register TLC2 to FCS In register + FBIAS register FBON to FZC register – CXD3021R ...
Page 115
... The default settings aim for 0dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. Max. 11.4µs Timing Chart 5-4 – 115 – CXD3021R AGCNTL completion ...
Page 116
... AGCNTL coefficient reaches the appropriate value and stops changing, the CXD3021R confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by setting AGS to 0 ...
Page 117
... FOCUS SERVO OFF, 0V OUT 0 1 FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP Table 5-6. $02 $03 and performing only FCS search operation. $00 $02 $03 FCSDRV RF FOK FE 0 FZC – 117 – CXD3021R : Don't care $08 Fig. 5-8. ...
Page 118
... The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD3021R has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 5-17.) SLD Servo ...
Page 119
... Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 –Peak Hold1 DFCT MIRR Comp (Mirror comparator level Fig. 5-11. SDF (Defect comparator level Fig. 5-12. – 119 – CXD3021R ...
Page 120
... When the upper 8 bits of the command register are $1, vibration detection can be monitored from the SENS pin. Anti Shock TE Filter TRK Gain Up Filter TRK Gain Normal Filter Hold Filter Hold register EN DFCT Servo Filter Fig. 5-13. ATSK Comparator TRK DAC Fig. 5-14. – 120 – CXD3021R SENS ...
Page 121
... ANTI SHOCK ON 0 ANTI SHOCK OFF 1 BRAKE ON BRAKE OFF 0 0 TRACKING GAIN NORMAL 1 TRACKING GAIN UP 1 TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 0 Table 5-17. – 121 – CXD3021R Outer track Inner track FWD Servo ON JMP Fig. 5-16. : Don't care ...
Page 122
... During readout, the upper 8 bits of the command register must be 39 (H). $3953: FCS AGCNTL coefficient result $3963: TRK AGCNTL coefficient result $391C: TRVSC adjustment result t SPW … 1/f SCLK … MSB Fig. 5-18. Symbol Min. Typ. f SCLK t 31.3 SPW t 15 DLS Table 5-19. – 122 – CXD3021R LSB Unit Max. MHz 16 ns µs ...
Page 123
... The coefficient rewrite command is comprised of 24 bits, with D14 $34 as the address (D15 = 0) and the data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients, be sure to wait 11.3µs (when MCK = 128Fs) before sending the next rewrite command. – 123 – CXD3021R ...
Page 124
... V DD 256 0. Output value –B 64MCK – 128 32MCK 32MCK 32MCK 256 –B – 256 256 Timing Chart 5-22 DRV / Fig. 5-23. Drive Circuit – 124 – CXD3021R Output value 0 64MCK 32MCK 32MCK V DD ...
Page 125
... When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. – 125 – CXD3021R ...
Page 126
... No time limit 0 1 1.1ms 1 0 2.2ms 1 1 4.0ms D10 KA2 KA1 KA0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D10 Processing Processing – 126 – CXD3021R MRT2 MRT1 0 0 ...
Page 127
... DOUT sync window is not open. DOUT sync window is open. DOUT WOD = 1 D10 EMPH CAT DOUT DOUT DOUT DMUT WOD Processing Processing Processing Processing Processing Processing Processing – 127 – CXD3021R WIN DOUT EN2 ...
Page 128
... CXD3021R DOUT output OFF 0dB The output from the PCM data readout from a disc – dB The output from the PCM data readout from a disc 0dB The output from the DA interface input – ...
Page 129
... SFBK1: When 1, brake operation is performed by setting the LowBooster-1 input to 0. This is valid only when TLB1ON = 1. The preset is 0. SFBK2: When 1, brake operation is performed by setting the LowBooster-2 input to 0. This is valid only when TLB2ON = 1. The preset is 0. D10 – 129 – CXD3021R ...
Page 130
... The sampling frequency is 88.2kHz (when MCK = 128Fs). Set SFJP ($36 TAOZ ($34D order to boost the low frequency for the TRK jump operation. Note 44.1kHz D10 FHB TLB1 FLB1 TLB2 0 HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 – 130 – CXD3021R ...
Page 131
... LB1S0 BK4 — –255/256 0 0 –511/512 1 1 –1023/1024 1 Table 5-25b. LowBooster-2 setting LB2S1 LB2S0 BK7 — –255/256 –511/512 1 –1023/1024 1 Table 5-25c. – 131 – CXD3021R BK2 BK3 96/128 2 112/128 2 120/128 2 BK5 BK6 1023/1024 1/4 2047/2048 1/4 4095/4096 1/4 BK8 BK9 1023/1024 1/4 2047/2048 1/4 4095/4096 1/4 ...
Page 132
... Fig. 5-26a. Servo HighBooster characteristics [FCS, TRK] (MCK = 128Fs) HBST1 = 0 HBST1 = 1, HBST0 = 100 1k Frequency [Hz 100 1k Frequency [Hz] HBST1 = 1, HBST0 = 1 3 – 132 – CXD3021R 10k 10k ...
Page 133
... Fig. 5-26b. Servo LowBooster-1 characteristics [FCS, TRK] (MCK = 128Fs) LB1S1 = 0 LB1S1 = 1, LB1S0 = 100 1k Frequency [Hz] 100 1k Frequency [Hz] LB1S1 = 1, LB1S0 = 1 3 – 133 – CXD3021R 10k 10k ...
Page 134
... Fig. 5-26c. Servo LowBooster-2 characteristics [FCS, TRK] (MCK = 128Fs) LB2S1 = 0 LB2S1 = 1, LB2S0 = 100 1k Frequency [Hz] 100 1k Frequency [Hz] LB2S1 = 1, LB2S0 = 1 3 – 134 – CXD3021R 10k 10k ...
Page 135
... SAOZ: When 0, the SLD drive DAC output is the center potential when the SLD servo is off. (default) When 1, the SLD drive DAC output is high impedance when the SLD servo is off. D10 FAOZ TAOZ SAOZ – 135 – CXD3021R ...
Page 136
... FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 D10 FB9 FB8 FB7 FB6 FB5 V D10 TV9 TV8 TV7 TV6 TV5 – 136 – CXD3021R — FB4 FB3 FB2 FB1 — respectively supply voltage ...
Page 137
... 1. 0.897 0.769 preset / supply voltage D10 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 V / supply voltage – 137 – CXD3021R supply voltage ...
Page 138
... Default value: 0 (256ms) D10 / supply voltage); FE input conversion DD DD Slice level preset 16/64 supply voltage FE/TE input conversion preset – 138 – CXD3021R ...
Page 139
... Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with are accepted every 2.9ms. (when MCK = 128Fs) All commands are on when 1. D10 – 139 – CXD3021R ...
Page 140
... RFDC envelope (bottom) RFDC envelope (peak) RFDC envelope (peak) – (bottom) VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal – 140 – CXD3021R Readout data length 8 bits 16 bits 8 bits $399F $399E 8 bits 9 bits $399D $399C 9 bits ...
Page 141
... Relative gain TPS1 0dB 0 +6dB 0 +12dB 1 +18dB 1 – 141 – CXD3021R SJHD INBK MTI0 The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step ...
Page 142
... 48/256 56/256 preset SDF1 Slice level 0 0.0156 0.0234 0.0313 0.0391 preset supply voltage DD MAX1 DFCT maximum time 0 No timer limit 1 2.00ms 0 2.36 1 2.72 : preset – 142 – CXD3021R ...
Page 143
... This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK. V V/ms, 44.1kHz) DD Count-down speed [V/ms] [kHz] 0.0431 V 22.05 DD 0.0861 V 44.1 DD 0.172 V 88.2 DD 0.344 V 176 preset supply voltage DD V V/ms, 352.8kHz) DD Count-down speed [V/ms] [kHz] 0.344 V 176.4 DD 0.688 V 352.8 DD 1.38 V 705.6 DD 2.75 V 1411 preset supply voltage DD – 143 – CXD3021R ...
Page 144
... BTS1 BTS0 MRC1 MRC0 TZC STZC HPTZC DTZC COUT pin output STZC HPTZC COUT : preset, —: don't care – 144 – CXD3021R MRC1 MRC0 Setting time [µ 5.669 0 1 11.338 1 0 22.675 ...
Page 145
... SLD filter OFF OFF OFF Tracking zero level correction TRK filter SLD filter OFF OFF OFF VC level correction TRK filter SLD filter OFF OFF OFF : preset, —: don't care – 145 – CXD3021R ...
Page 146
... Input coefficient sign inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, CXD3021R outputs servo drives which have the reversed phase of input errors. Negative input coefficient TE Negative input coefficient ...
Page 147
... MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source. – 147 – CXD3021R LKIN COIN MDFI MIRI XT1D : preset, —: don't care ...
Page 148
... 1/ 1 XT4D Frequency division ratio 0 According to XTSL — 1/1 — 1/2 1 1/4 – 148 – CXD3021R See $37 for AGGF and AGGT. The presets are AGG4 = 0, AGGF = 1 and AGGT = 1. : preset, —: don't care : preset, —: don't care ...
Page 149
... Data Readout" on the following page.) AGHF: This halves the frequency of the internally generated sine wave during AGC. FTQ: The slope of the output during focus search is 1/4 of the conventional output slope. On when 1; default is 0 SRO0 = 1 DA10 pin DA09 pin DA11 pin – 149 – CXD3021R ...
Page 150
... CLK Serial data input D/A Analog output Clock input Latch enable input Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. – 150 – CXD3021R … … … MSB LSB LSB To the 7-segment LED To the 7-segment LED MSB Data is connected to the 7-segment LED by 4 bits at a time ...
Page 151
... FOCUS GAIN DOWN PHASE COMPENSATE FILTER A K2B 44 FOCUS GAIN DOWN DEFECT HOLD GAIN K2C 4E FOCUS GAIN DOWN PHASE COMPENSATE FILTER B K2D 1B FOCUS GAIN DOWN OUTPUT GAIN K2E 00 NOT USED K2F 00 NOT USED Fix indicates that normal preset values should be used. CONTENTS – 151 – CXD3021R ...
Page 152
... NOT USED K48 02 FOCUS HOLD FILTER INPUT GAIN K49 7F FOCUS HOLD FILTER A-H K4A 7F FOCUS HOLD FILTER A-L K4B 79 FOCUS HOLD FILTER B-H K4C 17 FOCUS HOLD FILTER B-L K4D 54 FOCUS HOLD FILTER OUTPUT GAIN K4E 00 NOT USED K4F 00 NOT USED CONTENTS – 152 – CXD3021R ...
Page 153
... CXD3021R ...
Page 154
... CXD3021R ...
Page 155
... CXD3021R ...
Page 156
... CXD3021R ...
Page 157
... K02 K04 Note) Set the MSB bit of the K02 and K04 coefficients to 0. Slice M09 – K14 K15 – 157 – CXD3021R TRK AUTO Gain – M02 K05 K07 DAC SLD MOV TZC Reg M0A AUTO Gain ...
Page 158
... Note) Set the MSB bit of the K42 and K44 coefficients to 0. M10 – K49 K4B 2 – – 7 K4A K4C Note) Set the MSB bit of the K4A and K4C coefficients to 0. – 158 – CXD3021R M0A Anti Shock Comp K35 Reg – K33 K34 AVRG Reg M19 TRK K45 Hold Reg – ...
Page 159
... When using the preset coefficients with the boost function off. FOCUS frequency response NORMAL GAINDOWN 10 100 1k f – Frequency [Hz] When using the preset coefficients with the boost function off. – 159 – CXD3021R 180° 90° G 0° –90° –180° 20k 180° 90° ...
Page 160
... ATSK DATA XLAT CLOK COUT COUT MIRR MIRR DFCT DFCT FOK TESO FSW FSW Circuit Driver Circuit Driver – 160 – CXD3021R XOLT DA12 SOCK DA13 SOUT DA14 BCKI DA15 PCMDI DA16 LRCKI LRCK WDCK WDCK PSSL ASYE ...
Page 161
... COPPER ALLOY 0.8g PACKAGE MASS 120PIN LQFP(PLASTIC) 18.0 ± 0.2 1.7MAX 16.0 ± b=0.22 ± 0.05 (0.2) DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT LQFP-120P-L051 SOLDER P-LQFP120-16x16-0.5 LEAD MATERIAL COPPER ALLOY PACKAGE WEIGHT 0.8g – 161 – CXD3021R 1.4 ± 0 1.4 ± 0 ...