M37640E8FP Mitsumi Electronics, Corp., M37640E8FP Datasheet
M37640E8FP
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M37640E8FP Summary of contents
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... Power-saving modes ..... WIT (Idle), STP (Clocks halt) 1.3 APPLICATIONS Cameras, games, musical instruments, modems ) = 24 MHz in scanners, and PC peripherals MHz M37640E8FP M37640M8-XXXFP Package outline: 80P6N-A 7640 Group = 4.15~5.25V ...
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Ver 1.4 1.4 FUNCTIONAL BLOCK DIAGRAM Fig. 1.2. Functional Block Diagram 2 MITSUBISHI MICROCOMPUTERS 7640 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ...
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Ver 1.4 1.5 PIN DESCRIPTION AND LAYOUT Table 1.1. Pin Description and Layout NAME I/O P0 /AB0~ P1 /AB15 I/O CMOS I/O port (address bus). When the MCU is in memory expansion microprocessor mode, these pins function ...
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Ver 1.4 NAME I/O CMOS I/O port or IBF P7 /IBF /HLDA I/O IBF and HLDA are mutually exclusive. IBF /OBF I/O CMOS I/O port or OBF 4 1 CMOS I/O port or UART2 pin UTXD2 ...
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... M37640M8-XXXFP M 37640E8FP M37640E8FS MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Package Type: ROM Number ROM capacity: Memory type: 7640 Group 7600 Series M37640E8FP One-time PROM version ROM RAM Package capacity capacity type 32K bytes 1 K bytes 80P6N-A 32K bytes 1 K bytes 80P6N-A ...
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Ver 1.4 1.9 CENTRAL PROCESSING UNIT The central processing unit (CPU) has six registers: • Accumulator (A) • Index Register X (X) • Index Register Y (Y) • Stack Pointer (S) • Processor Status Register (PS) • Program Counter (PC) ...
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Ver 1.4 1.10 CPU MODE REGISTERS This device has two CPU mode registers: • CPU Mode Register A (CPMA) • CPU Mode Register B (CPMB) These registers control the processor mode, clock, slow memory wait and other CPU functions. The ...
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Ver 1.4 1.11 MEMORY MAP The first 112 bytes of memory from 0000 is the special function register (SFR) area and con- tains the CPU mode registers, interrupt registers, and other registers to control peripheral functions (see Figure 1.7). SFR ...
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Ver 1.4 1.12 PROCESSOR MODES The operation modes are described below. The memory maps for the first three modes are shown in Figure 1.8. Single chip mode is normally entered after reset. How- ever, if the MCU has a CNVss ...
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Ver 1.4 1.12.1 Single Chip In this mode, all ports take on their primary function and all internal memory is accessible. Those areas that are not in internal memory are not accessible. Also, slow memory wait and EDMA are disabled ...
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out AD out DB in/out Out RDY No Wait One Time S/W Wait CPMB = 01 CPMB = out AD out DB In in/out RD WR ...
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out AD out DB in/out In Out RDY One Time Fixed Wait No Wait CPMB = 09 CPMB = out AD out ...
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out AD out DB in/out In In Out ///////// ///////// RDY One Time Extended RDY Wait No Wait CPMB = 0D CPMB = ...
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Ver 1.4 1.12.5 Hold Function The hold function is used when the MCU is put in a system where more than one device will need control of the external address and data buses. Two signals are used to implement this ...
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Ver 1.4 SYNC out RD WR Address PC Data 91 EDMA Fig. 1.13. Instruction sequences for STA ($zz) IndY with EDMA Enable [LDA ($zz), “0”)] Instruction Sequence (EDMA) SYNC out Address B1 Data ...
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Ver 1.4 1.13 SPECIAL FUNCTION REGISTERS The special function registers (SFR) are used for controlling the functional blocks, such as I/O ports, Timers, UART, and so forth (see Table 1.4). The re- served addresses should not be read or written ...
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Ver 1.4 1.14 INPUT AND OUTPUT PORTS Table 1.5. Input and Output Ports Pin Name Input/ Output Input/output, Port 0 P0 – P0 individual bits 0 7 Input/output, Port 1 P1 – P1 individual bits 0 7 Port 2 Input/output, ...
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Ver 1.4 1.14.1 I/O Ports This device has 66 programmable I/O pins arranged as ports Each port bit can be configured input or output. To set the I/O port bit direction, write a ...
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Ver 1.4 1.14.1.3 Port P4 Port 5-bit general purpose I/O port that can be configured to access special second functions. The port can be set up in any configuration in all three pro- cessor modes. Port P4 ...
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Ver 1.4 1.14.1.4 Port P5 Port 8-bit general purpose I/O port that can be configured to access special second functions. The port can be set up in any configuration in all three pro- cessor modes. Port P5 ...
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Ver 1.4 1.14.1.5 Port P6 Port 8-bit general purpose I/O port that can be configured to access special second functions. The port acts as the data bus interface for the bus in- terface control block when DBBC06 ...
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Ver 1.4 1.14.1.6 Port P7 Port 5-bit general purpose I/O port that can be configured to access special second functions. Port P7 0 This pin is multiplexed with the USB start of frame pulse (SOF) output. When ...
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Ver 1.4 1.14.5.7 Port 8 Port 8-bit general purpose I/O port that can be configured to access special second functions. The port can be set up in any configuration in all three pro- cessor modes. Port P8 ...
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Ver 1.4 Port P8 4 This pin is multiplexed with the UART1 TxD signal. When UART1 is in transmit mode, the pin acts as the TxD output signal. Port P8 5 This pin is multiplexed with the UART1 RxD signal. ...
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Ver 1.4 1.14.2 Port Control Register (PTC) This device is equipped with a port control register to turn on and off the slew rate control and to control the input levels for Port P2 and the MBI pins (see Figure ...
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Ver 1.4 1.15 INTERRUPT CONTROL UNIT This section details a specialized peripheral, the inter- rupt control unit (ICU). This series supports a maximum of 23 maskable inter- rupts, one software interrupts, and one reset vector that is treated as a ...
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Ver 1.4 1.15.1 Interrupt Control Each maskable interrupt has associated with it an in- terrupt request bit and an interrupt enable bit. These bits, along with the I flag, determine whether interrupt events can cause an interrupt service request to ...
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Ver 1.4 MSB ICA7 ICA6 ICA5 ICA4 ICA3 Fig. 1.27 Interrupt Control Register A (ICONA) MSB ICB7 ICB6 ICB5 ICB4 ICB3 7 Fig. 1.28. Interrupt Control Register B (ICONB) Reserved ICC6 ICC5 ICC4 ICC3 MSB 7 Fig. 1.29. Interrupt Control ...
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Ver 1.4 1.16 KEY-ON WAKE UP This device contains a key-on wake up interrupt func- tion. The key-on wake up interrupt function is one way of returning from a power-down state caused by the STP or WIT instructions. This interrupt ...
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Ver 1.4 1.17 TIMERS This device has five built-in timers: Timer X, Timer Y, Timer 1, Timer 2, and Timer 3. The contents of the timer latch, corresponding to each timer, determine the divide ratio. The timers can be read ...
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Ver 1.4 MSB TXM7 TXM6 TXM5 TXM4 TXM3 7 Fig. 1.33. Timer X Mode Register (TXM ) 1.17.1 Timer X Timer 16-bit timer that has a 16-bit reload latch, and can be placed in one of four ...
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Ver 1.4 •Pulse Output Mode Count Source:F/n (where 16, 32, or 64) or SCSGCLK Each time the timer X underflows, the output of the CNTR0 pin is inverted, and the corresponding Timer X interrupt request bit is ...
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Ver 1.4 MSB TYM3 TYM7 TYM6 TYM5 TYM4 7 Fig. 1.34. Timer Y Mode Register (TYM) 1.17.2 Timer Y Timer 16-bit timer that has a 16-bit reload latch, and can be placed in any of four modes ...
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Ver 1.4 Each time the Timer Y underflows, the output of the CNTR1 pin is inverted, and the corresponding Timer Y interrupt request bit is set to a “1”. The repeated in- version of the CNTR1 pin output produces a ...
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Ver 1.4 MSB T123M7 T123M6 T123M5 T123M4 T123M3 7 Fig. 1.35. Timer Mode Register (T123M) 1.17.3 Timer 1 Timer 8-bit timer with an 8-bit reload latch and has a pulse output option (see Figure ...
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Ver 1.4 1.17.4 Timer 2 Timer 8-bit timer with an 8-bit reload latch (see Figure 1.35). T123M7 (bit 7 of T123M) is the Timer 1 and 2 Data Write Control Bit. If T123M7 is “1”, data written ...
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Ver 1.4 1.18 SERIAL I/O The Serial I/O has the following main features: • Synchronous transmission or reception • Handshaking via SRDY output signal • 8-bit character length • Interrupt after transmission or reception • Internal Clock (When serial I/O ...
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Ver 1.4 1.18.1 SIO Control Registers (SIOCON) The Serial I/O Control Register 1 controls various SIO functions such as transfer direction and transfer clock divisor (see Figure 1.37). All of this register’s bits can be read from and written to ...
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Ver 1.4 1.18.2 SIO Normal Operation An internal clock or an external clock can be selected as the synchronous clock. When the internal clock is chosen, dividers are built in to provide eight different clock selections. The start of a ...
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Ver 1.4 1.18.3 SPI Compatible Operation Setting the SPI bit (bit 0 in SIOCON2) puts the SIO in an SPI compatible mode. The internal/external clock select bit (bit 6 in SIOCON1) determines whether the SIO is an SPI master or ...
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Ver 1.4 1.19 UART This chip contains two identical UARTs. Each UART has the following main features: • Clock selection .................................. F or SCSGCLK • Prescaler selection ............... x1/x8/x32/x256 divisions ............................................ (both F and SCSGCLK) • Baud rate .......................................... (at ...
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Ver 1.4 1.19.1 UART Mode Register (UxMOD) UxMOD defines data formats and selects the clock to be used (see Figure 1.42). MSB LE1 LE0 PEN PMD 7 Fig. 1.42. UART Mode Register (U1MOD, U2MOD) MSB RTS_SEL CTS_SEL ...
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Ver 1.4 1.19.3 UART Status Register (UxSTS) The UART Status Register (UxSTS) reflects both the transmit and receive status (see Figure 1.44). The sta- tus register is read only. The MSB is always “0” during a read operation. Writing to ...
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Ver 1.4 MSB Reserved SER OER FER PER 7 Fig. 1.44. UART Status Register (U1STS, U2STS) 1.19.4 Transmit/Receive Methods 1.19.4.1 Transmit Method Setup •Define the baud rate by writing a value from 0-255 into the UxBRG (see Figure 1.45). •Set ...
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Ver 1.4 UxBRG Clock UxTRB1 Write TBE TCM UTXDx Start bit Fig. 1.45. UART Transmit Operation Waveform 1.19.4.2 Receive Method Set up •Define the baud rate by writing a value from 0-255 into UxBRG. •Set the Receive Initialization Bit (RIN, ...
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Ver 1.4 URXDx Start bit UxBRG Clock Edge 2-of-3 detection sampling RBF UxTRB1 Read Fig. 1.46. UART Receive Operation Waveforms CTS (input) TXD (output) RXD (input) DATA RTS (output) In both examples, the Transmit and Receive have already been enabled ...
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Ver 1.4 1.19.5 Interrupts The transmit and receive interrupts are generated un- der the conditions described below. The generation of the receive interrupts differs when UART Address mode is enabled. 1.19.5.1 Transmit interrupts The UART generates a Transmit interrupt to ...
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Ver 1.4 1.19.7 UART Address Mode The UART address mode is intended for use in a multi-receiver environment where an address is sent before each message to designate which UART or UARTs are to wake-up and receive the message. An ...
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Ver 1.4 1.20 SPECIAL COUNT SOURCE GENERATOR This device has a built-in special count source genera- tor. It cons ists of two 8-bit timers: SCSG1, and SCSG2 (see Figure 1.49). The contents of the timer latch, corresponding to each timer, ...
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Ver 1.4 1.21 UNIVERSAL SERIAL BUS The Universal Serial Bus (USB) has the following fea- tures: •Complete USB Specification (version 1.1) Compatibility •Error Handling capabilities •FIFOs: •Endpoint 0: IN 16-byte •Endpoint 1: IN 512-byte OUT 800-byte •Endpoint 2: IN 32-byte ...
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Ver 1.4 1.21.2 USB Interrupts There are two types of USB interrupts in this device. USB function (including overrun/underrun, reset, sus- pend and resume) interrupt, which is used to control the flow of data. The second type is start-of-frame (SOF) ...
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Ver 1.4 1.21.3.1 IN (Transmit) FIFOs The CPU/DMA writes data to the endpoint’s IN FIFO location specified by the FIFO write pointer, which au- tomatically increments by “1” after a write. The CPU/ DMA should only write data to the ...
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Ver 1.4 The following outlines the operation sequence for an IN endpoint used to communicate rate feedback infor- mation: 1. Set MAXP > 1/2 of the endpoint’s FIFO size 2. Set the INTPT bit of the IN CSR 3. Flush ...
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Ver 1.4 1.21.4 USB Special Function Registers The MCU controls USB operation through the use of special function registers (SFR). This section de- scribes in detail each USB related SFR. Certain USB SFRs are endpoint-indexed: the Control & Status Registers ...
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Ver 1.4 The USB Power Management Register, shown in Figure 1.54, is used for power management in the USB FCU. • USB Suspend Detection Flag (SUSPEND) When the USB FCU does not detect any bus activ- ity on D+/D- for ...
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Ver 1.4 The USB FCU is able to generate a USB function in- terrupt as discussed in section 1.21.2.1. The USB Interrupt Status Registers (USBIS1, USBIS2), shown in Figure 1.55 and Figure 1.56, are used to in- dicate the condition ...
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Ver 1.4 MSB INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 7 Fig. 1.57. USB Interrupt Enable Register 1 (USBIE1) MSB INTEN15 INTEN12 Fig. ...
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Ver 1.4 MSB FN7 FN6 FN5 FN4 7 Fig. 1.59. USB Frame Number Low Register (USBSOFL) MSB ved ...
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Ver 1.4 MSB INOCSR7 INOCSR6 INOCSR5 INOCSR4 INOCSR3 INOCSR2 INOCSR1 INOCSR0 7 Fig. 1.62. USB Endpoint 0 IN CSR (IN_CSR) The USB Endpoint 0 IN CSR Control & Status Register, shown in Figure 1.62, contains the control and status information ...
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Ver 1.4 All of the conditions stated on the preceeding page (except the bad data toggle in the SETUP state case) cause the device to send a STALL handshake for the IN/OUT token in question. In the bad data toggle ...
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Ver 1.4 INXCSR3 (ISO/TOGGLE_INIT): When the endpoint is used for isochronous data transfer, the CPU sets this bit to a “1” for the entire duration of the isochronous transfer. With the ISO bit set to a “1”, the device uses ...
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Ver 1.4 MSB OUTXCSR7 OUTXCSR6 OUTXCSR5 OUTXCSR4 OUTXCSR3 7 Fig. 1.65. USB Endpoint x OUT CSR (OUT_CSR) The USB Endpoint x OUT CSR (Control & Status Register), shown in Figure 1.65, contains control and status information of the respective OUT ...
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Ver 1.4 The USB Endpoint x IN MAXP, shown in Figure 1.66, indicates the maximum packet size (MAXP Endpoint x IN packet. The default value for Endpoint 0 and 2 The default value for Endpoint 1 ...
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Ver 1.4 The USB Endpoint x FIFO Registers, shown in Fig- ure 1.70 through Figure 1.74, are the USB IN (transmit) and OUT (receive) FIFO data registers. The CPU writes data to these registers for the corre- sponding Endpoint IN ...
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Ver 1.4 1.22 MASTER CPU BUS INTERFACE This device has a bus interface function with 2 I/O buff- ers that can be operated in slave mode by control signals from the master CPU (see Figure 1.75). Bus Interface Circuit). The ...
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Ver 1.4 1.22.1 Data Bus Buffer Status Registers (DBBS0, DBBS1) The data bus buffer status register is an 8-bit register that indicates the data bus status, with bits 0, 1, and 3 being dedicated read-only bits. Bits ...
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Ver 1.4 MSB DBBS13 DBBS17 DBBS16 DBBS15 DBBS14 7 Fig. 1.79. Data Bus Buffer Status Register 1 (DBBS1) MSB DBBC17 ved ved DBBC14 DBBC13 7 Fig. 1.80. Data Bus Buffer Control Register ...
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Ver 1.4 1.23 DIRECT MEMORY ACCESS CONTROLLER This device contains a two-channel Direct Memory Access Controller (DMAC). Each channel performs fast data transfers between any two locations in the memory map initiated by specific peripheral events or software triggers. The ...
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Ver 1.4 MSB DCI ved DRLDD DTSC DISFI 7 Fig. 1.82. DMAC Index and Status Mode Register (DMAIS) MSB DxTMS DxRLD DxDAUE DxDWC DxDRCE Fig. 1.83. DMAC Channel x Mode Register 1 (DMAxM1) MITSUBISHI MICROCOMPUTERS SINGLE-CHIP ...
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Ver 1.4 MSB D0CEN D0CRR D0UMIE D0SWT D0HRS3 Fig. 1.84. DMAC Channel 0 Mode Register 2 (DMA0M2) MSB D1CEN D1CRR D1UMIE D1SWT D1HRS3 7 Fig. 1.85. DMAC Channel 1 Mode Register 2 (DMA1M2) 70 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ...
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Ver 1.4 out SYNC out RD WR Address PC Data DMAC Transfer Signal (Port3 ) 3 Transfer Request Source (active low) Transfe Request Source Sampling Transfer Request Source Sample Latch Reset Fig. 1.86. DMAC Transfer-Hardware Source Initiated out SYNC out ...
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Ver 1.4 1.24 OSCILLATOR CIRCUIT An on-chip oscillator provides the system and periph- eral clocks as well as the USB clock necessary for operation. This oscillator circuit is comprised of ampli- fiers that provide the gain necessary for oscillation, oscillation ...
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Ver 1.4 RESET X in clock clock stopped Note 1 Stop PLL clock stopped =f(X in )/4 Note 2 Wait CPMA=0C, FSC= CPMA4 X in clock clock on Stop Note 1 PLL ...
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Ver 1.4 1.24.1 Frequency Synthesizer Circuit The Frequency Synthesizer Circuit generates a 48MHz clock needed by the USB block and a clock f are both a multiple of the external input reference clock block diagram of the ...
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Ver 1.4 P1HATRSTB P2LATRSTB PIN1 PIN2 PIN1 PadResetB P2 Peripheral Oscillator Countdown P1 Peripheral Timer 1->2 Interrupt Request I Flag S PadResetB STP Delay R QB OSCSTP XOSCSTP ...
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Ver 1.4 MSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 7 FSM1 f n PIN 10 320.00 KHz 74 2.00 MHz 11 4.00 MHz 5 6.00 MHz 3 12.00 MHz 1 24.00 MHz ...
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Ver 1.4 1.25 LOW POWER MODES This device has two low-power dissipation modes: •Stop •Wait 1.25.1 Stop Mode Use of the stop mode allows the MCU to be placed in a state where no internal excitation of the circuitry is ...
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Ver 1.4 1.25.2 Wait Mode Use of the wait mode allows the microcomputer to be placed in a state where excitation of the CPU is stopped, but the clocks to the peripherals continue to oscillate. This mode provides lower power ...
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Ver 1.4 1.26 RESET This device is reset if the RESET pin is held low for a minimum of 2ms while the supply voltage is set be- tween 4.15 and 5.25V. When the RESET pin returns high, the reset sequence ...
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Ver 1.4 2.1 ABSOLUTE MAXIMUM RATINGS Table 2.1 Absolute Maximum Ratings Symbol Parameter V Power supply CC AV Analog power supply CC V Input voltage P0, P1, P2, P3, P4, P5, P6, P7 Input voltage RESET, X ...
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Ver 1.4 2.2 RECOMMENDED OPERATING CONDITIONS Table 2.2. Recommended Operating Conditions (Vcc = 4.15 to 5.25V, Vss = 0V - Symbol V Supply voltage CC AV Analog supply voltage CC V Supply voltage SS AV Analog ...
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Ver 1.4 2.3 ELECTRICAL CHARACTERISTICS Table 2.3. Electrical Characteristics (Vcc = 4.15 to 5.25V, Vss = 0V - Symbol Parameters H output V P0, P1, P2, P3, P4, P5, P6, P7 voltage H output ...
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Ver 1.4 2.4 TIMING REQUIREMENTS AND SWITCHING CHARACTERISCTICS Table 2.4 Timing Requirements and Switching Characterisctics (Vcc = 4.15 to 5.25V, Vss = 0V -20 to 85°C unless otherwise noted) Symbol Parameter Inputs tw(RESET) RESET input “Low” pulse width ...
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Ver 1.4 Table 2.4 Timing Requirements and Switching Characterisctics (continued) (Vcc = 4.15 to 5.25V, Vss = 0V -20 to 85°C unless otherwise noted) Parameter Symbol _ __ MBI (Separate R and W Type Mode) _ tsu(S-R) S ...
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Ver 1.4 Inputs RESET Interrupts _____ _____ INT0, INT1 CNTR0, CNTR1 Timers TOUT CNTR0, CNTR1 CNTR0, CNTR1 Fig. 2.1. Reset, Clock, Interrupts and Timers Timing Diagram MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER _______ tw(RESET) 0.2Vcc tc twh(X ) ...
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Ver 1.4 Read OBF Write IBF Note: TTL input levels in parenthesis (TTL levels selected when PTC7 = “1”) Fig. 2.2. MBI ...
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Ver 1.4 Table 2.5. Memory Expansion Mode and Microprocessor Mode Timing (Vcc = 4.15 to 5.25V, Vss = 0V -20 to 85°C unless otherwise noted) Symbol tc( ) clock cycle time twh( ) clock “H” pulse width twl( ...
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Ver 1.4 0.5Vcc td( AB15-AB8 td( AB7-AB0 RD, WR SYNC OUT td( - DMA 0.5Vcc OUT RDY HOLD (Enter state) HLDA HOLD (Exit state) HLDA DB0-DB7 (CPU Read Phase) DB0-DB7 (CPU Write Phase) USB D+ USB D- Fig. 2.4. Microprocessor ...
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Ver 1.4 RD, WR AB15-AB8 AB7-AB0 RDY DB0-DB7 (CPU Read Phase) DB0-DB7 (CPU Write Phase) Fig. 2.5. Microprocessor and Memory Expansion Mode Timing Diagram 2 SIO Fig. 2.6. SIO Timing Diagram Measurement output pin Fig. 2.7. Output Switching Characteristics Measurements ...
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Ver 1.4 DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1. Mask ROM Order Confirmation Form 2. Mark Specification Form 3. Data to be written to ROM, in EPROM form three identical copies) ...
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Ver 1.4 GZZ-SH57-30B<9XA0> 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37640M8-XXXFP We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to ...
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Ver 1.4 GZZ-SH57-30B<9XA0> 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37640M8-XXXFP MITSUBISHI ELECTRIC Company name * Customer Date Date: issued *1 Confirmation Three EPROMs are required for each pattern if this order is performed by EPROMs. One floppy disk ...
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Ver 1.4 80P6n (80-PIN QFP) MARK SPECIFICATION FORM Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). Notes A. Standard Mitsubishi Mark ...
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Ver 1.4 80P6N-A EIAJ Package Code JEDEC Code QFP80-P-1420-0.80 – MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Weight(g) Lead Material 1.58 Alloy ...
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Ver 1.4 HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that ...
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REVISION HISTORY Rev. No. 1.4 First Edition 7640 GROUP DATA SHEET Revision Description (1/1) Rev. date 09/05/00 ...