W83787IF Winbond, W83787IF Datasheet
W83787IF
Available stocks
Related parts for W83787IF
W83787IF Summary of contents
Page 1
... The W83787IF integrates a disk drive adapter ,two 16550 compatible UARTs, and one parallel port with EPP mode, ECP mode, and joystick mode. The disk drive adapter functions of the W83787IF is sames as W83787F which including a floppy disk drive controller compatible with the industry standard 765, data separator, write pre- compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic ...
Page 2
... Extension 2FDD mode support disk drive A and B through parallel port --- Compatible with IBM Parallel Port --- Support parallel port with bi-directional lines IDE Interface --- Support two embedded hard disk drives(IDE AT BUS) Game Port Supported Based on pinout of W83777/787F Two General Purpose I/O pins 100 PQFP Publication Release Date:Sep 1995 - 2 - W83787IF Revision A1 ...
Page 3
... FUNCTION Publication Release Date:Sep 1995 - 3 - W83787IF RIB 50 X DCDB DSRB X CTSB DTRB X 45 RTSB X 44 IRQ3 ...
Page 4
... Extension Adapter. When this pin is active, a DMA cycle is underway and the controller is executing a DMA transfer. In ECP mode, this pin is the parallel port DMA Acknowledge input. XTAL1 7 I 24Mhz XTAL/Oscillator/Clock input XTAL2 8 O XTAL output FUNCTION Publication Release Date:Sep 1995 - 4 - W83787IF Revision A1 ...
Page 5
... UART B Data Terminal Ready. An active low informs the modem or DTRB data set that controller is ready to communicate. HURAS0 During power-on reset, this pin is pulled down internally and is defined as HURAS0 used for setting the I/O address of UART A. (See Table 1-2.) FUNCTION Publication Release Date:Sep 1995 - 5 - W83787IF Revision A1 ...
Page 6
... CRA. The active state is dependent on bit 6 of CRA (PEXTACT); the default is low active. During power-on reset, this pin is pulled down internally and is defined as HPRTM0 used to determine the mode of the parallel port. (See Table 1-1.) FUNCTION FUNCTION Publication Release Date:Sep 1995 - 6 - W83787IF Revision A1 ...
Page 7
... This pin is an interrupt request generated by the Extension Adapter and is an active high input. EXTENSION 2FDD MODE: MOB2 OD This pin is for Extension FDD A and B; the function of this pin is the same as that of the MOB pin. JOYSTICK MODE: NC pin. _ FUNCTION Publication Release Date:Sep 1995 - 7 - W83787IF Revision A1 ...
Page 8
... EXTENSION ADAPTER MODE: XA0 O This pin is system address A0 for the Extension Adapter. EXTENSION 2FDD MODE: WD2 OD This pin is for Extension FDD A and B; this function of this pin is the same as that of the WD pin. JOYSTICK MODE: NC pin. _ FUNCTION Publication Release Date:Sep 1995 - 8 - W83787IF Revision A1 ...
Page 9
... HEADpin. EXTENSION ADAPTER MODE: XA2 O This pin is system address A2 for the Extension Adapter. EXTENSION 2FDD MODE: HEAD2 OD This pin is for Extension FDD A and B; its function is the same as that of the HEAD pin. JOYSTICK MODE: NC pin. _ FUNCTION Publication Release Date:Sep 1995 - 9 - W83787IF Revision A1 ...
Page 10
... This pin is the DMA acknowledge output for the Extension Adapter; the output is sent directly from PDACKX . EXTENSION 2FDD MODE: DIR2 OD This pin is for Extension FDD A and B; its function is the same as that of the DIR pin. JOYSTICK MODE FUNCTION for joystick. DD for joystick. DD Publication Release Date:Sep 1995 - 10 - W83787IF Revision A1 ...
Page 11
... Adapter address register, XRD and XWR go low simultaneously so that the command register on the Extension Adapter can latch the same base address. EXTENSION 2FDD MODE: This pin is a tri-state output. - JOYSTICK MODE FUNCTION for joystick. DD for joystick. DD Publication Release Date:Sep 1995 - 11 - W83787IF Revision A1 ...
Page 12
... This pin is system data bus D1 for the Extension Adapter. EXTENSION. 2FDD MODE: TRAK02 I This pin is for Extension FDD A and B; this function of this pin is the same as TRAK0 pin. This pin is pulled high internally. JOYSTICK MODE: JP1 I/O This pin is the paddle 1 input for joystick. FUNCTION Publication Release Date:Sep 1995 - 12 - W83787IF Revision A1 ...
Page 13
... This pin is system data bus D3 for the Extension Adapter. EXTENSION 2FDD MODE: RDATA2 I This pin is for Extension FDD A and B; this function of this pin is the same as that of the RDATA pin. This pin is pulled high internally. JOYSTICK MODE: NC pin - FUNCTION Publication Release Date:Sep 1995 - 13 - W83787IF Revision A1 ...
Page 14
... This pin is a tri-state output. I/O EXTENSION ADAPTER MODE: XD5 This pin is system data bus D5 for the Extension Adapter - EXTENSION 2FDD MODE: This pin is a tri-state output. I JOYSTICK MODE: JB1 This pin is the button 1 input for the joystick. FUNCTION Publication Release Date:Sep 1995 - 14 - W83787IF Revision A1 ...
Page 15
... GIO1.If GIOSEL=0,this pin act as IDED7.It can also be programmed by CR0C register bit 1 O Reset signal for IDE, active low to initialize the IDE RESIDE IRRX3 I RESIDE can be programmed by CR0D register as input pin IRRX3 for serial infrared communication. FUNCTION FUNCTION 2. Publication Release Date:Sep 1995 - 15 - W83787IF Revision A1 ...
Page 16
... FDC function. When set to low, it enables the FDC port (default). When set to high, it disables the FDC port. PDBDIR can be programmed by CR0D register as output pin IRTX2 for serial infrared communication. FUNCTION Publication Release Date:Sep 1995 - 16 - W83787IF Revision A1 ...
Page 17
... When bit 5 of CR9 (EN3MODE) is set to high, the three-mode FDD function is enabled, and the pin will have a different definition. Refer to the EN3MODE bit in CR9. Write data. This logic low open drain writes precompensation serial data to the selected FDD. An open drain output. Publication Release Date:Sep 1995 - 17 - W83787IF Revision A1 ...
Page 18
... V 15 GND 25, 40 Ground 65, 90 Table 1-1: PARALLEL PORT FUNCTION MODE POWER-ON SETTING PDRQX GMWR HPRTM1 HPRTM0 L L Printer Mode (Default ECP/EPP H L EPP H H EXT2FDD FUNCTION Publication Release Date:Sep 1995 - 18 - W83787IF Revision A1 ...
Page 19
... IDED7 UART B SOUTB RTSB HURBS HURBS0 W83787IF nRESIDE/IRRX3 PDBDIR/IRTX2/nFDCEN PDCIN/IRRX2 SINB/IRRX1 SOUTB/IRTX1/HURBS1 nDBENL/nIDBEN/GIOSEL nDBENH/GIO0/URIRSEL nIOCS16 nCS0/IRRX4/nIDEEN nCS1/IRTX3/HADSEL IDED7/GIO1 Publication Release Date:Sep 1995 - 19 - W83787IF COM3 (3E8) COM4 (2E8) COM2 (2F8) (Default) Disabled Revision A1 ...
Page 20
... FDC FUNCTIONAL DESCRIPTION 2.1 W83787IF FDC The floppy disk controller of the W83787IF integrates all of the logic required for floppy disk control.The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital Data Separator, and FDC Core. 2.1.1 AT interface The interface consists of the standard asynchronous signals: /RD, /WR, A0-A3, IRQ, DMA control, and a data bus ...
Page 21
... Record RCN: Relative Cylinder Number R/W: Read/Write SC: Sector/per cylinder SK: Skip deleted data address mark SRT: Step Rate Time ST0: Status Register 0 ST1: Status Register 1 ST2: Status Register 2 ST3: Status Register 3 WG: Write gate alters timing of WE Publication Release Date:Sep 1995 - 21 - W83787IF Revision A1 ...
Page 22
... HDS DS1 DS0 Publication Release Date:Sep 1995 - 22 - W83787IF REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution REMARKS Command codes ...
Page 23
... HDS DS1 DS0 Publication Release Date:Sep 1995 - 23 - W83787IF REMARKS Status information after command execution Sector ID information after command execution REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all ...
Page 24
... HDS DS1 DS0 Publication Release Date:Sep 1995 - 24 - W83787IF REMARKS Command codes The first correct ID information on the cylinder is stored in Data Register Status information after command execution Disk status after the command has been completed REMARKS Command codes ...
Page 25
... HDS DS1 DS0 Publication Release Date:Sep 1995 - 25 - W83787IF REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Revision A1 ...
Page 26
... DS1 DS0 Publication Release Date:Sep 1995 - 26 - W83787IF REMARKS Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after command execution REMARKS Command codes Head retracted to Track 0 Interrupt REMARKS Command code Status information at the ...
Page 27
... HDS DS1 DS0 Publication Release Date:Sep 1995 - 27 - W83787IF REMARKS Command codes REMARKS Command codes Head positioned over proper cylinder on diskette REMARKS Command Code Status information about disk drive REMARKS Invalid codes (no operation - FDC goes into standby ...
Page 28
... HDS DS1 DS0 Publication Release Date:Sep 1995 - 28 - W83787IF REMARKS Command codes Sector ID information prior to command execution REMARKS Data compare between the FDD and system Status information after command execution Sector ID information after command execution Revision A1 ...
Page 29
... HDS DS1 DS0 Publication Release Date:Sep 1995 - 29 - W83787IF REMARKS Command codes Sector ID information prior to command execution Data compare between the FDD and system Status information after command execution Sector ID information after command execution Revision A1 ...
Page 30
... Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ 2.3 Register Descriptions There are status, data, and control registers in the W83787IF. The addresses of these registers are defined below: ADDRESS PRIMARY SECONDARY 3F2 372 3F3 373 3F4 374 3F5 375 3F7 377 D5 D4 ...
Page 31
... This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds the media ID, drive type, and floppy boot drive information of the floppy disk drive.If three mode FDD function is enabled (EN3MODE =1 in CR9), the bit definitions are as follows (W83787IF ...
Page 32
... This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. DRIVE SELECTED 0 None Publication Release Date:Sep 1995 - 32 - W83787IF Revision A1 ...
Page 33
... Indicates wrong Cylinder DD (Data error in the Data field the FDC detects a CRC error in the data field 0 No error CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always 0 Publication Release Date:Sep 1995 - 33 - W83787IF Revision A1 ...
Page 34
... US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault Reserved for the hard disk controller x During a read of this register, these bits are in tri-state DSKCHG Publication Release Date:Sep 1995 - 34 - W83787IF DRATE0 DRATE1 Revision A1 ...
Page 35
... Error Register Write-Precomp Sector Count Sector Count Sector Number Sector Number Cylinder LOW Cylinder LOW Cylinder HIGH Cylinder HIGH SDH Register SDH Register Status Register Command Register Alternate Status Fixed Disk Control Digital Input Undefined Publication Release Date:Sep 1995 - 35 - W83787IF = LOW; Revision A1 ...
Page 36
... Edge Toggling to Send (TDSR) (FERI) (TDCD) (CTS) Bit 1 Bit 2 Bit 3 Bit 4 Bit 1 Bit 2 Bit 3 Bit 4 Bit 9 Bit 10 Bit 11 Bit 12 Publication Release Date:Sep 1995 - 36 - W83787IF Data RX Data RX Data Bit 5 Bit 6 Bit 7 TX Data TX Data TX Data Bit 5 Bit 6 Bit ...
Page 37
... Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB) Publication Release Date:Sep 1995 - 37 - W83787IF Revision A1 ...
Page 38
... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) Publication Release Date:Sep 1995 - 38 - W83787IF Revision A1 ...
Page 39
... Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR . Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable CTS, Loopback RI input ( bit 2 of HCR) DCD . Publication Release Date:Sep 1995 - 39 - W83787IF RI Revision A1 ...
Page 40
... Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB) Publication Release Date:Sep 1995 - 40 - W83787IF Revision A1 ...
Page 41
... Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit will be set to a logical interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled Publication Release Date:Sep 1995 - 41 - W83787IF Revision A1 ...
Page 42
... RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) Publication Release Date:Sep 1995 - 42 - W83787IF Clear Interrupt - Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 1 ...
Page 43
... The percentage error for all baud rates, except where indicated otherwise, is 0.16%. 16 Decimal divisor used to Percent error difference generate 16X clock between desired and actual 2304 1536 1047 857 768 384 192 104* 52* 26* 1* Publication Release Date:Sep 1995 - 43 - W83787IF -1. The output frequency 0.18% 0.099 0.53 Revision A1 ...
Page 44
... UARTA and UARTB. When the address of UARTA or UARTB is selected as COM1 or COM3, interrupt requests for the UART are sent out of W83787IF via IRQ4. If the address of UARTA or UARTB is selected as COM2 or COM4, interrupts are sent out via IRQ3. Thus when UARTA is set as COM1, UARTB should not be set as COM3, and vice versa ...
Page 45
... MOB2 WD2 I SLCT OD WE2 O nAFD OD RWC2 I nERR OD NERR2 O nINIT OD DIR2 O nSLIN OD STEP2 Publication ReleaseDate:Sep 1995 - 45 - W83787IF ECP nSTB PD<0:7> nACK 2 BUSY, PeriphAck 2 PEerror, nAckReverse SLCT 2 nAFD, HostAck 1 2 nFault , nPeriphRequest 1 2 nINIT , nReverseRqst 1, 2 nSLIN PIN EXTFDD ATTRIBUTE --- --- --- ...
Page 46
... XD6 I/O PD7 I/O XD7 I nACK I XDRQ I BUSY I XIRQ XA0 I SLCT O XA1 O nAFD O XRD I nERR O XA2 O nINIT O XDACK O nSLIN O TC REGISTER Publication ReleaseDate:Sep 1995 - 46 - W83787IF PIN JOYSTICK ATTRIBUTE MODE JP0 I JP1 I --- I --- I JB0 I JB1 I --- I --- I --- I --- I --- I --- --- ...
Page 47
... Bit 7, 6: These two bits are a logic one during a read. They can be written. Bit 5: Direction control bit TMOUT ERROR SLCT PE ACK BUSY STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR Publication ReleaseDate:Sep 1995 - 47 - W83787IF Revision A1 ...
Page 48
... PD0-PD7 during a write operation. The leading edge of IOW causes PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 c auses an EPP address write cycle to be performed, and the PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Publication ReleaseDate:Sep 1995 - 48 - W83787IF Revision A1 ...
Page 49
... PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 EPP DESCRIPTION Publication ReleaseDate:Sep 1995 - 49 - W83787IF PD2 PD1 PD0 1 1 TMOUT INIT AUTOFD STROBE INIT AUTOFD STROBE PD2 PD1 PD0 PD2 PD1 ...
Page 50
... Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte repeated. Hardware support for compression is optional. For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard. Publication ReleaseDate:Sep 1995 - 50 - W83787IF Revision A1 ...
Page 51
... Data Register R/W 011 ECP FIFO (Address) R All Status Register R/W All Control Register R/W 010 Parallel Port Data FIFO R/W 011 ECP FIFO (DATA) R/W 110 Test FIFO R 111 Configuration Register A R/W 111 Configuration Register B R/W All Extended Control Register DESCRIPTION Publication ReleaseDate:Sep 1995 - 51 - W83787IF FUNCTION Revision A1 ...
Page 52
... Bit 2-0: These three bits are not implemented and are always logic one during a read PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Address or RLE Address/RLE nFault Select PError nAck nBusy Publication ReleaseDate:Sep 1995 - 52 - W83787IF Revision A1 ...
Page 53
... Register A) Mode = 111 This register is a read-only register. When it is read, 10H is returned. This indicates to the system that this is an 8-bit implementation strobe autofd nInit SelectIn ackIntEn Direction Publication ReleaseDate:Sep 1995 - 53 - W83787IF Revision A1 ...
Page 54
... Selects EPP Mode. In this mode, EPP is selected if the EPP supported option is selected intrValue compress empty full service Intr dmaEn nErrIntrEn MODE MODE MODE Publication ReleaseDate:Sep 1995 - 54 - W83787IF . Revision A1 ...
Page 55
... Address or RLE field ecpAFifo dsr nBusy nAck 1 1 dcr cFifo Parallel Port Data FIFO PD5 PD4 PD3 PD2 PError Select nFault 1 Directio ackIntEn SelectIn nInit Publication ReleaseDate:Sep 1995 - 55 - W83787IF D1 D0 NOTE PD1 PD0 autofd strobe 1 2 Revision A1 ...
Page 56
... Requests a byte of data from the peripheral when it is asserted. This signal indicates whether the data lines contain ECP address or data in the forward direction. When in forward direction, normal data are transferred when nAutoFd (HostAck) is high and an 8-bit command is transferred when it is low. Publication ReleaseDate:Sep 1995 - 56 - W83787IF D1 D0 NOTE ...
Page 57
... PeriphAck is low. The most significant bit of the command is always zero. Data Compression The W83787IF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo ...
Page 58
... I/O will empty or fill the FIFO using the appropriate direction and mode. 5.4 Extension FDD Mode (EXTFDD) In this mode, the W83787IF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 5-1 ...
Page 59
... The operation of EXTADP mode is described below: 1. Set the W83787IF to EXTADP mode by programming bit 7 of CR7 as low and bit 3 and bit 2 of CR0 as high and low, respectively. 2. The W83787IF CR2 is an address register that records the address of the extension When the desired address is written into CR2, pins XWR and XRD of the W83787IF will simultaneously go low and the desired address will also appear on the printer data bus PD7-PD0 ...
Page 60
... The W83787IF provides many configuration registers for setting up different types of configurations. After power-on reset, the state of the hardware setting of each pin will be latched by the relevant configuration register to allow the W83787IF to enter the proper operating configuration. To protect the chip from invalid reads or writes, the configuration registers cannot be accessed by the user. To enable the configuration registers to be read and written, first the value 89H/88H must be written to the Extended Functions Enable Register (I/O port address 250H) ...
Page 61
... FADSEL pin. If there is no setting, a default 3F0H-3F7H will be latched by this bit because of the pull-up resistor on the DBENH 0 Selects address range 370H-377H. 1 Selects address range 3F0H-3F7H OCSS0 OCSS1 PRTMODS0 PRTMODS1 FADSEL FDCEN HADSEL IDEEN / FADSEL pin. Publication ReleaseDate:Sep 1995 - 61 - W83787IF Revision A1 ...
Page 62
... Immediate power-down (IPD) state, OSCS2 = 0 When bit and bit 1 is set to 0, the W83787IF will stop its oscillator and enter power-down mode immediately. The W83787IF will not leave the power-down mode until either a system power-on reset from the MR pin or these two bits are used to program the chip back to power-on state. After leaving the power-down mode, the W83787IF must wait 128 mS for the oscillator to stabilize ...
Page 63
... The W83787IF enters this state automatically after the counter described above has counted down. If there is a change in any of the conditions listed above, the W83787IF's clock will be restarted and bits 1 and 0 will be set to (1, 0), i.e., standby for automatic power-down. When the clock is restarted, the chip is ready for normal operation, with no need to wait for the oscillator to stabilize. Example 7.1: Enable IDE (1F0H-1F7H, 3F6H, 3F7H), FDC (3F0H-3F7H) ...
Page 64
... DTRA at power-on setting. If there is no setting, the default is LPT1.) 00 Selects LPT3 address, 3BCH 01 Selects LPT2 address, 278H 10 Selects LPT1 address, 378H 11 Disables parallel port all function modes URAS0 URBS0 URAS1 URBS1 PTRAS0 PTRAS1 Reserved ABCHG Publication ReleaseDate:Sep 1995 - 64 - W83787IF Revision A1 ...
Page 65
... XD1-XD7. After the base address is latched into CR2, a subsequent read/write cycle to this same base address will generate an XRD or XWR signal. If CEA is set to 0, then the W83787IF will compare system addresses SA9-SA3 with EA9-EA3 to generate a compare-equal signal for this read/write command to access the Extension adapter. If CEA is set to 1, then only EA9-EA4 are used in this comparison ...
Page 66
... Refer to the description of CR1 bit Selects COM1 address, 3F8H URAS2 (bit 3): This bit determines the base address of UARTA. 0 Refer to the description of CR1 bit Selects COM2 address, 2F8H SUBMIDI SUAMIDI URBS2 URAS2 GMODS EPPVER GMENL PRTBEN Publication ReleaseDate:Sep 1995 - 66 - W83787IF Revision A1 ...
Page 67
... Puts the game port in power-down mode URAPWD (Bit 5): 0 Supplies power to COMA 1 Puts COMA in power-down mode URBPWD (Bit 4): 0 Supplies power to COMB 1 Puts COMB in power-down mode URBTRI URATRI GMTRI PRTTRI URBPWD URAPWD GMPWD PRTPWD Publication ReleaseDate:Sep 1995 - 67 - W83787IF Revision A1 ...
Page 68
... When 89H is loaded into EFER and 06H is loaded into EFIR, the CR6 register can be accessed through EFDR. The bit definitions are as follows ECP FTHR0 ECP FTHR1 ECP FTHR2 ECP FTHR3 Reserved Reserved Reserved Reserved Publication ReleaseDate:Sep 1995 - 68 - W83787IF Revision A1 ...
Page 69
... Bit 7: Reserved OSCS2 (Bit 6): This bit and OSCS1, OSCS0 (bit CR0) select one of the W83787IF's power-down functions. Refer to descriptions of CR0. SEL4FDD (Bit 5): Selects four FDD mode 0 Selects two FDD mode (see Table 7-2) 1 Selects four FDD mode DSA , DSB , MOA and MOB output pins are encoded as show in Table 7-3 to select four drives ...
Page 70
... Selects normal mode. When RWC = 0, the data transfer rate is 250 kb/s. When RWC = 1, the data transfer rate is 500 kb/ FDD A type 0 FDD A type 1 FDD B type 0 FDD B type 1 FDD C type 0 FDD C type 1 FDD D type 0 FDD D type 1 Publication ReleaseDate:Sep 1995 - 70 - W83787IF Revision A1 ...
Page 71
... DISFDDWR (Bit 5): This bit enables or disables FDD write data. 0 Enables FDD write 1 Disables FDD write (forces pins WE stay high Floppy Boot Drive 0 Floppy Boot Drive 1 Media ID 0 Media ID 1 SWWP DISFDDWR APDTMS2 APDTMS1 Publication ReleaseDate:Sep 1995 - 71 - W83787IF Revision A1 ...
Page 72
... Media ID 1 Media ID 0 (Bit 3, 2): These two bits hold the media ID bit 1, 0 for three mode Floppy Boot Drive 1 Floppy Boot Drive 0 (bit 1, 0) These two bits hold the value of floppy boot drive 1 and drive 0 for three mode Publication ReleaseDate:Sep 1995 - 72 - W83787IF Revision A1 ...
Page 73
... EFDR. The bit definitions are as follows Notes: PRTMODS2 (Bit 7): This bit and PRTMODS1, PRTMODS0 (bits CR0) select the operating mode of the W83787IF. Refer to the descriptions of CR0. LOCKREG (Bit 6): This bit enables or disables the reading and writing of all configuration registers. 0 ...
Page 74
... PEXTEPP (Bit 2): This bit controls whether the PEXTEN pin is active in EPP mode. 0 PEXTEN is not active in EPP mode 1 PEXTEN is active in EPP mode PEXTECPP PEXT ECP PEXT EPP PEXT ADP PDCACT PDIRHOP PEXT ACT PFDCACT Publication ReleaseDate:Sep 1995 - 74 - W83787IF Revision A1 ...
Page 75
... The Extended Function Enable Register (EFER) enable value is set to 89H. During power-on reset, the default vaule is set by the Pin 41 (GMRD#) pulled high or low. This pin is internal pull-high. Bit 4: Reserved TX2INV RX2INV IDEGIOSEL URIRSEL Reserved HEFERE TURB TURA Publication ReleaseDate:Sep 1995 - 75 - W83787IF Revision A1 ...
Page 76
... GIOSEL (Bit 2): This bit select IDE function or GIO function. 0 Select the IDE pins definition compatible to W83787IF IDE pins definition. 1 Select the W83787IF IDE pins definition and general purpose I/O function. During power-on reset, the default value is set by Pin 91 (HGIOSEL) pulled high or low. This pin is pulled high internally ...
Page 77
... ASK_IR 0 MUX MUX 0 IRMODE1 (CRD.bit1) IRDA MUX 1 MUX IRMODE2 (CRD.bit2) URIRSEL (CRC,bit3) Publication ReleaseDate:Sep 1995 - 77 - W83787IF IRRX high Demodulation into SINB Demodulation into SINB routed to SINB routed to SINB Demodulation into SINB Demodulation into SINB IRRX1 SIN2 01 (default) IRRX2 00 PDCIN IRRX4 ...
Page 78
... GIO0AD10 Reserved Reserved Reserved GIO0 ADR MODE0 GIO0 ADR MODE1 Decode Mode 1 byte decode (Compare GIO0ADR10~0 with SA10~0) 2 bytes decode (Compare GIO0ADR10~1 with SA10~1) 4 bytes decode (Compare GIO0ADR10~2 with SA10~2) 8 bytes decode (Compare GIO0ADR10~3 with SA10~3) Publication ReleaseDate:Sep 1995 - 78 - W83787IF Revision A1 ...
Page 79
... GIO1 ADR MODE1 ~ 0 (Bit7 ~ Bit6): These two bits select address mode. (Defined as following table GIO1AD0 GIO1AD1 GIO1AD2 GIO1AD3 GIO1AD4 GIO1AD5 GIO1AD6 GIO1AD7 GIO1AD8 GIO1AD9 GIO1AD10 Reserved Reserved Reserved GIO1 ADR MODE0 GIO1 ADR MODE1 Publication ReleaseDate:Sep 1995 - 79 - W83787IF Revision A1 ...
Page 80
... Decode Mode 1 byte decode (Compare GIO1ADR10~0 with SA10~0) 2 bytes decode (Compare GIO1ADR10~1 with SA10~1) 4 bytes decode (Compare GIO1ADR10~2 with SA10~2) 8 bytes decode (Compare GIO1ADR10~3 with SA10~ GDA0IPI GDA0OPI GCS0IOW GCS0IOR GIO0 CS TYPE GIOP0MD0 GIOP0MD1 GIOP0MD2 Publication ReleaseDate:Sep 1995 - 80 - W83787IF Revision A1 ...
Page 81
... Active HIGH when (AEN=L) & (IOWN=L or IORN=L) & (SA10~0=GIO0AD10~0). GCS0IOR, GCS0IOW (Bit 3, Bit2): These two bits define GIOP0 Chip Select Active Mode, that is in IORL, or IOWL, or IOR/WN, as shown in the following table. GIOP0 Pin Mode Inactive (tri-state) GIOP0). GIOP0). GIOP0). Publication ReleaseDate:Sep 1995 - 81 - W83787IF Revision A1 ...
Page 82
... When 89H is loaded into EFER and 15H is loaded into EFIR, the CR15 register can be accessed through EFDR. The bit definitions are as follows: Chip Select Pin Type GIOP0 Data Pin Type GIOP0 GIOP0 GIOP0 Publication ReleaseDate:Sep 1995 - 82 - W83787IF SD0, SD0 GIOP0 SD0, SD0, SD0, Revision A1 ...
Page 83
... Active LOW when (AEN=L) & (IOW =L or IOR =L) & (SA10~0=GIO0AD10~0). 1 Active HIGH when (AEN=L) & (IOW =L or IOR =L) & (SA10~0=GIO0AD10~0 GDA1IPI GDA1OPI GCS1IOW GCS1IOR GIO1 CS TYPE GIOP1MD0 GIOP1MD1 GIOP1MD2 GIO1 Pin Mode Inactive (tri-state) GIOP0). GIOP0). GIOP0). Publication ReleaseDate:Sep 1995 - 83 - W83787IF Revision A1 ...
Page 84
... The GIOP1 functions as a data pin, and inverse GIOP1 SD1 GIOP1 The GIOP1 functions as a data pin, and GIOP1 inverse SD1 The GIOP1 functions as a data pin, and inverse GIOP1 inverse SD1 Publication ReleaseDate:Sep 1995 - 84 - W83787IF SD1, SD1, SD1, GIOP1 SD1, GIOP1 Revision A1 ...
Page 85
... SIRRX1 SIRRX0 HDUPLX GIO0AD5 GIO0AD4 GIO0AD3 GIO1AD5 GIO1AD4 GIO1AD3 GIOP0MD0 GIO0CSH GCS0IOR GIOP1MD0 GIO1CSH GCS1IOR Publication ReleaseDate:Sep 1995 - 85 - W83787IF PRTMODS0 APD IPD URAS1 URBS0 URAS0 RA4 RA3 CEA URBS2 SUAMIDI SUBMIDI GMTRI URATRI URBTRI ECPTHR2 ECPTHR1 ECPTHR0 IDEPWD ...
Page 86
... V S OUT 0 OUT - all outputs OL 2 all outputs Publication ReleaseDate:Sep 1995 - 86 - W83787IF CONDITIONS (other pins (other pins HEAD , = Revision A1 ...
Page 87
... MIN. TYP. MAX. (NOTE 360/570 /675 360/570 /675 260/430 /510 0 0 Publication ReleaseDate:Sep 1995 - 87 - W83787IF UNIT TEST CONDITIONS 100 100 100 Revision A1 ...
Page 88
... MAX. (NOTE 1) 6/12 /20/24 135/220 /260 1.8/3/3.5 0.5/0.9 /1.0 1.0/1.6 /2.0 24/40/48 6.8/11.5 7/11.7 7.2/11.9 /13.8 /14 /14.2 Note 2 Note 2 Note 2 100/185 125/210 150/235 /225 /250 /275 100/138 125/210 150/235 /225 /250 /275 SYMBOL Publication ReleaseDate:Sep 1995 - 88 - W83787IF UNIT TEST CONDITION MAX. UNIT Revision A1 ...
Page 89
... SYM. MIN. TYP. MAX. tx1 50 tx2 50 tx3 50 tx4 0 tx5 50 tx6 50 tx7 50 tx8 50 Publication ReleaseDate:Sep 1995 - 89 - W83787IF UNIT TEST CONDITIONS Baud Rate 100pF Loading S Baud Rate nS 100pF Loading Baud Rate Baud Rate nS 100pF Loading nS 100pF Loading 100pF Loading nS 100pF Loading ...
Page 90
... Publication ReleaseDate:Sep 1995 - 90 - W83787IF MAX. UNIT 100 105 nS 300 nS 105 nS UNIT 160 185 nS 190 180 ...
Page 91
... Publication ReleaseDate:Sep 1995 - 91 - W83787IF UNIT 195 nS 180 UNIT ...
Page 92
... SYMBOL MIN. MAX 200 t6 80 200 Publication ReleaseDate:Sep 1995 - 92 - W83787IF UNIT UNIT UNIT UNIT Revision A1 ...
Page 93
... T2 104 T2 208 T2 416 SYMBOL MIN. TYP. T1 1.4 1.6 T1 1.4 3.22 T1 1.4 4.8 T1 1.4 9.7 T1 1.4 19 8. 104 T2 208 T2 416 Publication ReleaseDate:Sep 1995 - 93 - W83787IF MAX. UNIT 2.71 S 3.69 S 5.53 S 11.07 S 22.13 S 44.27 S 88. MAX. UNIT 2.71 S 3.69 S 5.53 S 11.07 S 22.13 S 44.27 S 88. Revision A1 ...
Page 94
... Modulated Output ON Modulated Output OFF Modulated Output ON Modulated Output OFF SYMBOL MIN. TYP 0.8 1 SYMBOL MIN. TYP 0.8 1 Publication ReleaseDate:Sep 1995 - 94 - W83787IF MAX. UNIT S S 1.2 S 1.2 S 1.2 S 1.2 S MAX. UNIT S S 1.2 S 1.2 S 1.2 S 1.2 S Revision A1 ...
Page 95
... TMW(IOW) TMR(IOR) WD TRA TDH TDF INDEX TR TC TWA TWW TWD TDW RESET TWI DIR TMCY TAA TDST TSTP TMRW STEP Publication ReleaseDate:Sep 1995 - 95 - W83787IF Write Date TWDD Index TIDX TIDX Terminal Count TTC Reset TRST Drive Seek operation TSTD TSC Revision A1 ...
Page 96
... THRS > < IRQ3 or IRQ4 THR < > IOW < > TSI (WRITE THR) IOR (READ TIR Receiver Timing DATA BITS (5-8) PARITY STOP TSINT > < Transmitter Timing DATA (5-8) PARITY STOP (1-2) > THR > < Publication ReleaseDate:Sep 1995 - 96 - W83787IF TRINT > < STAR TSTI < TIR < > Revision A1 ...
Page 97
... TRIM ¢x ¢x ¢x ¢x ¢ Printer Interrupt Timing ¡ ö TLAD ¢x ¢x ¢x ¢ ¢x ¢x Publication ReleaseDate:Sep 1995 - 97 - W83787IF ¢x ¢x ¢x ¡ ÷ ¡ ö TMWO ¢x ¢ ¢x ¢x ¢x ¢x ¢ ¢x ¢x ¢x ¢x ¢ ...
Page 98
... Parallel Port 9.4.1 Parallel Port Timing IOW INIT,STROBE AUTOFD, SLCTIN PD<0:7> ACK t2 IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) IRQ Publication ReleaseDate:Sep 1995 - 98 - W83787IF Revision A1 ...
Page 99
... EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 ADDRSTB t24 DATASTB WAIT t18 t19 t25 t27 t26 Publication ReleaseDate:Sep 1995 - 99 - W83787IF t15 t20 t28 Revision A1 ...
Page 100
... EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW IOCHRDY t9 t10 t11 WRITE t13 PD<0:7> DATAST ADDRSTB WAIT t22 PBDIR t15 t16 t17 t18 t19 t21 t20 Publication ReleaseDate:Sep 1995 - 100 - W83787IF t6 t12 t14 Revision A1 ...
Page 101
... EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 ADDRSTB t24 DATASTB WAIT t18 t19 t25 t27 t26 Publication ReleaseDate:Sep 1995 - 101 - W83787IF t15 t20 t28 Revision A1 ...
Page 102
... EPP Data or Address Write Cycle (EPP Version 1.7) A10-A0 SD<0:7> t1 IOW IOCHRDY t9 t10 t11 WRITE t13 PD<0:7> DATAST ADDRSTB WAIT 9.4.6 Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY t15 t16 t17 t18 t19 t20 >| > t6 >| Publication ReleaseDate:Sep 1995 - 102 - W83787IF t6 t22 t22 t4 >| >| t5 >| Revision A1 ...
Page 103
... ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE t5 BUSY 9.4.8 ECP Parallel Port Reverse Timing PD<0:7> t1 nACK t5 nAUTOFD Publication ReleaseDate:Sep 1995 - 103 - W83787IF Revision A1 ...
Page 104
... Extension Adapter Mode Command Cycle IOR IOW XRD XWR tx1 SA<0:2> XA<0:2> tx2 XD<0:7> 9.4.10 Extension Adapter Mode Interrupt Cycle XIRQ IRQ7 9.4.11 Extension Adapter Mode DMA Cycle XDRQ tx6 DRQX DACKX XDACK TC XTC tx3 tx5 tx7 tx8 Publication ReleaseDate:Sep 1995 - 104 - W83787IF tx4 Revision A1 ...
Page 105
... IRRXn: CR0C.bit0 (TX2INV active low. 9.4.13 IrDA Transmit Timing SOUTB IRTXn IRTXn Notes: 1. IRTXn: CR0C.bit1 (RX2INV active high (default). IRTXn: CR0C.bit1 (RX2INV active low Publication ReleaseDate:Sep 1995 - 105 - W83787IF Revision A1 ...
Page 106
... Notes: 1: Receive 500KHZ Pulse Detection Criteria: A received pulse is detected if the received pulse is minimum of 0 IRTXn: CR0C.bit0 (TX2INV active high (default). IRTXn: CR0C.bit0 (TX2INV active low Publication ReleaseDate:Sep 1995 - 106 - W83787IF Revision A1 ...
Page 107
... PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram JP 13A DCH2 34 HEAD2 32 RDD2 30 WP2 28 TRK02 26 WE2 24 WD2 22 STEP2 20 DIR2 18 MOB2 16 14 DSB2 12 10 IDX2 RWC2 2 EXT FDC Publication ReleaseDate:Sep 1995 - 107 - W83787IF Revision A1 ...
Page 108
... VDD 1,8,9, GND 4,5, 81K 81K Joystick 15-pin connector Publication ReleaseDate:Sep 1995 - 108 - W83787IF Printer Port 25-pin Connector 1,14,15,16,17 18~ Revision A1 ...
Page 109
... Dimension b does not include dambar protrusion/intrusion Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec Detail F Publication ReleaseDate:Sep 1995 - 109 - W83787IF DSA DSB DSC DSD MOA MOB MOC MOD Dimension in inches Dimension in mm Min. Nom. Max. Min. ...
Page 110
... Differences between W83877 and W83787IF eature rief W83877: W83777F + Dummy Plug and Play + IR W83787IF: W83787F + IR D escription Illustrates the pins that have different functionality on the W83787F, W83787IF and the W83877F. The following table lists the pins that differ. Pin W83787F/777F 1 nRESIDE 2 PDBDIR/nFDCEN 3 ...
Page 111
... Pin 94-95: They can be programmed by CR0D register as input/output pin IRRX4/IRTX3 for serial infrared communication. Pin 96: During power-on reset, if Pin #91GIOSEL =0, this pin act as IDED7. If GIOSEL =1, this pin act as GIO1 (General Purpose I/O). 877/787I APN 2 W83787IF same as 787 nDACK_B same as 787 IRQ_F same as 787 ...
Page 112
... The default value of URIRSEL is dependent on pin 92 at power on setting bit 2: GIOSEL = 0 select the IDE pins definition compatible to W83787F IDE pins definition. =1 select the W83787IF IDE pins definition and general purpose I/O function. The default value of GIOSEL is dependent on pin 91 at power on setting. bit 1: RX2INV =0 the SINB pin of UART B function or IRRX pin of IR function in normal condition. ...
Page 113
CR0D bit 7: SIRTX1 => IRTX pin selection bit 1 bit 6: SIRTX0 => IRTX pin selection bit 0 SIRTX1 SIRTX0 IRTX output on pin bit 5: SIRRX1 => IRRX pin selection ...
Page 114
CR11: bit 3 - bit 0: GIO0AD10 - GIO0AD8 => GIOP0 (pin 92) address bit 10 - bit 8 bit 5- bit 3 : Reversed bit 7 - bit 6: G0CADM1 - G0CADM0 => GIOP0 address bit compare mode selection ...
Page 115
X bit 4: GIO0CSH =0 the Chip Select pin will active LOW when (AEN=L) AND (SA10-0 = GIO0AD10-0) OR (NIOR=L) OR (NIOW=L) =1 the Chip Select pin will active HIGH when (AEN=L) AND (SA10-0 = GIO0AD10-0) OR (NIOR=L) OR ...
Page 116
X bit 4: GIO1CSH =0 the Chip Select pin will active LOW when (AEN=L) AND (SA10-0 = GIOAD10-0) OR (NIOR=L) OR (NIOW=L) =1 the Chip Select pin will active HIGH when (AEN=L) AND (SA10-0 = ...
Page 117
... B. W83877F Configuration Register CR0D ~ CR15 Same as W83787IF CR1E This register is used to select the base address of Game Chip Select Decoder (GAMECS) from 100H - 3F0H on 16-byte boundries. The default value is 81H. NCS=0 and A10=0 are required to qualify the GAMECS output. bit 7 - bit 2: match A[9:4]. ...
Page 118
CR22 This register is used to select the base address of the IDE Interface Alternate Status Register from 106H - 3F6H on 16-byte boundries + 6. The default value is FDH. NCS=0 and A10=0 are required to access the IDE ...
Page 119
CR26 This register is used to select DMA resources for the FDC (bits and the parallel port (bits 3 - 0). Any unselected DMA is in tristate. The default value is 23H. bit 7- bit4, bit 3 ...
Page 120
... W83787IF Application Note 4 Aug 9, 1995 How to test IR function in 787IF very easy to test the IR Function within the 787IF. I suggest some methods to test it, you can follow below steps you only have an old board with 787F, you can mount 787IF to this old board, i.e., 787IF is pin to pin compatible with 787F ...
Page 121
... If you use Trasxit or another application tools which support IR function, you must set the operation. Introduction of SELFTIR.EXE The program is self-test W83787IF IR function in the full duplex which is similar to UART loopback function. If you have no IR module, you still to test the IR function. As follows, we show the procedure of this program. 787I APN 4 // First you must set Baud rate in COMB ...
Page 122
Configuration Register of IR (CR0C) (B).Set IR Pin Assignment (CR0D) (A).Set Low Baud Rate (2400 bps) (B).Sequence output data 0~255 and (A).Set Mid. Baud Rate (19200 bps) (B). Test method is same as 2400 bps. (A).Set the highest Baud ...
Page 123
Command usage DOS prompt, type SELFTIR <IRTX> <IRRX> 2. Put on the IR module or short the terminal of IRTX and IRRX Press any key to continue. Example: Use Pin94 and Pin95 as IRTX and IRRX respectively, then ...