M5M44265CTP-6S Mitsumi Electronics, Corp., M5M44265CTP-6S Datasheet

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M5M44265CTP-6S

Manufacturer Part Number
M5M44265CTP-6S
Description
Manufacturer
Mitsumi Electronics, Corp.
Datasheet
1.M5M44265CTP-6S.pdf (31 pages)

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
M5M44265CTP-6S
Manufacturer:
MIT
Quantity:
416
1
DESCRIPTION
Microcomputer memory, Refresh memory for CRT, Frame Buffer
memory for CRT
This is a family of 262144-word by 16-bit dynamic RAMs with
Hyper Page mode fuction, fabricated with the high performance
CMOS process, and is ideal for the buffer memory systems of
personal computer graphics and HDD where high speed, low
power dissipation, and low costs are essential.
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application.
512 cycles every 8.2ms.
FEATURES
PIN DESCRIPTION
XX=J,TP
APPLICATION
This device has 2CAS and 1W terminals with a refresh cycle of
Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
Operating power dissipation
Self refresh capability*
Extended refresh capability
Hyper-page mode (512-column random access), Read-modify-
write, RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A
512 refresh cycles every 128ms (A
Byte or word control for Read/Write operation (2CAS, 1W type)
*
M5M44265CXX-5,-5S
M5M44265CXX-6,-6S
M5M44265CXX-7,-7S
UCAS
DQ
RAS
LCAS
W
OE
V
The use of double-layer metalization process technology and a
A
V
Pin name
: Applicable to self refresh version (M5M44265CJ,TP-5S,-6S,-7S
CC
0
SS
Type name
CMOS Input level
CMOS Input level
M5M44265Cxx-5,-5S
M5M44265Cxx-6,-6S
M5M44265Cxx-7,-7S
Self refresh current
Extended refresh current
: option) only
~A
1
~DQ
8
16
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
Upper byte control
column address strobe input
(max.ns)
access
RAS
time
70
50
60
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Function
(max.ns)
access
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAS
time
13
15
20
0
(max.ns)
0
Address
~A
access
~A
time
25
30
35
8
8
)
)*
(max.ns)
access
time
13
15
20
OE
(min.ns)
Cycle
130
110
550µW (Max)*
time
5.5mW (Max)
688mW (Max)
605mW (Max)
523mW (Max)
90
150µA (Max)
150µA (Max)
M5M44265CJ,TP-5,-6,-7,
(typ.mW)
dissipa-
Power
625
550
475
tion
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
PIN CONFIGURATION (TOP VIEW)
Outline 44P3W-R (400mil TSOP Nomal Bend)
(5V)V
(5V)V
(5V)V
(5V)V
(5V)V
(5V)V
RAS
DQ4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
RAS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Outline 40P0K (400mil SOJ)
NC
NC
NC
NC
NC
NC
CC
CC
CC
CC
CC
CC
A
A
A
A
W
A
A
A
A
W
1
2
3
4
5
6
7
8
0
1
2
3
1
2
3
5
6
7
8
0
1
2
3
10
11
12
13
14
15
16
17
18
19
20
10
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
-5S,-6S,-7S
MITSUBISHI LSIs
40
39
38
37
36
35
34
33
32
31
30
28
27
26
25
24
23
22
21
44
43
42
41
40
39
38
37
36
35
32
29
28
27
26
25
24
23
MITSUBISHI LSIs
29
31
30
NC: NO CONNECTION
V
V
V
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
A
A
A
A
A
V
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
A
A
A
A
A
SS
SS
SS
SS
8
7
6
5
4
SS
SS
8
7
6
5
4
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
(0V)
(0V)
(0V)
(0V)
(0V)
(0V)

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M5M44265CTP-6S Summary of contents

Page 1

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM DESCRIPTION This is a family of 262144-word by 16-bit dynamic RAMs with Hyper Page mode fuction, fabricated with the high ...

Page 2

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM FUNCTION In addition to Hyper page mode, normal read, write and read- modify-write operations the M5M44265CJ, TP provides a number of Table 1 Input conditions for each mode Operation Lower ...

Page 3

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Supply voltage V CC Input voltage Output voltage O I Output current O Power dissipation P d Operating temperature T opr Storage ...

Page 4

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM CAPACITANCE (Ta=0~70˚ Parameter Symbol Input capacitance, address inputs C I (A) Input capacitance, clock inputs C I (CLK) C Input/Output capacitance, data ports SWITCHING CHARACTERISTICS ...

Page 5

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Hyper-Page Mode Cycles) (Ta=0~70˚C, V =5V±10%, V =0V, unless otherwise noted, see notes 14,15 Symbol t Refresh cycle time REF ...

Page 6

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Write Cycle (Early Write and Delayed Write) Symbol t Write cycle time WC RAS low pulse width t RAS t CAS low pulse width CAS t CAS hold time after ...

Page 7

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hyper Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control Symbol t Hyper page mode read/write cycle time HPC t ...

Page 8

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Timing Diagrams (Note 31) Read Cycle V IH RAS CRP V IH LCAS/UCAS ASR ADDRESS ...

Page 9

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Byte Read Cycle V IH RAS CRP V IH LCAS (or UCAS UCAS (or LCAS ASR ...

Page 10

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Early Write Cycle V IH RAS CRP V IH LCAS/UCAS ASR ADDRESS ...

Page 11

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Byte Early Write Cycle V IH RAS CRP V LCAS IH (or UCAS UCAS (or LCAS ASR ...

Page 12

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Delayed Write Cycle V IH RAS CRP V IH LCAS/UCAS ASR ...

Page 13

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Byte Delayed Write Cycle V IH RAS CRP V IH LCAS (or UCAS UCAS (or LCAS ASR ...

Page 14

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Read-Write, Read-Modify-Write Cycle V IH RAS CRP V IH LCAS/UCAS ASR ...

Page 15

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Byte Read-Write, Read-Modify-Write Cycle V IH RAS CRP V LCAS IH (or UCAS UCAS (or LCAS ASR ...

Page 16

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hyper Page Mode Read Cycle V IH RAS CRP V IH LCAS/UCAS ASR V IH ROW ADDRESS ...

Page 17

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hyper Page Mode Byte Read Cycle V IH RAS CRP V LCAS IH (or UCAS UCAS (or LCAS ASR V ...

Page 18

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hyper Page Mode Early Write Cycle V IH RAS CRP V IH LCAS/UCAS ASR V IH ROW ADDRESS V IL ...

Page 19

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hyper Page Mode Byte Early Write Cycle V IH RAS CRP V IH LCAS (or UCAS UCAS (or LCAS ASR ...

Page 20

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hyper Page Mode Read-Write, Read-Modify-Write Cycle V IH RAS CRP V IH LCAS/UCAS ASR ADDRESS ...

Page 21

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hyper Page Mode Byte Read-Write, Read-Modify-Write Cycle V IH RAS CRP V IH LCAS (or UCAS UCAS (or LCAS ASR ...

Page 22

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hyper Page Mode Mix Cycle ( RAS CRP V IH LCAS/UCAS ASR V IH ROW ADDRESS V IL ...

Page 23

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hyper Page Mode Mix Cycle ( RAS LCAS/UCAS ...

Page 24

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hyper Page Mode Read Cycle (Hi-Z control by OE RAS CRP V IH LCAS/UCAS ASR V IH ROW ...

Page 25

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hyper Page Mode Read Cycle (Hi-Z control RAS CRP V IH LCAS/UCAS ASR V IH ROW ...

Page 26

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM RAS-only Refresh Cycle V IH RAS CRP V IH LCAS/UCAS ASR ...

Page 27

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM CAS before RAS Refresh Cycle, Extended Refresh Cycle RAS RPC V IH LCAS/UCAS CPN ...

Page 28

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 32 RAS CRP V IH LCAS/UCAS ASR ADDRESS ...

Page 29

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM * Self Refresh Cycle (Note 30 RAS RPC V IH LCAS/UCAS CPN ...

Page 30

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM Note 30 : Self refresh sequence Two refreshing methods should be used properly depending on the low pulse width ( RAS signal during self refresh RASS period. 1. ...

Page 31

EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM 2. Burst refresh during Read/Write operation (A) Timing diagram Read / Write RAS first refresh cycles Table 3 Read / Write Read / Write Cycle Self Refresh CBR burst t ...

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