W921E400A Winbond, W921E400A Datasheet
W921E400A
Related parts for W921E400A
W921E400A Summary of contents
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... Normal/Special function selection of I/O...................................................................................14 6.5.2 Pull High and Open Drain Control of I/O ..................................................................................15 6.6 Serial Port ..........................................................................................................................................18 6.7 DTMF Generator................................................................................................................................20 6.8 Beep Tone Generator ........................................................................................................................22 6.9 Comparator........................................................................................................................................22 6.10 Timer/Counter ..................................................................................................................................24 6.10.1 TM0.......................................................................................................................................24 6.10.2 TM2.......................................................................................................................................26 6.10.3 TM3.......................................................................................................................................28 6.10.4 Arbitrary Waveform Generator ...............................................................................................29 6.11 Interrupt............................................................................................................................................30 6.11.1 Interrupt Control Register.......................................................................................................30 6.11.2 Interrupt Enable Flag .............................................................................................................31 W921E400A/W921C400 4-BIT MICROCONTROLLER Publication Release Date: July 1998 - 1 - Revision A3 ...
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... RAM Addressing Mode ......................................................................................................................42 9.2.1 Direct Addressing Mode: (2 words/2 cycles) .............................................................................43 9.2.2 Indirect Addressing Mode: (1 word / 1 cycle) ............................................................................43 9.2.3 Working Register Addressing Mode: (1 word / 1 cycle).............................................................43 9.3 Look-up Table Addressing Mode (1 word/2 cycles) ...........................................................................43 10. INSTRUCTION CODE MAP ...................................................................................................................45 11. INSTRUCTION SET SUMMARY ............................................................................................................48 12. PACKAGE DIMENSIONS........................................................................................................................52 28-pin DIP .................................................................................................................................................52 28-pin SOP ...............................................................................................................................................52 W921E400A/W921C400 - 2 - ...
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... I/O port and built in four by one channel comparator circuit, thus it can be easily implemented as telephone processor. Using the serial transmit/receive function, the W921E400A/W921C400 series can interface with Winbond LCD driver IC by the serial control circuit. There are also seven interrupt sources and 48-level subroutine nesting for interrupt applications ...
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... STOP mode: No operation including oscillator Addressing Mode ROM: Indirect call addressing mode Long jump/call addressing mode RAM: Direct addressing mode Indirect addressing mode Working register addressing mode Look-up table addressing mode Instruction Sets 117 instruction sets Package Type 28-pin DIP, 28-pin SOP W921E400A/W921C400 - 4 - ...
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... P3.1/ANI1 P3.2/ANI2 P3.3/ANI3 P4.2 P4.3/INT0 P5.1/TM2 P6.0/WDATA P6.1/WCLK P6.2/RDATA V SS P6.3/RCLK W921E400A/W921C400 PIN NAME 1 PA.0 2 PA.1 3 PA.2 4 PA.3 5 PB.0 6 PB.1 7 PB.2 8 PB.3 9 BTG 10 DTMF 11 RESET 12 OSCO 13 OSCI W921E400A / W921C400 1 Publication Release Date: July 1999 - 5 - DIP28 (OR SOP28 Revision A3 ...
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... Dual tone multi-frequency output pin BTG O Beep tone generator output pin I Reset input pin with low active RESET V I Positive power supply input pin Negative power supply input pin SS Notes: V open drain option by software K open drain and pull high resistor option by software W921E400A/W921C400 FUNCTION - 6 - ...
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... Counter EPROM Decoder and Control Circuit Stack Pointer OSCI Oscillator and OSCO System Control Prescaler RESET (ANI0 to ANI3 W921E400A/W921C400 Co-V Co-U U Reg. Reg. Reg. B Reg. A Reg. ALU Port Mode RAM Register 512 x 4 Timer 0 Timer 2 Timer 3 MUX + - D/A Convertor D/A MSB D/A LSB ...
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... Priority: Reset > INT0 > TM0 > TM2 > (Comparator/TM3) > P4.2 > Serial Port W921E400A/W921C400 Interrupt Area Indirect Call, Long Call/Jump, Look-up Table Area 4096 x 10-bit JMPL Instruction (Reset) XXXXX XXXXX JMPL Instruction (INT0) XXXXX ...
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... Port P4 Pull High Resistor Register 004H Port P4 Output Type Register 005H Port P6 Pull High Resistor Register 006H Port P6 Output Type Register 007H Port PAB Pull High Resistor Register 008H Port PAB Output Type Register W921E400A/W921C400 000 063 064 079 Stack 080 Register Serial 127 Buffer ...
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... TM0 MSB Data Register 022H TM0 LSB Data Register 023H TM0 Status Register 024H Reserved 025H Reserved 026H Reserved 027H Reserved 028H Reserved W921E400A/W921C400 ABBREVIATION (SRLNR) (SRMNR) (SRSPC) (SRINV) (P2TP) ( P3IO ) ( P4IO ) ( P5IO ) ( P6IO ) (OSCCTR) (DTMF) (RCCTL) (DACTL) (DALSB) (DAMSB) ...
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... The stack pointer will be decreased by 4 when the CALL/CALLP or interrupt is accepted, and will be increased by 4 when the RTN or RTNI instruction is executed. The format of the stack content is shown in the following table. W921E400A/W921C400 ABBREVIATION (TM2CR) ...
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... WRx ANL A, WRx ORL A, WRx XRL A, WRx CMP A, WRx where 6.3 Internal Oscillator Circuit f TM0 OSCI Crystal Type or RC Type OSCO W921E400A/W921C400 Z C PC12 PC11 PC10 PC9 PC8 Stack 1 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Z C PC12 PC11 ...
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... The oscillator configuration is shown as follows. 6.4 Initial State The W921E400A/W921C400 is reset either by a power-on reset or by using the external RESET pin. The initial state of the W921E400A/W921C400 after the reset function is executed is described below. The EVF interrupt request signal register value is random, so user must do CLR EVF,#11111111b instruction to clear all interrupt request signals after power-on reset ...
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... P4.2 to P4.3: Multi-function I/O pins (selected by P4IO register) Normal function I/O pins Special function input pins: (All the pins are falling edge active) P4IO register: (address = 010H, default data = 0H P5.1: Multi-function I/O pins (selected by P5IO register) Normal function I/O pins Special function I/O pins W921E400A/W921C400 Normal I/O P3.0 1: Analog input pin 0 (ANI0) 0: Normal I/O P3.1 ...
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... Pull High and Open Drain Control of I/O Some of the above I/O ports can be controlled with pull-high resistor or open drain by programming the special register. All pull-high resistors of the following table are 400 K reset the following special register will all reset to '0H'. W921E400A/W921C400 b1 b0 Reserved 0: Normal I/O P5 ...
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... P4.2 to P4.3: P4PH register: (address = 003H, default data = 0H P4TP register: (address = 004H, default data = 0H Reserved P6.0 to P6.3: P6PH register: (address = 005H, default data = 0H W921E400A/W921C400 b1 b0 Reserved Reserved 0: P4.2 without pull-high resistor 1: P4.2 with pull-high resistor 0: P4.3 without pull-high resistor 1: P4.3 with pull-high resistor b1 b0 Reserved 0: P4.2 work as CMOS type 1: P4 ...
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... PA, PB: PABPH register: (address = 007H, default data = 0H Reserved Reserved PABTP register: (address = 008H, default data = 0H Reserved Reserved W921E400A/W921C400 P6.0 work as CMOS type 1: P6.0 work as open-drain type 0: P6.1 work as CMOS type 1: P6.1 work as open-drain type 0: P6.2 work as CMOS type 1: P6.2 work as open-drain type 0: P6 ...
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... Reserved Reserved 6.6 Serial Port The W921E400A/W921C400 has a clock-synchronous serial interface which transmits and receives 8-bit data as default. User can program the P6IO register to select port P6 as the serial port. The serial transmitter/receiver function can be operated with multi-nibble function and the LSB of every nibble is transmitted/received first ...
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... I/O Buffer Serial Buffer Registers 050H The internal serial clock can be controlled by the serial clock speed control register (SRSPC) and the format is as follows: W921E400A/W921C400 b0 0: Serial data latch at WCLK/RCLK rising edge (normal high) 1: Serial data latch at WCLK/RCLK falling edge (normal low) ...
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... DTMF Generator There is one dual tone multi-frequency (DTMF) generator channel in this chip. The correct DTMF output frequency is decided by the OSCCTR register as shown below. OSCCTR register: (address = 013H, default data = 0H Reserved W921E400A/W921C400 ...
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... The output frequency of the row and column will be controlled by the row/column frequency control register (RCCTL). RCCTL register: (address = 015H, default data = 0H Reserved The following table shows the DTMF keypad and its frequency W921E400A/W921C400 Function Description Row frequency disable 1: Row frequency enable 0: Column frequency disable 1: Column frequency enable 0: ...
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... Reserved If the Beep Tone Generator is disabled by setting bit3 of the BTGR register to zero or after power on reset, the BTG output pin will remain in high state. 6.9 Comparator ANI3 ANI2 ANI1 ANI0 Vrang = 1 (2/3)V 8bit D/A Converter DAMSB 4-bit Register W921E400A/W921C400 ...
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... The power source of the D/A converter can be selected from the (2/3)V the DACTL register bit2. D/A Converter LSB Data Register DALSB register: (address = 017H, default data = 0H D/A Converter MSB Data Register DAMSB register: (address = 018H, default data = 0H W921E400A/W921C400 Reserved ...
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... Watch-dog timer System f SYS 11-bit Prescaler Clock 1/4 TM0 Control High Speed Register Clock W921E400A/W921C400 Compare stop 1: Compare start 0: Vneg = Vref; Vpos = Vani 1: Vneg = Vani; Vpos = Vref (Read Only) 0: Vpos voltage < Vneg voltage 1: Vpos voltage >= Vneg volatge Must be set value "1" ...
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... STTM0 bit1. The WDT (STTM0 bit1) will be reset to zero only with power on reset or RAM write mode. In the timer mode the time out will be the programming data subtract 1 ([TM0MSB, TM0LSB]-1). TM2 and TM3 are the same as TM0. W921E400A/W921C400 ...
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... SYS System 11-bit Prescaler Clock 1/4 High Speed Clock TM2 Control Period/Pulse Width Port 5.1 Measurement TM2CR register: (address = 02AH, default data = 0H W921E400A/W921C400 f TM2 Read TM2 Register 8 Order Divider Register TM2 Set Register (8 bits) TM2 Control Logic Input frequency (f ...
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... When the TM2 normal function is performed, the special function will be disabled automatically. The format of the TM2 trigger condition register (TGTM2) is shown below: TGTM2 register: (address = 02EH, default data = 0H W921E400A/W921C400 TM2 normal function selected 1: Special function selected Reserved ...
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... TM3CR register: (address = 02FH, default data = 0H The TM3 set register is divided into TM3 MSB data register (TM3MSB register, address = 030H, default = 0FH) and TM3 LSB data register (TM3LSB register, address = 031H, default = 0FH). W921E400A/W921C400 the number of interrupt flag occurs, 255 ( N ...
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... The TM2 have the arbitrary waveform generator circuit. It has function as the following description. Type will keep the waveform in the high state Type will keep the waveform in the low state Note the value stored in the TM2 Set Reg. (TM2MSB, TM2LSB) W921E400A/W921C400 Reserved Reserved ...
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... There are seven interrupt W921E400A/W921C400. All the pins of external sourcesÄINT0 (P4.3) and port P4.2Äare falling edge active. The priority of those interrupts is INT0 > TM0 > TM2 > ( Comparator / TM3 ) > P4.2 > SERIAL. 6.11.1 Interrupt Control Register Which interrupt is enabled is controlled by the interrupt control register1 to 3 (INTCT1 to INTCT3). ...
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... All functions works well and the C operates according to the clock generated by the system clock. 6.12.2 Hold Mode: In hold mode, all operations of C cease, except for the operation of the oscillator, timer/counter, serial port and interrupt active pins. The C enters hold mode when the HOLD instruction is executed. W921E400A/W921C400 ...
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... HMRF2 register: (address = 037H, default data = 0H Reserved HMRF3 register: (address = 038H, default data = 0H Reserved W921E400A/W921C400 TM0 hold released disable 1: TM0 hold released enable Reserved 0: TM2 hold released disable 1: TM2 hold released enable 0: TM3 hold released disable 1: TM3 hold released enable ...
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... Flag Set? Yes Reset ENINT Flag and Individual Request Flag Execute Interrupt Service Routine Hold note the corresponding flag bit of interrupt enable or hold mode release register W921E400A/W921C400 TM0, TM2, TM3 Serial; Comparator; Falling change occurs at INT0, P4 Yes Hold Mode? ...
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... The C enters the stop mode only when the STOP instruction is executed. Because the oscillator is stopped, all functions in this chip are stopped. The stop mode can be released by the RESET pin, INT0, P4.2, PA port or PB port. The stop condition release flag (STPRF, address = 035H) is the stop mode release control register. W921E400A/W921C400 Hold was released by TM0 ...
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... The control flow chart is shown below: Stop mode operation flow chart PC (PA, PB Ports on low level state W921E400A/W921C400 b0 0: Stop released by any pin disable 1: Stop released by any pin enable 0: Stop released by any pin disable 1: Stop released by any pin enable 0: Stop released by P4 ...
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... Initial Condition Register of EPROM Program Method There is one 4-bit of the initial condition register (not part of the RAM) in W921E400A to control the micro-controller initial status after power-on. The format is described as following: INI register: (initial value = 0FH 6.14 Reset The W921E400A/W921C400 provides two reset methods, pull low RESET pin and watch dog timer reset ...
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... Input/Output Voltage Power Dissipation Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 8. ELECTRICAL CHARACTERISTICS 8.1 DC Characteristics W921E400A EPROM TYPE ( 3.0V 4.0 MHz all outputs unloaded OSC ...
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... W921E400A EPROM Type DC Characteristics, continued PARAMETER SYMBOL Hold Mode Current I HM1 I HM2 I HM3 Stop Mode Current I SM1 I SM2 I SM3 Input High Voltage V IH Input Low Voltage V IL Output High Voltage V OH Output Low Voltage V OL1 V OL2 Input Leakage Current V IL DTMF Output DC Level ...
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... OL2 Input Leakage Current V IL DTMF Output DC Level V TDC DTMF Distortion THD DTMF Output Voltage V TO Pre-emphasis D/A DC Reference V REF Voltage D/A Resolution Voltage V RSL W921E400A/W921C400 CONDITIONS MIN. 4 MHz 2 MHz 400 KHz 4 MHz MHz DD 400 KHz 4 MHz MHz DD 400 KHz V = 3V, F ...
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... AC Characteristics W921E400A EPROM TYPE ( 3.0V 4.0 MHz all outputs unloaded OSC A PARAMETER SYMBOL F F Operating Frequency Instruction Cycle Time Serial Port Data Ready T Time Serial Port Data Hold T Time T RESET Active Width ROW 1 Frequency F ROW1 (697 Hz) ROW 2 Frequency F ROW2 ...
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... Serial Port Data Hold Time RESET Active Width ROW 1 Frequency (697Hz) ROW 2 Frequency (770 Hz) ROW 3 Frequency (852 Hz) ROW 4 Frequency (941 Hz) COL 1 Frequency (1209 Hz) COL 2 Frequency (1336 Hz) COL 3 Frequency (1477 Hz) COL 4 Frequency (1633 Hz) Oscillator Start Time W921E400A/W921C400 SYM. CONDITIONS F OSC1 F OSC2 F OSC3 OSCI, OSCO ...
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... Instruction: CALL, JMPL, JB0, JB1, JB2, JB3, JC, JNC, JZ, JNZ 9.2 RAM Addressing Mode There are three types of RAM addressing mode in this chip: Direct addressing mode Indirect addressing mode Working register addressing mode W921E400A/W921C400 Register PC b11 b10 ...
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... Instruction: MOV A, WRn; MOV WRn, A; ..., etc. 9.3 Look-up Table Addressing Mode (1 word/2 cycles) There is one special function look-up table addressing mode in this chip, the instruction is TBL I and the function is shown in the following table. W921E400A/W921C400 ...
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... MOV A, #03H MOV B, #01H TBL 02H . . . ORG 213H DC 3DCH . . . W921E400A/W921C400 register A register b11 b10 OP2 OP1 ROM Code Output to Register or Port ...
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... MOV @M, A MOV @ MOV MOV MOV 1W/1C 2W/2C Undecided W921E400A/W921C400 SRL A MOV A, V MOV A, U INC B ADD A, Mx SRH A INC DP ADC A, Mx SLL A DEC B SUB A, Mx SLH A DEC DP SBC A, Mx ANL A, Mx ...
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... LSB MSB JB0 9 JB2 JMPL 1W/1C 2W/2C Undecided W921E400A/W921C400 MOV PMx, #I JB1 JB3 JNC JNZ CALL CALLP TBL 1W/2C 1W/3C 2W/3C 3W/ ...
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... ADD A, WRn 5 SUB A, WRn 6 ANL A, WRn 7 XRL A, WRn 1W/1C 2W/2C Undecided W921E400A/W921C400 MOV A, #I MOV B, #I MOV Mx, #I MOV @M, #I ADC A, WRn SBC A, WRn ORL A, WRn CMP A, WRn MOV A, WRn MOV A, Px MOV B, WRn MOV B, Px ...
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... ORL A, WRx 00 0101 1011 ORL 0110 1010, xxxxxxxxxx XRL 0111 XRL A, WRx 00 0110 1011 XRL 0111 1010, xxxxxxxxxx CMP 0111 CMP A, WRx W921E400A/W921C400 Function WRx ...
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... MOV @ 1000 nnnn MOV A, WRn 11 1001 xxxx MOV 1010 nnnn MOV B, WRn 11 1011 xxxx MOV 1100 nnnn MOV WRn 1101 nnnn MOV Px 1110 xxxx MOV WRn, B W921E400A/W921C400 Function ...
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... JNC addr 10 1011 00aa, aaaaaaaaaa JZ addr 10 1011 10aa, aaaaaaaaaa JNZ addr 10 1100 00aa, aaaaaaaaaa JMPL addr 10 1100 10aa, aaaaaaaaaa CALL addr 10 1101 aaaa CALLP addr 10 1110 aaaa TBL addr *1: Depends on the SRMNR, SRLNR register W921E400A/W921C400 Function ...
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... MOV DP 0111 1101 XCH 0110 1101 XCH 0100 1101 XCH A, B * *@ *@Addr = { target address for the CALLP instruction W921E400A/W921C400 Function Status W/C Memo Stack PC Stack PC ...
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... PACKAGE DIMENSIONS 28-pin DIP 28-pin SOP Seating Plane W921E400A/W921C400 Base Plane A Seating Plane Detail See Detail Dimension in Inches ...
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... No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. W921E400A/W921C400 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U ...