CXA3026AQ Sony, CXA3026AQ Datasheet
CXA3026AQ
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CXA3026AQ Summary of contents
Page 1
... Flash A/D Converter Description The CXA3026AQ is an 8-bit high-speed flash A/D converter capable of digitizing analog signals at the maximum rate of 140MSPS. ECL, PECL or TTL can be selected as the digital input level in accordance with the application. The TTL digital output level allows 1: 2 demultiplexed output. ...
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... V DGND3 – 1.05 DGND3 – 0 DGND3 – 3.2 DGND3 – 1.4 IL /T, INV 2 DGND1 IL /E – N/E|) 0.4 0.8 100 140 –20 VID —2— CXA3026AQ Unit °C W Max. Min. Typ. Max. +5.25 +4.75 +5.0 +5.25 +0.05 –0. ...
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... CC INV 6bits 8bits 6bits 8bits 6bits 6bits Delay D Q Select SELECT DGND1 DGND2 —3— CXA3026AQ DGND3 12 (MSB) P1D7 40 P1D6 39 P1D5 38 P1D4 37 P1D3 36 P1D2 35 P1D1 34 P1D0 33 (LSB) (MSB) P2D7 28 P2D6 27 P2D5 26 P2D4 25 P2D3 ...
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... Reset input. When the input is set to low level, the built-in CLK frequency divider circuit can be reset RESETN/E complementary input. EE When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. —4— CXA3026AQ Description ...
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... Data output polarity inversion input. When left open, this input goes to high level. 44 (See Table 1. I/O Correspondence Table.) DGND1 Data output mode selection. (See Table 2. Operating Mode 45 Table.) DGND1 —5— CXA3026AQ Description ...
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... Comparator Analog input. Vref 6 AGND Port 1 side data output CC2 Port 2 side data output DGND2 Clock output DGND1 VEE (See Table 2. Operating Mode Table.) —6— CXA3026AQ Description ...
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... RESETN – CLK RESETN – CLK ( pF) L DMUX mode ( pF pF) L 0 pF) L 0 pF) L —7— CXA3026AQ = ° Min. Typ. Max. Unit 8 bits ±0.5 LSB ±0.5 LSB 500 µ ...
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... RB INV —8— CXA3026AQ Min. Typ. Max. Unit 150 MHz –12 TPS ...
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... Taj is: Taj = 8 Latch CLK + Latch 16LSB —9— CXA3026AQ Amp Logic CXA3026AQ Analizer CLK 1024 samples ECL Buffer 129 128 t (LSB) 127 ...
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... Description of Operating Modes The CXA3026AQ has two types of operating modes which are selected with Pin 45 (SELECT). Operating Maximum SELECT mode conversion rate DMUX mode V 140MSPS CC Straight mode GND 100MSPS 1. DMUX mode (See Application Circuit 1– (1), (2) and (3).) Set the SELECT pin to V for this mode ...
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... The A/D converter can operate at Fc (min.) = 100MSPS in this mode. Digital input level and supply voltage settings The logic input level for the CXA3026AQ supports ECL, PECL and TTL levels. The power supplies (DV 3, DGND3) for the logic input block must be set to match the logic input (CLK and EE RESET signals) level ...
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... P2D0 to P2D7 8-bit Digital Data +5V(D) —12— CXA3026AQ 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch ...
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... P1D0 to P1D7 36 8-bit Digital Data +5V(D) —13— CXA3026AQ 8-bit Digital Data Latch 8-bit Digital Data Latch 8-bit Digital Data Latch ...
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... Short the analog system and digital system at one point immediately under the A/D converter. See the Notes on Operation. is the chip capacitor of 0.1µF. —14— CXA3026AQ RESETN/E RESET/E 47 RESETN/T 46 SELECT 45 INV 44 CLKOUT 43 DV ...
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... Td_clk T_rs N–1 N+1 Tds N T Tpw0 10ns (max.) 2.0V N–4 N–3 N–2 0.8V 2.0V N–5 N–4 N–3 0.8V 8ns (max.) 2.0V 0.8V —15— CXA3026AQ N+6 N+5 N+7 N+4 Tdo2;8ns (typ.) 6.5ns (min.) 10ns (max.) 2.0V N+1 N+3 0.8V 2.0V N N+2 0. Tdo1 T+1ns (typ.) 2.0V 0.8V N+2 N+3 N–1 N N–2 N–1 ...
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... Remark : In the timing chart, the values in the brackets ( ) are included all the temperature change and the power supply variation. Gate Array 8bit Latch 8bit 8bit 8bit 8bit 8bit Td-clk (min) 5.0ns (4.5ns) Td-clk (max) 7.5ns (8.0ns) Tdo2 (min) 7.0ns (6.5ns) Tdo2 (max) 9.5ns (10ns) —16— CXA3026AQ ts (min) th (min) 2.5ns 6.5ns 14ns ...
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... Notes on Operation • The CXA3026AQ is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high-speed operation ...
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... Analog input voltage [V] Current consumption vs. Conversion rate characteristics response 170 160 150 140 130 – Conversion rate [MSPS] Reference current vs. Ambient temperature characteristics –25 Ta—Ambient temperature [°C] —18— CXA3026AQ f CLK fin= –1kHz 4 DMUX mode C 5pF L= 70 140 25 75 ...
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... Error>16LSB –9 Error rate: 10 TPS 160 150 140 –25 25 Ta—Ambient temperature [°C] Error rate vs. Conversion rate characteristics 10 – CLK fin= –1kHz 10 – Error>16LSB 10 – – 9 – 140 Fc–Conversion rate [MSPS] 75 —19— CXA3026AQ 160 180 ...
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... Description The CXA3026AQ Evaluation Board is a special board designed to maximize and facilitate the evaluation performance of the CXA3026AQ. After latching the CXA3026AQ output data with a frequency divided clock, the analog signal can be regenerated by a 10-bit high-speed D/A converter. The latched data can also be extracted externally via a 24-pin cable connector ...
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... CXA3026AQ ...
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... DIR.IN 7. S2: Setting junction for the clock frequency division ratio. The operating speed after latching is determined by the frequency division ratio set here. When set to CLK OUT, it operates according to the CXA3026AQ clock output. 8. SW1 SELECT: CXA3026AQ output mode selector switch. 9. SW2 A/D INV: CXA3026AQ output polarity inversion switch ...
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... In the evaluation board of the CXA3026AQ,CLC404 (Comlinear) is employed for IC2 to drive the analog input signal. Though,CLC505 (Comlinear) can also be used instead of CLC404, there should be a little change in the peripheral circuit in this case. ...
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... P1 side DATA (TTL) CLK Approximately 9.0ns CON7 P1 side DATA N–6 (TTL) DATA N–6 CON4 P1 side OUT (Analog regeneration waveform) Operating Conditions CXA3026AQ operating mode Anaiong S2 setting N N–3 N– –1V : Straight mode : DIR IN pin input : 1/2 frequency divided clock —24— ...
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... P1D3 EE 36 P1D2 35 P1D1 34 1 P1D0 33 DGND2 IC1 CXA3026AQ DGND1 P2D7 28 P2D6 27 P2D5 26 P2D4 C30 0.1µ R28 R29 82 82 R30 82 DGND ...
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... P2D5 13 12 CON8 P2 side DATA P2D4 1 2 P2D3 3 4 P2D2 5 6 P2D1 9 8 P2D0 11 10 IC16 74ALS34 25 26 DGND —26— CXA3026AQ AGND R42 R43 MSB AGND C51 270 0.1µ VREF TL431CP ...
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... R12 R13, 23 33, 37, 38 R14 27 36, 39, 40 FRD-25SR (0.25W) 130 R15, 16, 43, 45 R17 R20, 22, 42, 44 R21 R41 Component side silk diagram —27— CXA3026AQ Product name Function RJ-5W-1K 1k volume resistor RJ-5W-2K 2k volume resistor RJ-5W-10K 10k volume resistor RGLD4X621J 620 network resistor FRD-25SR (0 ...
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... Component side pattern diagram Solder side pattern diagram —28— CXA3026AQ ...
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... This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). 48PIN QFP (PLASTIC 0.15 0.3 – 0.1 ± 0. 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT QFP-48P-L04 LEAD MATERIAL QFP048-P-1212-B PACKAGE WEIGHT —29— CXA3026AQ + 0.1 0.15 – 0.05 0.15 + 0.2 0.1 – 0.1 EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g ...