CXD1176Q Sony, CXD1176Q Datasheet

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CXD1176Q

Manufacturer Part Number
CXD1176Q
Description
8-bit 20MSPS Video A/D Converterwith Clamp Function
Manufacturer
Sony
Datasheet

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Description
for video use that features a sync clamp function. The
adoption of a 2 step-parallel method realizes low
power consumption and a maximum conversion
speed of 20MSPS.
Features
• Resolution power: 8-bit ± 1/2LSB (DL)
• Maximum sampling frequency: 20MSPS
• Low power consumption: 60mW (at 20MSPS typ.)
• Built-in sync type clamp function
• Built-in monostable multivibrator for clamp pulse
• Built-in sync pulse polarity selection function
• Clamp pulse direct input possible
• Built-in clamp ON/OFF function
• Built-in reference voltage self-bias circuit
• Input CMOS compatible
• 3-state TTL compatible output
• Single 5 V power supply
• Low input capacity: 11 pF
• Reference impedance: 330
Applications
Structure
The CXD1176Q is an 8-bit CMOS A/D converter
(Reference current excluded)
generation
TV and VCR digital systems and a wide range of
applications where high-speed A/D conversion is
required.
Silicon gate CMOS IC
8-bit 20MSPS Video A/D Converter with Clamp Function
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
(typ.)
—1—
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage V
• Reference voltage
• Input voltage
• Input voltage
• Output voltage V
• Storage temperature
Recommended Operating Conditions
• Supply voltage AV
• Reference input voltage
• Analog input
• Clock pulse width
• Operating ambient temperature
(Analog)
(Digital)
(Digital)
Tpw
CXD1176Q
1
32 pin QFP (Plastic)
, Tpw
V
V
V
Tstg
DV
| DV
V
V
V
Topr
DD
RT
IN
I
O
RB
RT
IN
DD
DD
, V
0
SS
, AV
, DV
RB
22.5 ns (min) to 1.1 µs (max)
– AV
SS
SS
V
V
V
V
DD
DD
DD
DD
SS
1.8Vp-p above
+ 0.5 to V
+ 0.5 to V
+ 0.5 to V
| 0 to 100
+ 0.5 to V
–55 to +150
4.75 to 5.25
–40 to +85
to 2.7
0 to
7
E90167J04-TE
SS
SS
SS
SS
– 0.5 V
– 0.5 V
– 0.5 V
– 0.5 V
mV
°C
°C
V
V
V
V

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CXD1176Q Summary of contents

Page 1

... Video A/D Converter with Clamp Function Description The CXD1176Q is an 8-bit CMOS A/D converter for video use that features a sync clamp function. The adoption step-parallel method realizes low power consumption and a maximum conversion speed of 20MSPS. Features • Resolution power: 8-bit ± 1/2LSB (DL) • ...

Page 2

... Reference supply Lower encoder Lower sampling (4 BIT) comparator (4 BIT) Lower encoder Lower sampling (4 BIT) comparator (4 BIT) Upper sampling Upper encoder comparator (4 BIT) (4 BIT CLE CCP VREF —2— CXD1176Q VRBS 25 24 VRB AVss 23 22 AVss VRT ...

Page 3

... Pin 14 (sync) as trigger, the monostable multivibrator generates 13 clamp pulses. When SEL is at high, with the rising edge of Pin 14 (sync) as trigger, it generates clamp pulses Trigger pulse input to the monostable multivibrator. 14 Trigger polarity can be selected through Pin 13 (SEL —3— CXD1176Q Description ...

Page 4

... Pin 14 (sync) is fixed DV to either low or high.) SS Analog + When shorted with VRT, generates approx. +2 Reference voltage (top Reference voltage (bottom Analog input AV SS Analog ground AV SS When shorted with VRB, generates approx. +0 —4— CXD1176Q Description ...

Page 5

... By connecting CLE pin to DV several hundred CLAMP SS clamp pulse can be tested. PULSE DV DD When low, Data is output. When high pins 30 turn to high impedance —5— CXD1176Q Description voltage changes are in IN via a DD resistance, the ...

Page 6

... – – 18ns Timing Chart 4.5ns 90% 10% t PZL 1.3V 10% t PZH 90% 1.3V Timing Chart. II —6— CXD1176Q LSB . . . . . . Points where analog signals are sampled ...

Page 7

... Potential difference to VRT Potential difference to VRB +20 End point NTSC 40 IRE mod ramp Fc = 14.3 MSPS V = 0.5 V REF V = DC, IN PWS = 3 µ 2.5 V REF C = 100 pF, 1. 130 k (15 PIN) —7— CXD1176Q = 2 °C) RT Typ. Max. Unit MSPS 0.5 20 MHz 18 –60 –40 –20 mV +40 +60 +0.5 +1.3 LSB ±0.3 ± ...

Page 8

... 4. Conditions with TTL 1 gate and 10pF load —8— CXD1176Q = 0 2 ° Min. Typ. Max. Unit 4.5 6.6 8 230 300 450 0.48 0.52 0.56 1 ...

Page 9

... CX20202A-1 TTL CXD 1176Q ECL 620 –5.2V CLK 0.5V TTL ECL 2. 0. – —9— CXD1176Q Measurement DV DD point To output pin C L includes capacitance of the probe and others. L ERROR RATE H.P.F COUNTER 1 10bit D/A 2 VECTOR SCOPE D.G 620 D.P. –5. ...

Page 10

... Digital output Operation (See Block Diagram and Timing Chart 3) 1. The CXD1176Q is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2 lower comparators groups of 4-bit each. The reference voltage that is equal to the voltage between VRT – VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower data ...

Page 11

... DV DD This is to avoid latch up due to the voltage difference between AV in series between the amplifier output and A/D input. RT pins be the common source of power supply —11— CXD1176Q and RT = 2.6 V and activated. RB high impedance is obtained. DD and DV pins when power is ON. ...

Page 12

... GND (Analog 0.01µ 0.1µ 22 10P 23 0.01µ VREF 0.01µ 20k GND (Analog) —12— CXD1176Q +5V (Digital) 0.1µ GND (Digital) +5V (Digital) 0.1µ ...

Page 13

... GND (Digital) GND (Analog 0.01µ 0.1µ 0.01µ +5V (Digital) GND (Analog) —13— CXD1176Q +5V (Digital) 0.1µ OPEN Clamp Level 6 setting data Latch, Subtracter, 5 Comparator, etc DAC, PWM, etc. +5V (Digital) 0.1µ ...

Page 14

... ADC and DAC Evaluation Board Evaluation boards are available for the high speed, low power consumption CMOS converters, CXD1176Q (8- bit 20MHz A/D) and CXD1171M (8-bit 40MHz D/A). The evaluation board is composed of a main board common to either type, to which is added sub board CXD1176Q or sub board CXD1171M ...

Page 15

... Analog Output (CXD1171M) Item Min. Typ. Analog output 1.9 2.0 Output Format (CXD1176Q) The table shows the output format of AD Converter. Analog input Step voltage MSB 127 . . 128 . . . . . . . 255 V RB Timing Chart Analog input External clock AD clock AD output Latch output DA input DA clock ...

Page 16

... CXD1176Q ...

Page 17

... CXD1176Q 0.01µ CXD1171M —17— CXD1176Q 14 SYNC 13 SEL 12 CLK 0.1µ ...

Page 18

... This adjustment enables interface with the signal generator and others at the PCB shipment, adjustment is performed to obtain a threshold of approx. 2 sync transistor Q1 2SC2785 Q2 2SC2785 Q3 2SC2785 IC IC1 74S174 IC2 74S174 IC3 74S04 oscillator OSC others connector BNC071 SW AT1D2M3 —18— CXD1176Q ...

Page 19

... OE, SEL, Sync, BLK, CLE, Sync INT The following pins are set on the main board: OE, SEL, Sync, CLE, Sync INT (CXD1176Q) and BLK (CXD1171M). For the pins function, refer to the specifications. The difference between Sync pin and Sync INT pin is that you input a horizontal synchronizing signal above 3.5 Vp-p Sync INT pin. The pulse threshold is set through VR5 ...

Page 20

... The connector hole on DAC part is used to mount the test chassis and the mount jack. will activate the self-bias function that generates V RBS turns to about 1 that time necessary to bias input signals, but keeping R 2 —20— CXD1176Q = 2.6 V and RT – above 1.8 Vp- ...

Page 21

... Latch Up Prevention The CXD1176Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AV (Pins 16, 19 and 20) and Correct usage a. When analog and digital supplies are from different sources AV DD +5V + When analog and digital supplies are from a common source ...

Page 22

... AV SS (ii + CXD1176Q CXD1176Q CXD1176Q —22— CXD1176Q DIGITAL IC DIGITAL IC DIGITAL IC ...

Page 23

... Silk Side Component Side Soldering Side (Diagram seen from the component side) —23— CXD1176Q ...

Page 24

... SONY CODE EIAJ CODE JEDEC CODE 32PIN QFP (PLASTIC) 9.0 ± 0.2 + 0.3 7.0 – 0 0.15 0.3 – 0.1 0.24 M PACKAGE MATERIAL LEAD TREATMENT QFP-32P-L01 QFP032-P-0707 LEAD MATERIAL PACKAGE MASS —24— CXD1176Q 0.1 + 0.35 1.5 – 0.15 + 0.2 0.1 – 0.1 + 0.1 0.127 – 0.05 0° to 10° EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g ...

Page 25

... This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). 32PIN QFP (PLASTIC) 9.0 ± 0.2 + 0.3 7.0 – 0.30 ± 0.03 DETAIL A : PALLADIUM PACKAGE MATERIAL LEAD TREATMENT QFP-32P-L01 LEAD MATERIAL QFP032-P-0707 PACKAGE MASS —25— CXD1176Q 0.1 + 0.35 1.5 – 0. 0.2 0.1 – 0.1 0° to 10° EPOXY RESIN SOLDER / PALLADIUM PLATING 42 / COPPER ALLOY 0.2g ...

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