M65863FP Mitsumi Electronics, Corp., M65863FP Datasheet
M65863FP
Related parts for M65863FP
M65863FP Summary of contents
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... Dolby Digital Decoder M65863FP Product Note April 1998 MITSUBISHI ELECTRIC CORPORATION ...
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... DSP I/F (twice higher PCM transfer rate) • Controllable dynamic range compression • Programmable center and surround channel delays • Dialogue level control • No external memory required (M65863FP doos not have memory space for surround delay) Analog IEC958 Figure 1.1 M65863FP Configuration Diagram (DIR I/F) *1 Dolby, Dolby Digital (AC-3), and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corp ...
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... Product Note April 1998 Figure 1.2 M65963FP Configuration Diagram (DEMUX I/F) MITSUBISHI ELECTRIC CORPORATION Video Video Decoder DEMUX Audio M65863FP IEC958 2 I C/Clocked serial MCU 2 M65863FP Dolby Digital Decoder ...
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... Product Note April 1998 The figure 2.1 show the M65863FP I/O interface. VDD5V ASOUT CDATA Main/Sub Chip CCLK Interface RSYCREQ SYNCRST DEMUX ADVLDS Interface ADATA ACLKS VDD3V GND VDD5V _ADREQ _AMUT DOTX Digital Audio DIRX Interface ALRCK1 DIR/ADC ACLK1 Interface ADATA1 GND MITSUBISHI ELECTRIC CORPORATION ...
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... Data from DIR D5 Audio master clock input D5 Audio master clock output D5 Audio master clock output (1/2MCLKI) D5 PCM output for L ch and PCM output for C channel PCM output for SL ch and M65863FP Dolby Digital Decoder Description (main chip output / sub chip ...
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... Processor clock output for crystal P3.3 Processor clock input P3.3 VDD for PLL Selection of audio master clock ([0: 512fs 384fs 256fs Reserved Reset D5 Chip mode D5 Decode status (Normal : 1, Error : 0) D5 (AC PCM : 0) D5 MCU I/F Selection (Clocked serial : 0, I2C : M65863FP Dolby Digital Decoder ...
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... Data enable instruction for DEMUX interface. Data is input when this signal is enabled (0). _ADREQ Used in the data transmission control of DEMUX interface. SYNCRST Synchronization lock cancel signal. M65863FP starts detecting sync word when this signal is disabled. RSYCREQ SYNCRST request signal which is enabled when M65863FP comes out of synchronization. ...
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... OFF when 1. DECSTAT Indicates the current decoding status: 1 during normal decoding and time of error. DIRSTAT Indicates the current DIR input stream the case of Dolby Digital AC-3 input the case of PCM input. MITSUBISHI ELECTRIC CORPORATION 7 M65863FP Dolby Digital Decoder ...
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... Control Test • Register Address Dual stream (main effect and Associate service) can be decoded with 2 M65863FP. In the case, the register addresses for a main chip (which decodes main effect) and those for a sub chip (which decodes associate service) are different. In the following sections, only the register address for a main chip will be shown. For a sub chip you should add h'40 to the corresponding register address for a main chip. For a example, the address of the control register " ...
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... This field indicates nominal bit rate. This code is used along with the sample rate code to determine the number of bytes per frame. address h'01 Bitstream Identification (bsid) This field contains the version number of the coder syntax. M65863FP only supports MITSUBISHI ELECTRIC CORPORATION ...
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... Associated service : emergency ( Associated service : voice-over (VO Main audio service : karaoke Audio Coding Mode Channel Array Ordering 1+1 1/0 2/0 3/0 2/1 3/1 2/2 3/2 [L,C,R,SL,SR] Indication Not indicated NOT Dolby Surround encoded Dolby Surround encoded Reserved 10 M65863FP Dolby Digital Decoder 3 bits 3 bits [Ch1,Ch2] [C] [L,R] [L,C,R] [L,R,S] [L,C,R,S] [L,R,SL,SR] 2 bits 1 bit 1 bit 1 bit ...
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... If this bit is a 1,this bitstream has a compression gain word for ch2 when acmod indicates dual mono MITSUBISHI ELECTRIC CORPORATION Type of Mixing Room Not indicated Large room. X curve monitor Small room. flat monitor Reserved 11 M65863FP Dolby Digital Decoder 5 bits 1 bit 1 bit 8 bits 8 bits 8 bits ...
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... This field contains room type for ch2 when acmod indicates dual mono mode (acmod=000). Audio Production Information Exists, Ch2 (audprodi2e) This bit indicates audio production information for ch2 when acmod indicates dual mono mode (acmod=000). MITSUBISHI ELECTRIC CORPORATION 12 M65863FP Dolby Digital Decoder 8 bits 8 bits 8 bits 5 bits ...
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... Main audio service : music and effects (ME) Associated service : visually impaired (VI) Associated service : hearing impaired (HI) Associated service : dialogue (D) Associated service : commentary (C) Associated service : emergency (E) Associated service : voice-over (VO main audio service : karaoke Status No error Error 13 M65863FP Dolby Digital Decoder R/W idtdep R 5 bits 1 bit 1 bit ...
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... The value of bsid is less than 8 and encode error doesn't exist The value of bsid is more than 9, or encode error exists Description Regular decode Mute Description Sync word was detected Sync word was not detected Description Sync word is locked Sync word is not locked 14 M65863FP Dolby Digital Decoder R/W bserr crc2err ...
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... Read Pointer to the Input Data Buffer (readpointer) Read pointer to the input data buffer. Read/Write operation are allowed when M65863FP is not decoding. Only read operation is allowed when M65863FP is decoding. address h'12 address h'13 Write Pointer to the Input Data Buffer (writepointer) Write pointer to the input data buffer ...
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... M65863FP Dolby Digital Decoder R/W synclock R dspif ...
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... Synchronous Lock Control (synclock) Set the number of sync words required for entering the state where synchronization is established. Default value is 2 (b'010). Set the value only once when M65863FP is in the initial state. synclock Output Format (dacform) Specify the output format ...
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... DSP/DAC Clock Mode (dacclkmode) Specify the LR clock and bit clock to be used in the DAC/DSP interface. M65863FP becomes the clock master and divides the audio master clock to generate LR clock (LRCK)/bit clock (BCLK). When dacclkmode=1, M65863FP becomes the slave and uses the DIR/ADC input clocks (ALRCK, ACLK) as the LR clock and bit clock, respectively ...
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... Default setting is noise off. slnoise 0 1 SR-ch Noise (srnoise) Control of noise generation for SR channel. When set to noise on, M65863FP enters noise output mode while ignoring the audio input from DIR/ADC and DEMUX. Noise generation can be turned on/off at any time. Default setting is noise off. srnoise 0 ...
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... DIR/ADC and DEMUX. Noise generation can be turned on or off at any time. Default setting is noise off. srnoise 0 1 address h'17 Data input Port Selection Control(inportsel) Select the audio input port of M65863FP in this field. In the default setting, data stream from DIR/ADC1 is received. This field can be changed at any time. inportsel ...
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... Full-time decoding Decoding done if dsurmod-specified Dolby surround is encoded Reserved Description 16 bit 18 bit 20 bit 24 bit Description Auto-balance ON Auto-balance OFF Description Wide mode Narrow mode Description Line-out mode RF mode Custom mode B Custom mode A 21 M65863FP Dolby Digital Decoder 2 bits 2 bits 1 bit 1 bit 2 bits ...
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... MITSUBISHI ELECTRIC CORPORATION Type of Dual Monaural Output Mode Lch:ch1, Rch:ch2 Lch:ch1, Rch:ch1 Lch:ch2, Rch:ch2 Lch:ch1+ch2, Rch:ch1+ch2 Output Channel Mode Output Channel Dolby Pro Logic encode stereo 1/0 2/0 3/0 2/1 3/1 2/2 3/2 22 M65863FP Dolby Digital Decoder 2 bits 3 bits [Lt,Rt] [C] [L,R] [L,C,R] [L,R,S] [L,C,R,S] [L,R,SL,SR] [L,C,R,SL,SR] ...
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... When this bit is set to 1, compression gain word and dynamic range gain word are transferred from the sub chip to the main chip via the main/sub chip interface, thus enabling it to decode dual streams. Default value is 0 (single stream mode). Set the value in this field only once when M65863FP is in the initial status. ...
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... This field indicates whether the default coefficient value used or not. This flag is valid only in the karaoke capable mode (when control register karaply = 1). When this flag is 0, M65863FP uses the default coefficient value. When value of control register (address IE-33) is used in karaoke mixing. ...
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... This field is valid. when using DEMUX I/F (inportsel=10) and specifies a interface protocol. When the field is '1', M65863FP inputs Dolby Digital (AC-3) stream for exactly 1 frame at a time. When the field is '0', M65863FP inputs Dolby Digital (AC-3) stream until the input buffer is full. Default value is '0'. Set the value in the field only once when M65863FP is in the initial state ...
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... Karaoke Mixing Coefficient (kcoeffk) Coefficient for mixing R with Rk. Value h'7FFF corresponds to 1.0. Default value is h'0000 (0.0). While this field can be changed at any time, set value is reflected in synchronization with the audio block during Dolby Digital (AC-3) decoding. MITSUBISHI ELECTRIC CORPORATION 26 M65863FP Dolby Digital Decoder 16 bits 16 bits 16 bits 16 bits ...
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... MITSUBISHI ELECTRIC CORPORATION Table 4.6 Test Registers inputh inputl Description Not underflow Underflow Description Not overflow Overflow Description Not underflow Underflow Description Not overflow Overflow 27 M65863FP Dolby Digital Decoder 6 7 R/W outputh outpuyl bit 1 bit 1 bit 1 bit ...
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... The relationship between the signal level of ALRCK and output channel (L/R, C/SW, SL/SR) is selective. The details are shown in figure 5.2 and figure 5.3. When M65863FP accepts Dolby Digital (AC-3) data from Digital Audio I/F Receiver, 16 bit mode must be selected. MITSUBISHI ELECTRIC CORPORATION ...
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... LEFT LEFT LSB MSB 16 cycles LSB MSB 18 cycles LSB MSB LSB MSB 32 cycles 2 S Format (16bit, 18bit, 20bit, 24bit) 29 M65863FP Dolby Digital Decoder RIGHT RIGHT MSB/LSB 16 cycles MSB/LSB 18 cycles MSB/LSB 20 cycles 24 cycles 32 cycles RIGHT RIGHT LSB LSB LSB 20 cycles ...
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... Figure 5.5 Interface Between DEMUX and M65863FP If burstcont _ADREQ will be high when the input buffer becomes full. If burstcont _ADREQ will be high when M65863FP relieves 1 sync frame. The burstcont returns to low when M65863FP outputs the first PCM of the frame. 5.1.3 Sync Word Detection Start Signal If SYNCRST is asserted when receiving DEMUX input (control register inportsel is 10) and the control register syncrsten is either 01 or 10, M65863FP returns to the state of being out of synchronization ...
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... SYNCRST is asserted. 2) When M65863FP detects rising edge of SYNCRST, M65863FP comes out of synchronization and asserts RSYCREQ. In the case of mode A, M65863FP does not detect sync word and remains out of synchronization while SYNCRST is enabled. When M65863FP is out of synchronization, input stream is not stored in the input buffer. ...
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... It should be noted, however, that decoding is not restarted under this condition. 4) When M65863FP detects the falling edge of SYNCRST, it restarts decoding at the nearest audio frame behind the address indicated by Readpointer. In mode B, decoding can be restarted at any desired audio frame which is input after assertion of SYNCRST, by writing over the Readpointer for the input buffer during the period of asserting SYNCRST (It is limited to the frame following the detection of sync word and restart of transfer to the input buffer ...
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... Audio Output Interface M65863FP carries out audio output in the format of DAC interface shown in 5.2.1 or DSP interface shown in 5.2.2. Selection from among these formats is made by means of the control register dspif. DAC interface is selected when dspif is 0, and DSP interface is selected when dspif is 1. ...
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... DAC interface. Relation between the signal levels of LRCK and 2LRCK and the output channel can be inverted by means of MSB of the control register dacform similarly to the case of DAC interface. LRCK can be either generated by M65863FP by dividing the audio master clock (master mode), or taken from the input of DIR/ADC interface (slave mode). Setting the control register dacclkmode to 0 results in master mode and setting results in slave mode ...
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... S Format Interface Between M65863FP and DAC(dacform[0]=1) 5.2.3 Digital Audio Interface M65863FP outputs either of 2 input data streams from DOTX. The selection of the input data streams desponds on the content of inportsel(Control register). 1) When inportsel(control register (DIR I/F input), M65863FP bypasses the input stream from DIRX to DOTX ...
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... The sub-frame isn't channel 0 (channel1, 2, ...) Category code 1 CR Sampling rate Shzdow fields are all zero Figure 5.12 Channel Status Table 5.3 Preamble Words Contents 36 M65863FP Dolby Digital Decoder 30 31 Subframe Frame 0 (Channel 0) Subframe (Channel 1) Block Frame191 Description ...
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... Table 5.5 Values of data_type Meaning Reserved Dolby Digital (AC-3) data Time Stamp Reserved 0-2 Value of bsmod in AC-3 elementary stream 3-4 Reserved, shall be set to '00' 37 M65863FP Dolby Digital Decoder *bit15 is MSB Meaning ...
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... C bus Figure 5.13 Data Transfer on the 1 R/_W ACK data ACK Figure 5.14 Data Transfer (7 bit address packet where the host micro (master) writes bytes to the M65863FP A Data Register address A 38 M65863FP Dolby Digital Decoder 2 3-8 9 End Condition 2 C BUS 1 ...
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... SCLK is transmission clock data input and SO is data output. Transmission is carried out in the unit of 1 byte, MSB first. In the case of data input, M65863FP takes in 8 byte data which remains in the buffer (shift register) at the time _SS is enabled. In the case of data output, 1 byte data following the clock immediately after _SS was enabled is output ...
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... MCU that follows. Figure 5.22 Instructions of Reading Registers of M65863FP When writing into M65863FP, specify in the 1 byte the start address of writing (7 bits) following 1 (1 bit) which indicates writing operation, and specify in the 2 byte the number of bytes to be written. Thereafter, specified number of bytes of data to be written is transmitted ...
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... Product Note April 1998 Figure 5.23 Instruction of Writing Registers of M65863FP MITSUBISHI ELECTRIC CORPORATION <Start address> <WRITEnumber of byte> <Data 1> <Data 2> * <Data N> 41 M65863FP Dolby Digital Decoder ...
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... April 1998 5.4 Main/Sub Chip Interface Dual stream(Main effect and Associated service) can be decoded with 2 M65863FP chips. In this case, set asmix (control register) to High on both chips and specify chip mode(mainchip or subchip) on either chip with Chipmode(control register). respectively. The Main chip and Sub chip communicate with each other in the following manner. ...
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... Change external I/F? When reset, M65863FP enters the initial state by executing the initialization routine. In the initial state, all control registers are set to their default values. When the initialization routine has completed, set the external interface and operation mode by writing over the values of the control registers. ...
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... Resetting and Initial State Figure 6.2 shows the operation during resetting. At least xxx is required for the period of asserting _RST. If _RST is negated, M65863FP executes the initialization routine to set default values in the on-chip registers. The initialization routine takes 0.2msec. Upon completion of the initialization routine, set the external interface and decoding mode by writing over the values of the control registers ...
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... Items which can be set only once immediately after resetting 1) Selection of LRCK/BCLK mode Control register : dacclkmode Option : Generation by M65863FP (master), use of input ALRCK, ACLK (slave) 2) Whether dual stream decoding or not Control register : asmix Option : Single stream decoding, dual stream decoding ...
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... Selection of Operation Mode M65863FP supports the following operation modes. Mode varies depending on the setting of control register and the input stream. Operation mode can be changed even during PCM output by M65863FP. When changing the mode, M65863FP automatically mutes the output to prevent abnormal sound. ...
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... A state in which output is muted because, although synchronization is established, an error was detected in external direction (external terminal AMUTE, control register muteonoff the stream. M65863FP enters the normal decoding status when the external direction is canceled or the error in the stream is removed. When detection of sync word fails twice successively, on the contrary, M65863FP comes out of synchronization ...
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... Muting Operation When an error is detected in the data stream which is being input, or when directed by the control register (muteonof)f and external (AMUTE), M65863FP mutes the output PCM. Specifically, muting operation is carried out in the following cases. 1) CRC1/CRC2 error and encode error are detected during Dolby Digital (AC-3) decoding. Encode error refers to a case when an abnormal value is detected in bitstream in spite of normal result of CRC check ...
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... Product Note April 1998 6.7 Decoding Delay Dolby Digital (AC-3) decoding delay of M65863FP varies between the cases of DIR I/F input and DEMUX I/F input. <Decoding delay with DIR I/F> Decoding delay is given by the following equation. Decoding delay = 1 frame transmission time * 2 audio block period For example, when sampling frequency is 48kHz and bit rate of stream data is 384 kbps (length of 1 frame is 768*16 bits), decoding delay becomes approx ...
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... One of 4 output modes can be selected when the main audio services the Dual Mode. Encode Channel Mode 1+1(Dual Mono) 1/0 2/0 3/0 2/1 3/1 2/2 3/2 Pro Logic (2/0) MITSUBISHI ELECTRIC CORPORATION Table 6.1 Output Channel Selection Available Output Channel Form Ch1->L Ch1->R Ch2->L Ch2->R Ch1->L Ch2->R (Ch1+Ch2)->L (Ch1+Ch2)->R 1/0, 2/0 (monaural stereo) 1/0, 2/0 1/0, 2/0, 3/0 1/0, 2/0, 2/1, 2/2 1/0, 2/0, 3/0, 2/1, 2/2, 3/1, 3/2 1/0, 2/0, 2/1, 2/2 1/0, 2/0, 3/0, 2/1, 2/2, 3/1, 3/2 1/0, 2/0, 3/0, 2/1, 2/2, 3/1, 3/2 50 M65863FP Dolby Digital Decoder ...
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... Product Note April 1998 M65863FP allows it to form oscillation circuit and a frequency quadruplier (PLL) circuit by connecting an oscillator element, resistor and capacitor on the outside. This enables it to generate the clock required for the internal operation, though auto-oscillation by using low-frequency external clock. MITSUBISHI ELECTRIC CORPORATION ...
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... A frequency quadruplier circuit can be formed by connecting a loop filter to PLL3 terminal, a PLL stabilizer resistor to PLL2 terminal and a current reference resistor to PLL1 terminal. MITSUBISHI ELECTRIC CORPORATION Cp PCLK Rp Cp PVCO Figure 7.2 Configuration for Clock Oscillator External Clock PCLK Figure 7.3 Figure 7.4 52 M65863FP Dolby Digital Decoder Symbol Value 30pF 3.3V Symbol Value ...
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... IEC958 output De-emphasis on/off <Complementary notes> 1) All or part of DEMUX, ADC and DIR can be connected to M65863FP as audio inputs. 2) 2nd DSP assumes processes such as center/surround delay and crossover filter to be done. When limited to AC-3 2ch output, output of M65863FP can be directly connected to DAC. 3) MCU I/F supports I2C I/F as well as the above (synchronized 4 line serial). ...
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... Frequency at external clock MITSUBISHI ELECTRIC CORPORATION Chapter 9 Value -0.3 to +6.5 -0.3 to +4.5 -0.3 to +4.5 GND-0.3 VI VDD5V+0.3 GND-0.3 VI PLLVCC+0.3 GND VO VDD5V GND VO PLLVCC 910 -20 to +75 -40 to +125 Condition for Measuvment min 0.7XVDD5V GND 54 M65863FP Dolby Digital Decoder Unit °C °C Value Unit typ max 4 ...
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... IOZL Low off state output leak current (I/O) MITSUBISHI ELECTRIC CORPORATION Characteristics Condition for Measuvment fpclk=???MHz VDD5V=5V,IIOI<1µA VDD5V=5V,IIOI<1µA VDD5V=4.5V,VOL=4.1V VDD5V=4.5V,VOL=0.4V VDD5V=5.5V,VI=5.5V VDD5V=5.5V,VI=0V VDD5V=5.5V,VI=5.5V VDD5V=5.5V,VI=0V 55 M65863FP Dolby Digital Decoder Value Unit min typ max - - TBD mA 4. ...
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... Setup time, ADATA and ACLK Hold time, ADATA and ACLK th(ACLKS-ADVLDS) tsu(ADVLDS-ACLKS) tsu(ACLKS-ADATAS) Characteristics Setup time, ALRCK and ACLKS Hold time, ALRCK and ACLKS Setup time, ADATA and ACLKS Hold time, ADATA and ACLKS 56 M65863FP Dolby Digital Decoder min typ max Unit ...
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... DOxx Symbol tdv(2BCLK-LRCK) tdv(2BCLK-2LRCK) tdv(2BCLK-DO) MITSUBISHI ELECTRIC CORPORATION tdv(BCLK-LRCK) tdv(BCLK-DO) Characteristics LRCK output delay DO output delay tdv(2BCLK-2LRCK) tdv(2BCLK-DO) Characteristics LRCK output delay 2LRCK output delay DO output delay 57 M65863FP Dolby Digital Decoder min typ max Unit - - tdv(2BCLK-LRCK) min typ max ...
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... Characteristics Setup time, _SS and SCK Setup time, _SS and SCK SO output delay SO disable delay Setup time, SI and SCK Hold time, SI and SCK 58 M65863FP Dolby Digital Decoder Lead Material Alloy 42 th(SCK-SS) tdz(SS-SO) min typ max Unit 10 - ...
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... Product Note April 1998 MITSUBISHI ELECTRIC CORPORATION Chapter 10 Package 59 M65863FP Dolby Digital Decoder ...
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... No liability is assumed as a result of their use or application. No rights under any patent accompanies the sale of any such product(s) or information. Copyright (C)1998 MITSUBISHI ELECTRIC CORPORATION. All rights reserved. Printed in Japan April 1998 MITSUBISHI ELECTRIC CORPORATION Appendix A 60 M65863FP Dolby Digital Decoder ...