VSC055 Maxim Integrated Products, VSC055 Datasheet
VSC055
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VSC055 Summary of contents
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... D ENERAL ESCRIPTION The VSC055-01 device is an I/O-intensive peripheral device that is intended to be part of a cost-effective Fibre Channel Arbitrated Loop (FC-AL), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), or Serial ATA (SATA) enclosure management solution. The device contains an address-programmable two-wire serial interface, a block of control and status registers, I/O port control logic, specialized port bypass control logic, and a clock-generation block. Along with an external crystal, the device can be configured to support bits of general-purpose I/O ...
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... This capability allows independent Master mode two-wire serial slave ports to be created using 32 of the I/O pins. The addressing capability of the VSC055-01 includes three pins, which are used for device addressing, as well as one pin that can be used to select two device type identifiers. Sixteen VSC055-01 devices can be used in a single two-wire serial interface system. Block Diagram P0.0 − ...
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... Two-Wire Serial Interface Temperature Sensor (LM75) Copper or Optics Local I/O (x8) VSC7142 PBC_EN VSC120 Embedded Controller Flash Memory PBC_EN1 VSC7147 PBC_EN2 PBC_EN3 PBC_EN4 VSC055-01 Enhanced Backplane Controller LEDs (x8 133 Drive Bay 1 Drive Bay 2 Drive Bay 3 Drive Bay 4 Power Supplies Fans (x4) Revision 4.1 January 2008 ...
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... Two-Wire Serial Interf ace Interrupt (optional) I/O (x8) I/O (x8) VSC055-01 VSC055-01 I/O (x8) I/O (x8) I/O (x8) Enhanced I/O (x8) I/O (x8) I/O (x8) Backplane Backplane I/O (x8) Controller I/O (x8) I/O (x8) I/O (x8) VSC055-01 VSC055-01 I/O (x8) I/O (x8) I/O (x8) Enhanced I/O (x8) I/O (x8) Backplane I/O (x8) Backplane I/O (x8) Controller I/O (x8 133 VSC055-01 Data Sheet I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) Enhanced I/O (x8) I/O (x8) I/O (x8) I/O (x8) Controller I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) I/O (x8) Enhanced I/O (x8) I/O (x8) I/O (x8) I/O (x8) Controller I/O (x8) ...
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... VSC055-01 Data Sheet Contents General Description..................................................................................................... 1 Features ........................................................................................................................ 1 Applications ................................................................................................................. 1 Typical Applications .................................................................................................... 3 Revision History........................................................................................................... 9 1 Introduction ....................................................................................................... 10 2 Functional Descriptions ................................................................................... 11 2.1 Two-Wire Serial Interface ............................................................................................................11 2.2 Control Registers .........................................................................................................................11 2.3 I/O Logic ......................................................................................................................................13 2.4 Clock Generator ..........................................................................................................................13 2.5 Power-on Reset ...........................................................................................................................14 3 Registers ............................................................................................................ 15 3.1 Control Registers .........................................................................................................................15 3.2 Control Register Definitions .........................................................................................................21 3.2.1 00h: General-Purpose I/O Port 0 Data (GPD0) .............................................................21 3.2.2 01h: General-Purpose I/O Port 1 Data (GPD1) .............................................................22 3 ...
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... Pulse Train Control 20 (PTC20) ............................................................................66 3.2.62 75h: Pulse Train Control 21 (PTC21) ............................................................................67 3.2.63 76h: Pulse Train Control 30 (PTC30) ............................................................................68 3.2.64 77h: Pulse Train Control 31 (PTC31) ............................................................................69 3.2.65 78h: Pulse Train Control 40 (PTC40) ............................................................................70 3.2.66 79h: Pulse Train Control 41 (PTC41) ............................................................................71 3.2.67 7Ah: Pulse Train Control 50 (PTC50) ............................................................................72 Revision 4.1 January 2008 6 of 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.68 7Bh: Pulse Train Control 51 (PTC51) ............................................................................73 3.2.69 7Ch: Pulse Train Control 60 (PTC60) ............................................................................74 3.2.70 7Dh: Pulse Train Control 61 (PTC61) ............................................................................75 3.2.71 7Eh: Pulse Train Control 70 (PTC70) ............................................................................76 3.2.72 7Fh: Pulse Train Control 71 (PTC71) ............................................................................77 3.2.73 80h-87h: Bit Control Port 0 (BCP00-BCP07) .................................................................78 3.2.74 88h: Pulse Train Control 80 (PTC80) ............................................................................81 3.2.75 89h: Pulse Train Control 81 (PTC81) ............................................................................82 3 ...
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... Two-Wire Serial Interface Operation ..........................................................................................122 4.6 Oscillator Requirements ............................................................................................................123 4.7 Optional External Tach Filter .....................................................................................................123 5 Pin Descriptions .............................................................................................. 124 5.1 Pin Diagram ...............................................................................................................................124 5.2 Pin Identifications ......................................................................................................................126 6 Package Information ....................................................................................... 131 6.1 Thermal Specifications ..............................................................................................................131 6.2 Moisture Sensitivity ...................................................................................................................131 6.3 Package Drawing .......................................................................................................................131 7 Ordering Information ...................................................................................... 133 Revision 4.1 January 2008 8 of 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet R H EVISION ISTORY This section describes changes that have been implemented in this document. The changes are listed by revision, starting with the most recent publication. Revision 4.1 Revision 4.1 of this data sheet was published in January 2008. The following is a summary of the changes implemented in the data sheet ...
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... Introduction This data sheet provides reference information for the Maxim Enhanced Two-Wire Serial Backplane Controller, VSC055-01 intended for system designers and software and firmware developers who are using this device to support enclosure management functions or other related remote I/O expansion tasks. The VSC055-01 is pin, function, feature, package, and power supply compatible with the VSC055. ...
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... All sequential transactions cause the internal address to increment by one, regardless of the register address. 2.2 Control Registers The VSC055-01 device contains six groups of control registers. Each group supports a specific function within the device as follows: the first group is the port data registers ● ...
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... The VSC055-01 device contains 164 registers to support all required functions. In normal I/O operation, each 8-bit group of I/O pins are controlled by a pair of registers, Port Data and Data Direction. The use of these pairs of registers allows each I/O line to be individually configured as an input with internal pull-up, output or open-drain output with internal pull-up ...
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... Additionally, when using a high frequency clock, the CKOUT pin provides a divided clock that can be used to drive other VSC055-01 devices within the system. This mechanism ensures that a single additional load is placed on the system clock with all subsequent clock inputs daisy-chained from the first VSC055-01 ...
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... LEDs at the same frequency, providing a synchronized visible indication. Devices attached to different two-wire serial busses can be synchronized by enabling the SYNC# pin. This pin, which is connected to the SYNC# pin of all VSC055-01 devices in the system, provides a sync pulse based on a programmable delay that is greater than the slowest selected LED flash rate. For more information about the programmable capabilities of this feature, see Control (CSC),” ...
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... VSC055-01 Data Sheet 3 Registers This section contains descriptions for the device-specific control registers. All register locations are fixed within the device and are mapped for easy access, as well as for future enhancements. 3.1 Control Registers The control register section is separated into three sub-sections: a register map, an address map, and bit level descriptions of all registers ...
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... Pulse Train 0 Control 1 Register PTC10 Pulse Train 1 Control 0 Register PTC11 Pulse Train 1 Control 1 Register PTC20 Pulse Train 2 Control 0 Register PTC21 Pulse Train 2 Control 1 Register PTC30 Pulse Train 3 Control 0 Register PTC31 Pulse Train 3 Control 1 Register PTC40 Pulse Train 4 Control 0 Register 16 of 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet Table 2. Register Map (continued) Data Memory Address Access 79h R/W 7Ah R/W 7Bh R/W 7Ch R/W 7Dh R/W 7Eh R/W 7Fh R/W 80h R/W 81h R/W 82h R/W 83h R/W 84h R/W 85h R/W 86h R/W 87h R/W 88h R/W 89h R/W 8Ch R/W 8Dh R/W 90h R/W 91h R/W 92h R/W 93h R/W 94h R/W 95h R/W 96h R/W 97h R/W 98h R/W 99h R/W 9Ah ...
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... BCP63 Bit Control Port 6 - Bit 3 Register BCP64 Bit Control Port 6 - Bit 4 Register BCP65 Bit Control Port 6 - Bit 5 Register BCP66 Bit Control Port 6 - Bit 6 Register BCP67 Bit Control Port 6 - Bit 7 Register MICD Master Interface Clock Divider Register 18 of 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet Table 2. Register Map (continued) Data Memory Address Access E9h R/W EAh R/W EBh R/W ECh R/W EDh R EEh R F0h R/W F1h R/W F2h R/W F3h R/W F4h R/W F5h R/W F6h R/W F7h R/W F8h R/W FCh R/W FDh R/W FEh R/W FFh R The following table provides the mapping of the register sets by address. Table 3. Address Map ...
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... BCP62 BCP61 BCP66 BCP65 MID MIPS MIRD MIS BCP72 BCP71 BCP76 BCP75 reserved reserved CDC CSC 20 of 133 VSC055-01 Data Sheet 00b Address FSC7 4Ch reserved 50h-6Ch PTC00 70h PTC20 74h PTC40 78h PTC50 7Ch BCP00 80h BCP04 84h ...
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... VSC055-01 Data Sheet 3.2 Control Register Definitions The control register definitions provides a bit-level description of all register bits, including power on and default values. The terms set and assert refer to bits that are programmed to a binary 1. The terms reset, de- assert, and clear refer to bits that are programmed to a binary 0. Reserved bits are represented by RES and always return an unknown value ...
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... If a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors hold the pin at a binary 1. After a reset or power on, the register bits are set to a binary 1, however, the value returned from a register read is the level applied to the pin since each pin is an input by default 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.4 03h: General-Purpose I/O Port 3 Data (GPD3) The following table shows the bit assignments for the General-Purpose I/O Port 3 Data register. Control of the individual I/O pins in this register can be overridden by the PBC0, PBC1, PBC2, and PBC3 registers when port bypass control is required. ...
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... If a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors hold the pin at a binary 1. After a reset or power on, the register bits are set to a binary 1, however, the value returned from a register read is the level applied to the pin since each pin is an input by default 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.8 07h: General-Purpose I/O Port 7 Data (GPD7) The following table shows the bit assignments for the General-Purpose I/O Port 7 Data register. Register Name: GPD7 Address: 07h Reset Value: XXXX_XXXXb Bit Bit Label 7:0 GPD7.7-0 3.2.9 10h: I/O Port 0 Data Direction (DDP0) The following table shows the bit assignments for the I/O Port 0 Data Direction register. ...
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... Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I input with weak pull-up 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.12 13h: I/O Port 3 Data Direction (DDP3) The following table shows the bit assignments for the I/O Port 3 Data Direction register. Control of the individual I/O pins in this register can be overridden by the PBC0, PBC1, PBC2, and PBC3 registers when port bypass control is required. ...
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... Each I/O pin can be individually configured as a true bidirectional function. To implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. After a reset or power on, these bits are set to a binary 1, enabling the I input with weak pull-up 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.16 17h: I/O Port 7 Data Direction (DDP7) The following table shows the bit assignments for the I/O Port 7 Data Direction register. Register Name: DDP7 Address: 17h Reset Value: 1111_1111b Bit Bit Label 7:0 DDP7.7-0 Access Description R/W Data Direction These bits determine the direction of the data flow through the I/O pin. ...
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... When the PBCEN bit is set, this bit becomes a read-only indication of the P3.0 I/O pin, which has been connected to the signal detected output of a PBC/ CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.18 21h: Port Bypass Control 1 (PBC1) The following table shows the bit assignments for the Port Bypass Control 1 register. This register functions the same as the Port Bypass Control 0 register except it affects the P3.3 and P3.2 pins. Register Name: PBC1 Address: 21h ...
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... When the PBCEN bit is set, this bit becomes a read-only indication of the P3.4 I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.20 23h: Port Bypass Control 3 (PBC3) The following table shows the bit assignments for the Port Bypass Control 3 register. This register functions the same as the Port Bypass Control 0 register except it affects the P3.7 and P3.6 pins. Register Name: PBC3 Address: 23h ...
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... When the PBCEN bit is set, this bit becomes a read-only indication of the P4.0 I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.22 25h: Port Bypass Control 5 (PBC5) The following table shows the bit assignments for the Port Bypass Control 5 register. This register functions the same as the Port Bypass Control 0 register except it affects the P4.3 and P4.2 pins. Register Name: PBC5 Address: 25h ...
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... When the PBCEN bit is set, this bit becomes a read-only indication of the P4.4 I/O pin, which has been connected to the signal detected output of a PBC/ CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.24 27h: Port Bypass Control 7 (PBC7) The following table shows the bit assignments for the Port Bypass Control 7 register. This register functions the same as the Port Bypass Control 0 register except it affects the P4.7 and P4.6 pins. Register Name: PBC7 Address: 27h ...
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... When the PBCEN bit is set, this bit becomes a read-only indication of the P5.0 I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.26 29h: Port Bypass Control 9 (PBC9) The following table shows the bit assignments for the Port Bypass Control 9 register. This register functions the same as the Port Bypass Control 0 register except it affects the P5.3 and P5.2 pins. Register Name: PBC9 Address: 29h ...
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... When the PBCEN bit is set, this bit becomes a read-only indication of the P5.4 I/O pin, which is connected to the signal detected output of a PBC/CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.28 2Bh: Port Bypass Control 11 (PBC11) The following table shows the bit assignments for the Port Bypass Control 11 register. This register functions the same as the Port Bypass Control 0 register except it affects the P5.7 and P5.6 pins. Register Name: PBC11 Address: 2Bh ...
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... When the PBCEN bit is set, this bit becomes a read-only indication of the P6.0 I/O pin, which has been connected to the signal detected output of a PBC/ CRU/SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.30 2Dh: Port Bypass Control 13 (PBC13) The following table shows the bit assignments for the Port Bypass Control 13 register. This register functions the same as the Port Bypass Control 0 register except it affects the P6.3 and P6.2 pins. Register Name: PBC13 Address: 2Dh ...
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... When the PBCEN bit is set, this bit becomes a read-only indication of the P6.4 I/O pin, which has been connected to the signal detected output of a PBC/CRU/ SDU function. If this bit is set, the signal detect unit detects a high-speed signal. If this bit is reset, the signal detect unit does not detect a high-speed signal 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.32 2Fh: Port Bypass Control 15 (PBC15) The following table shows the bit assignments for the Port Bypass Control 15 register. This register functions the same as the Port Bypass Control 0 register except it affects the P6.7 and P6.6 pins. Register Name: PBC15 Address: 2Fh ...
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... Typical applications can consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values 133 VSC055-01 Data Sheet this input is SS ...
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... VSC055-01 Data Sheet 3.2.34 31h: Fan Speed Count Overflow 0 (FSCO0) The following table shows the bit assignments for the Fan Speed Count Overflow 0 register. This register affects the P2.0 pin. Register Name: FSCO0 Address: 31h Reset Value: 0000_0000b Bit Bit Label 7:0 FSCO7-0 3.2.35 32h: Fan Speed Current Count 0 (FSCC0) The following table shows the bit assignments for the Fan Speed Current Count 0 register ...
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... Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values 133 VSC055-01 Data Sheet this input is ...
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... VSC055-01 Data Sheet 3.2.37 35h: Fan Speed Count Overflow 1 (FSCO1) The following table shows the bit assignments for the Fan Speed Count Overflow 1 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.1 pin. Register Name: FSCO1 Address: ...
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... Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values 133 VSC055-01 Data Sheet this input is SS ...
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... VSC055-01 Data Sheet 3.2.40 39h: Fan Speed Count Overflow 2 (FSCO2) The following table shows the bit assignments for the Fan Speed Count Overflow 2 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.2 pin. Register Name: FSCO2 Address: ...
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... Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values 133 VSC055-01 Data Sheet this input is ...
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... VSC055-01 Data Sheet 3.2.43 3Dh: Fan Speed Count Overflow 3 (FSCO3) The following table shows the bit assignments for the Fan Speed Count Overflow 3 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.3 pin. Register Name: FSCO3 Address: ...
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... Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values 133 VSC055-01 Data Sheet this input is SS ...
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... VSC055-01 Data Sheet 3.2.46 41h: Fan Speed Count Overflow 4 (FSCO4) The following table shows the bit assignments for the Fan Speed Count Overflow 4 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.4 pin. Register Name: FSCO4 Address: ...
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... Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values 133 VSC055-01 Data Sheet this input is ...
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... VSC055-01 Data Sheet 3.2.49 45h: Fan Speed Count Overflow 5 (FSCO5) The following table shows the bit assignments for the Fan Speed Count Overflow 5 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.5 pin. Register Name: FSCO5 Address: ...
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... Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values 133 VSC055-01 Data Sheet this input is ...
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... VSC055-01 Data Sheet 3.2.52 49h: Fan Speed Count Overflow 6 (FSCO6) The following table shows the bit assignments for the Fan Speed Count Overflow 6 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.6 pin. Register Name: FSCO6 Address: ...
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... Typical applications may consider 60% to 70% of nominal RPM a fan failure, which would result in a decimal count value of 250 (FAh) and 214 (D6h), respectively, at the above stated RPM values 133 VSC055-01 Data Sheet this input is ...
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... VSC055-01 Data Sheet 3.2.55 4Dh: Fan Speed Count Overflow 7 (FSCO7) The following table shows the bit assignments for the Fan Speed Count Overflow 7 register. This register functions same the Fan Speed Count Overflow 0 register except it affects the P2.7 pin. Register Name: FSCO7 Address: ...
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... Revision 4.1 January 2008 page 111. Access Description R/W Pulse Train These eight bits are the first bits shifted out from and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.58 71h: Pulse Train Control 01 (PTC01) This register, along with the PTC00 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC00 register provides eight of the twelve bits available in the programmable pulse train. ...
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... Revision 4.1 January 2008 page 111. Access Description R/W Pulse Train These eight bits are the first bits shifted out from and define the on/off time for the flash rate. 1: defines LED on time 0: defines LED off time 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.60 73h: Pulse Train Control 11 (PTC11) This register, along with the PTC10 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC10 register provides eight of the twelve bits available in the programmable pulse train. ...
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... Revision 4.1 January 2008 page 111. Access Description R/W Pulse Train These eight bits are the first bits shifted out from and define the on/off time for the flash rate. 1: defines LED on time 0: defines LED off time 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.62 75h: Pulse Train Control 21 (PTC21) This register, along with the PTC20 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC20 register provides eight of the twelve bits available in the programmable pulse train. ...
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... Revision 4.1 January 2008 page 111. Access Description R/W Pulse Train These eight bits are the first bits shifted out from and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.64 77h: Pulse Train Control 31 (PTC31) This register, along with the PTC30 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC30 register provides eight of the twelve bits available in the programmable pulse train. ...
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... Revision 4.1 January 2008 page 111. Access Description R/W Pulse Train These eight bits are the first bits shifted out from and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.66 79h: Pulse Train Control 41 (PTC41) This register, along with the PTC40 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC40 register provides eight of the twelve bits available in the programmable pulse train. ...
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... Revision 4.1 January 2008 page 111. Access Description R/W Pulse Train These eight bits are the first bits shifted out from and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.68 7Bh: Pulse Train Control 51 (PTC51) This register, along with the PTC50 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC50 register provides eight of the twelve bits available in the programmable pulse train. ...
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... Revision 4.1 January 2008 page 111. Access Description R/W Pulse Train These eight bits are the first bits shifted out from and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.70 7Dh: Pulse Train Control 61 (PTC61) This register, along with the PTC60 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length and the on/off time to derive a specific visual indication. The PTC60 register provides eight of the twelve bits available in the programmable pulse train. ...
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... Revision 4.1 January 2008 page 111. Access Description R/W Pulse Train These eight bits are the first bits shifted out from and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time 133 VSC055-01 Data Sheet ...
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... VSC055-01 Data Sheet 3.2.72 7Fh: Pulse Train Control 71 (PTC71) This register, along with the PTC70 register, provides a user-programmable LED flashing pulse train. The user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific visual indication. The PTC70 register provides eight of the twelve bits available in the programmable pulse train. ...
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... Port 2). The lowest priorities are the bit control features found in the GPD, DD, and BCP registers. Only one mode of operation should be enabled for each I/O pin at any time mode change is desired, first disable the existing mode, then enable the new mode 133 VSC055-01 Data Sheet Table 5, page 80. Table 4, page 80. ...
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... VSC055-01 Data Sheet Bit Bit Label 4:2 FS2 GPD Access Description R/W Function Select These three bits, along with the PTE, DD, and GPD bits, determine the function of each I/O pin. When configured as an output, the FS2-0 bits determine the rate at which the high current drive I/O toggles, providing a simple mechanism for flashing LEDs. ...
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... Pulse Train 1 selected, drive Pulse Train 2 selected, drive Pulse Train 3 selected, drive Pulse Train 4 selected, drive Pulse Train 5 selected, drive 133 VSC055-01 Data Sheet SS only SS only SS only SS only SS only SS only SS only SS only ...
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... VSC055-01 Data Sheet Table 5. LED Options (continued) PTE FS2 FS1 Table 6 shows the available input edge combinations. Table 6. Input Edge Combinations FS2 FS1 3.2.74 88h: Pulse Train Control 80 (PTC80) This register, along with the PTC81 register, provides a user-programmable LED flashing pulse train that defines the 0 ...
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... R/W Pulse Train These four bits are the last bits shifted out from and define the on/off time for the flash rate. 1: defines LED on time. 0: defines LED off time 133 VSC055-01 Data Sheet ...
Page 83
... VSC055-01 Data Sheet 3.2.76 8Ch: Pulse Train Control 90 (PTC90) This register, along with the PTC91 register, provides a user-programmable LED flashing pulse train that defines the 0.25 Hz flash rate (selectable in the bit control registers) at power on. The user can adjust the pulse duration, pulse train length, and the on/off time to derive a specific visual indication. The PTC90 register provides eight of the twelve bits available in the programmable pulse train ...
Page 84
... R/W Pulse Train These four bits are the last bits shifted out from and define the on/off time for the flash rate. 1: defines an LED on time. 0: defines an LED off time 133 VSC055-01 Data Sheet ...
Page 85
... VSC055-01 Data Sheet 3.2.78 90h-97h: Bit Control Port 1 (BCP10-BCP17) These eight registers function the same as the Bit Control Port 0 register except they provide individual bit control for the Port 1 I/O pins. All register bits are identical from a control and status perspective, with the only difference being the individual I/O pin controlled and the presence of the bypass function ...
Page 86
... After a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is the level applied to the pin since each pin is an input by default 133 VSC055-01 Data Sheet DD with an SS Table 5, page 80 ...
Page 87
... VSC055-01 Data Sheet 3.2.79 98h-9Fh: Pulse-Width Modulation Control (PWMC0-PWMC7) These eight registers provide a pulse-width modulated output that can optionally be made available on each of the Port 1 I/O pins. Configurations for these I/O pins that may have been previously enabled through other control registers are overridden if either one or both of the PWBF bits are set. The PWBF bits have higher priority control over the Port 1 I/O pins than any other mode of operation ...
Page 88
... VSC055-01 Data Sheet ...
Page 89
... VSC055-01 Data Sheet 3.2.80 A0h-A7h: Bit Control Port 2 (BCP20-BCP27) These eight registers function the same as the Bit Control Port 0 registers except they provide individual bit control for the Port 2 I/O pins. All register bits are identical from a control and status perspective, with the only difference being the individual I/O pin controlled and the presence of the bypass function ...
Page 90
... After a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is the level applied to the pin since each pin is an input by default 133 VSC055-01 Data Sheet with an DD ...
Page 91
... VSC055-01 Data Sheet 3.2.81 B0h-B7h: Bit Control Port 3 (BCP30-BCP37) These eight registers function the same as the Bit Control Port 0 registers except they provide individual bit control for the Port 3 I/O pins. All register bits are identical from a control and status perspective, with the only difference being the individual I/O pin controlled and the presence of the bypass function ...
Page 92
... After a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is the level applied to the pin since each pin is an input by default 133 VSC055-01 Data Sheet with an DD ...
Page 93
... VSC055-01 Data Sheet 3.2.82 C0h-C7h: Bit Control Port 4 (BCP40-BCP47) These eight registers function the same as the Bit Control Port 0 registers except they provide individual bit control for the Port 4 I/O pins. All register bits are identical from a control and status perspective, with the only difference being the individual I/O pin controlled and the presence of the bypass function ...
Page 94
... After a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is the level applied to the pin since each pin is an input by default 133 VSC055-01 Data Sheet DD with an SS Table 5, page 80 ...
Page 95
... VSC055-01 Data Sheet 3.2.83 CCh: General-Purpose Timer Count 0 (GPTC0) The following table shows the bit assignments for the General-Purpose Timer Count 0 register. Register Name: GPTC0 Address: CCh Reset Value: 0000_0000b Bit Bit Label 7:0 TC7-0 3.2.84 CDh: General-Purpose Timer Count 1 (GPTC1) The following table shows the bit assignments for the General-Purpose Timer Count 1 register. ...
Page 96
... MHz core clock. When the 24-bit timer reaches a value of zero, the interrupt output of the VSC055-01 is asserted. The timer then re-loads with the initial count value found in the GPTC0, GPTC1, and GPTC2 registers and begins counting down again ...
Page 97
... VSC055-01 Data Sheet 3.2.87 D0h-D7h: Bit Control Port 5 (BCP50-BCP57) These eight registers function the same as the eight Bit Control Port 0 registers except that they relate to the Port 5 I/O pins. In addition, the control of the individual I/O pins assigned to these registers can be overridden by the PBC8, PBC9, PBC10, and PBC11 registers when port bypass control is required. For information about the functionality of the Bit Control Port 0 registers, see (BCP00-BCP07),” ...
Page 98
... After a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is the level applied to the pin since each pin is an input by default 133 VSC055-01 Data Sheet with an DD with an external ...
Page 99
... VSC055-01 Data Sheet 3.2.88 E0h-E7h: Bit Control Port 6 (BCP60-BCP67) These eight registers function the same as the eight Bit Control Port 0 registers except that they relate to the Port 6 I/O pins. In addition, the control of the individual I/O pins assigned to these registers can be overridden by the PBC12, PBC13, PBC14, and PBC15 registers when port bypass control is required. For information about the functionality of the Bit Control Port 0 registers, see (BCP00-BCP07),” ...
Page 100
... After a reset or power on, this register bit is set to a binary 1, but the value returned from a register read is the level applied to the pin since, by default, each pin is an input. 100 of 133 VSC055-01 Data Sheet with an DD with an external ...
Page 101
... Master Interface uses a four-cycle state machine to drive the SCL output. All timings for the Master Interface are based on this four-cycle state machine. The frequency of operation desired is based on the divider value along with the core clock frequency of the VSC055-01. For the various divider values that result in common frequencies of operation, see Divider ...
Page 102
... Reserved. R/W These three bits determine the port selected for Master mode two-wire serial transfers. Valid ports for the VSC055-01 include Port 4 (4h), Port 5 (5h), Port 6 (6h), and Port 7 (7h). Values other than those specified do not enable the interface. After a reset or power on, these bits are cleared. ...
Page 103
... This read-only bit indicates the current state of the master serial interface SDA input. 1: SDA signal is tri-stated and is being pulled HIGH by an external pull-up resistor. 0: device (including the VSC055-01) is actively driving a low value onto the SDA wire. After a reset or power on, this bit is unknown. R/W Serial Data Output This bit provides low-level drive control of the master serial interface SDA signal ...
Page 104
... SDA while SCL is HIGH) prior to transferring the immediate byte. This operation should be initiated at the beginning of a telegram and as required for restarts during read transactions. After a reset or power on, this bit is cleared. --> --> 104 of 133 VSC055-01 Data Sheet MID register (data) MID register (data) ...
Page 105
... VSC055-01 Data Sheet (repeat steps 5-8 if there are multiple register address bytes or data bytes) Send data written to slave device register with a stop: 9) <data byte> 10) Write 5Ah to the MIC register (command) 11) Poll the MIS register until bit 12) Test bit 1, if set continue, if clear then the slave device ...
Page 106
... Drive SCL low by setting bit 0 low in the MILC register. 8) Release SCL by setting bit 0 high in the MILC register (clock out one data bit) 9) Release SDA (stop-condition) by setting bit 6 high in the MIC register 10) Begin normal two-wire serial transfers Revision 4.1 January 2008 106 of 133 VSC055-01 Data Sheet ...
Page 107
... VSC055-01 Data Sheet 3.2.93 ECh: Master Interface Low-Level Control (MILC) The following table shows the bit assignments for the Master Interface Low-Level Control register. Register Name: MILC Address: ECh Reset Value: XXXX_XXX1b Bit Bit Label 7:1 RES 0 SCLO 3.2.94 EDh: Master Interface Status (MIS) The following table shows the bit assignments for the Master Interface Status register ...
Page 108
... When this bit is set, the FS bits select one of eight pulse train circuits instead of the normal fixed-rate LED flashing circuits or the normal output drive mode. For the various LED drive control modes, see After a reset or power on, this bit is cleared. 108 of 133 VSC055-01 Data Sheet . “80h- Table 5, ...
Page 109
... VSC055-01 Data Sheet Bit Bit Label 6:5 BYP1-0 4:2 FS2 Access Description R/W Bypass Select These two bits determine the bypass function of the odd-numbered I/O pins P0.7, P0.5, P0.3, and P0.1. Setting either or both of these bits causes the I/O pin to be configured as an output that reflects the input state of the corresponding even-numbered I/O pins P0 ...
Page 110
... To clear the current interrupt and de-assert the INT# pin, a value of FFh must be written to this register higher binary value or lower priority interrupt source is still active, the new value is generated and the INT# pin re-asserts. 110 of 133 VSC055-01 Data Sheet ...
Page 111
... VSC055-01 Data Sheet 3.2.98 FCh: Backplane Controller Test (BCT) The following table shows the bit assignments for the Backplane Controller Test register. Register Name: BCT Address: FCh Reset Value: 0XXX_X000b Bit Bit Label 7 SRST 6:3 RES 2 FSB 1 FRB 0 SIFB 3.2.99 FDh: Clock Select Control (CSC) The following table shows the bit assignments for the Clock Select Control register ...
Page 112
... Synchronization Period These four bits determine the synchronization period of the device. The synchronization function can be used by a single VSC055-01 device for internal synchronization or by multiple VSC055-01devices for chip-to-chip synchronization. At the end of the synchronization period, a pulse is generated on the SYNC# pin that causes this device, as well as all other devices attached to the SYNC# pin, to re-synchronize their internal dividers ...
Page 113
... For example, if 66.67 MHz is the input clock frequency, the CKSEL2 and CKSEL1 inputs would be connected to V 11.11 MHz internal clock, which is within the 8.0 MHz to 12.5 MHz operating range of the VSC055-01. The 11.11 MHz internal clock is then divided by 3 (3.7 MHz) and then divided by 185 (B8h is loaded into the CDC register) to achieve 20.02 kHz. ...
Page 114
... Generally, changes to bits 3:0 reflect a minor revision, and changes to bits 7:4 reflect a major revision or different device type. Firmware should check this register to determine the current capabilities of the device. 114 of 133 VSC055-01 Data Sheet CDC Register 20 kHz Clock 133 (84h) 20 ...
Page 115
... The following section shows the DC specifications for the VSC055-01 device. The tables are grouped by functionality. 4.1.1 General-Purpose I/O Ports The following table lists the DC specifications for the VSC055-01 when the device is configured in general-purpose I/O port mode for ports P7, P6, P5, P4, P3, P2, P1, and P0. Table 10. General-Purpose I/O Ports Parameter ...
Page 116
... V 0 – Symbol Minimum Maximum V 2.0 5 – 0 0.8 T– – 116 of 133 VSC055-01 Data Sheet Unit Condition µ µA Unit Condition µ ...
Page 117
... VSC055-01 Data Sheet 4.1.4 Interrupt Output The following table lists the DC specifications for the interrupt output, INT#. Table 14. Interrupt Output Parameter Output LOW voltage 4.1.5 Test and Synchronization Clock Control Inputs The following table lists the DC specifications for the test and synchronization clock control inputs, TEST, SYNCEN, CKSEL2, CKSEL1, and CKSEL0 ...
Page 118
... 0 – Symbol Minimum Maximum V V – 118 of 133 VSC055-01 Data Sheet Maximum Unit – Unit Condition µ Unit Condition ...
Page 119
... VSC055-01 Data Sheet 4.2 AC Characteristics The following section shows the AC specifications for the VSC055-01 device. 4.2.1 External Clock Timing The following section contains the external clock cycle timing waveform and parameters for low- frequency and high-frequency operation for the external clock. Figure 4. Clock Cycle Timing Waveform The following table lists the AC characteristics in low-frequency operation ...
Page 120
... Standard Mode Symbol Minimum Maximum f 0 100 SCL t 4.7 BUF t 4.0 HD:STA t 4.7 LOW t 4.0 HIGH t 4.7 SU:STA t 0 HD:DAT t 250 SU:DAT t 4.0 SU:STO 120 of 133 VSC055-01 Data Sheet t HD:STO t BUF Fast Mode Minimum Maximum Unit 0 400 kHz 1.3 µs 0.6 µs 1.3 µs 0.6 µs 0.6 µs 0 0.9 µs 100 µs 0.6 ...
Page 121
... VSC055-01 Data Sheet 4.3 Operating Conditions The following table lists the recommended operating conditions for the VSC055-01 device. Table 23. Recommended Operating Conditions Parameter Power supply voltage (1) Operating temperature 1. Lower limit of specification is ambient temperature, and upper limit is case temperature. 4.4 Maximum Ratings Stresses listed under Absolute Maximum Ratings may be applied to devices one at a time without causing permanent damage ...
Page 122
... Two-Wire Serial Interface Operation The following illustration shows the two-wire serial interface read and write capabilities of the VSC055-01. All operations can be performed in any order. Figure 6. Two-Wire Serial Interface Operation S Slave T Address Address ( Multi-Byte S Write Slave ...
Page 123
... VSC055-01 Data Sheet 4.6 Oscillator Requirements The VSC055-01 can use an external 3.3-V, 8.0 MHz to 12.5 MHz clock source connected to the OSCI pin, with CKSEL2 tied OSCI pin with CKSEL2 tied to V clock source can be connected to the OSCI pin with CKSEL2 tied to V Alternatively, an 8.0 MHz to 12.5 MHz crystal and several passive components may be used. ...
Page 124
... Pin Diagram The VSC055-01 has 100 pins. All pins have been placed to optimize their connection to external components. Power and ground distribution is also optimized for core and high current I/O connections. All high current I/O pins, serial interface pins, and the interrupt output are 5-V tolerant. Connect 3.3 V power supply with no more than ± ...
Page 125
... Figure 10. Pin Diagram, Top View P0.2 1 VSS VDD VDD2 P0.1 P0.0 TEST ASEL CKOUT OSCO OCSI VSS VDD CKSEL0 CKSEL1 CKSEL2 SYNC# 20 SYNCEN SCL SDA INT# P7.7 P7.6 VSS2 VSS VDD P7.5 30 100 90 VSC055- 125 of 133 81 80 P2.5 VDD VSS VSS2 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 70 P3.5 P3.6 P3.7 VDD VSS P4.0 P4.1 P4.2 P4.3 60 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 VDD2 VDD VSS 51 P5 ...
Page 126
... Input Oscillator Input This pin is connected to one side of an external 8.0 MHz to 12.5 MHz crystal to produce the clock required for the VSC055-01. 8.0 MHz, 8.33 MHz, 8.854 MHz and 10.0 MHz are pre-defined fixed frequencies supported by the CKSEL pins when using a crystal. An alternate external 3.3 V, 8.0MHz to 12.5MHz or 32.0MHz to 75.0MHz clock source can be connected to this pin ...
Page 127
... Clock Select These three pins determine the input frequency of the clock or crystal that is connected to the VSC055-01 on the OSCI and OSCO pins. These pins also enable or disable the internal system clock divider and adjust the flash rate and fan tach dividers to maintain the proper internal clock rates ...
Page 128
... Through bit control register setup, each odd-numbered bit of this port can be enabled as an output, which on a pair-by-pair basis, reflects the current state of each even-numbered bit of this port. Individual control is provided that allows programming each output as a totem pole or an open-drain/source driver. 128 of 133 VSC055-01 Data Sheet ...
Page 129
... VSC055-01 Data Sheet Table 30. I/O Ports (continued) Pin Name Pin Number P4.7 57 P4.6 58 P4.5 59 P4.4 60 P4.3 61 P4.2 62 P4.1 63 P4.0 64 P5.7 46 P5.6 47 P5.5 48 P5.4 49 P5.3 50 P5.2 51 P5.1 55 P5.0 56 P6.7 36 P6.6 37 P6.5 38 P6.4 39 P6.3 42 P6.2 43 P6.1 44 P6.0 45 I/O Description Bidirectional I/O Port 4, Bypass I/Os Port shared 8-bit bidirectional I/O port that can be used as a general-purpose I/O port or as Port Bypass control. The user can select between an input, totem pole output, or open-drain or open- source output ...
Page 130
... These pins are the power sources for the digital core logic and receivers of all non-analog input and bidirectional pins. Digital Core Ground Ground These pins are the ground connections for the digital core logic and receivers of all non-analog input and bidirectional pins. 130 of 133 VSC055-01 Data Sheet for normal operation. SS ...
Page 131
... Data Sheet 6 Package Information The VSC055-01 device is available in two package types. VSC055KM- 100-pin, plastic quad flat package (QFP) with body width body length, 2.7 mm body thickness, 0.65 mm pitch, and 3.1 mm maximum height. The device is also available in a lead(Pb)-free package, VSC055XKM-01. ...
Page 132
... Figure 11. Package Drawing Top View Pin 1 Indicator See detail B Detail A R2 radius R1 radius All dimensions and tolerances in millimeters. Revision 4.1 January 2008 Side View See detail A Seating plane Detail B 132 of 133 VSC055-01 Data Sheet Dimensions and Tolerances Reference Minimum Nominal Maximum A 3.04 3.10 A1 0.10 0.23 0.36 A2 2.57 2.71 2. ...
Page 133
... Data Sheet 7 Ordering Information The VSC055-01 device is available in two package types. VSC055KM- 100-pin plastic QFP. The device is also available in a lead(Pb)-free package, VSC055XKM-01. Lead(Pb)-free products from Maxim comply with the temperatures and profiles defined in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard. ...