DS21352 Maxim Integrated Products, DS21352 Datasheet
DS21352
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DS21352 Summary of contents
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... CMOS DESCRIPTION The DS21352/552 T1 single-chip transceiver contains all of the necessary functions for connection to T1 lines whether they are DS1 long haul or DSX–1 short haul. The clock recovery circuitry automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX–1 line build outs as well as CSU line build-outs of -7 ...
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TABLE OF CONTENTS 1. LIST OF FIGURES .........................................................................................................................5 2. LIST OF TABLES ...........................................................................................................................6 3. INTRODUCTION............................................................................................................................7 3.1 FUNCTIONAL DESCRIPTION..............................................................................................8 3.2 DOCUMENT REVISION HISTORY....................................................................................10 4. PIN DESCRIPTION ......................................................................................................................11 4.1 PIN FUNCTION DESCRIPTION..........................................................................................17 4.1.1 Transmit Side Pins ........................................................................................................17 4.1.2 Receive Side Pins ..........................................................................................................20 ...
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SIGNALING OPERATION..........................................................................................................58 10.1 PROCESSOR-BASED SIGNALING ....................................................................................58 10.2 HARDWARD-BASED SIGNALING ...................................................................................60 10.2.1 Receive Side.................................................................................................................60 10.2.2 Transmit Side...............................................................................................................61 11. PER-CHANNEL CODE (IDLE) GENERATION ......................................................................61 11.1 TRANSMIT SIDE CODE GENERATION ...........................................................................62 11.1.1 Fixed Per-Channel Idle Code Insertion ......................................................................62 11.1.2 Unique Per-Channel Idle ...
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LINE INTERFACE FUNCTION .................................................................................................85 16.1 RECEIVE CLOCK AND DATA RECOVERY ....................................................................85 16.2 TRANSMIT WAVE SHAPING AND LINE DRIVING.......................................................86 16.3 JITTER ATTNUATOR..........................................................................................................86 16.4 PROTECTED INTERFACES................................................................................................92 16.5 RECEIVE MONITOR MODE...............................................................................................95 17. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION ............96 18. TRANSMIT ...
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... Figure 16-3 TRANSMIT WAVEFORM TEMPLANE............................................................................89 Figure 16-4 JITTER TOLERANCE .........................................................................................................91 Figure 16-5 JITTER ATTENUATION ....................................................................................................91 Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21552...........................................93 Figure 16-7 PROTECTED INTERFACE EXAMPLE FOR TE DS21352..............................................94 Figure 16-8 TYPICAL MONITOR PORT APPLICATION....................................................................95 Figure 19-1 JTAG FUNCTIONAL BLOCK DIAGRAM......................................................................100 Figure 19-2 TAP CONTROLLER STATE DIAGRAM ........................................................................103 Figure 20-1 IBO BASIC CONFIGURATION USING 4 SCTS ............................................................110 Figure 21-1 RECEIVE SIDE D4 TIMING ...
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LIST OF TABLES Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER................................................................11 Table 4-2 PIN DESCRIPTION SORTED BY PIN SYMBOL ................................................................14 Table 5-1 REGISTER MAP SORTED BY ADDRESS...........................................................................29 Table 6-1 DEVICE ID BIT MAP .............................................................................................................33 Table 6-2 OUTPUT PIN TEST ...
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... INTRODUCTION The DS21352/552 are 3.3V/5V superset versions of the popular DS2152 T1 single-chip transceiver offering the new features listed below. All of the original features of the DS2152 have been retained and software created for the original devices is transferable into the DS21352/552. NEW FEATURES (after the DS2152) § ...
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... The clock applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock. The RSYSCLK can be a bursty clock with speeds up to 8.192 MHz. The transmit side of the DS21352/552 is totally independent from the receive side in both the clock requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic store if necessary ...
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Figure 3-1 SCT BLOCK DIAGRAM CI RPOSI RCLKI RNEGI RNEGO RCLKO RPOSO 8XCLK MHz XTALD MCLK Payload Loopback Framer Loopback Remote Loopback Jitter Attenuator 12.352 Either transmit or receive path Local Loopback Receive Line I/F Clock / Data Recovery 9 ...
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DOCUMENT REVISION HISTORY Revision 12-10-98 Initial Release 12-18-98 Add LIUODO (LIU Open Drain Output) to CCR7.0 Add CDIG (Customer Disconnect Indication Generator) to CCR7.1 Add LIUSI (Line Interface Unit Synchronization Interface) to CCR7.2 Correct IBO register bit functions order ...
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PIN DESCRIPTION Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER PIN SYMBOL 1 RCHBLK 2 JTMS 3 8MCLK 4 JTCLK 5 JTRST 6 RCL 7 JTDI JTDO 11 BTS 12 LIUC 13 8XCLK 14 ...
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TDATA 51 TSYSCLK 52 TSSYNC 53 TCHCLK MUX 56 D0/AD0 57 D1/AD1 58 D2/AD2 59 D3/AD3 60 DVSS 61 DVDD 62 D4/AD4 63 D5/AD5 64 D6/AD6 65 D7/AD7 ...
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Table 4-1 PIN DESCRIPTION SORTED BY PIN SYMBOL PIN SYMBOL 3 8MCLK 13 8XCLK ALE (AS)/A7 11 BTS CS* 56 ...
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RCLKI 89 RCLKO 74 RD*(DS*) 85 RDATA 97 RFSYNC 79 RLCLK 78 RLINK 99 RLOS/LOTC 96 RMSYNC 87 RNEGI 90 RNEGO 86 RPOSI 91 RPOSO 17 RRING 95 RSER 94 RSIG 93 RSIGF 98 RSYNC 100 RSYSCLK 16 RTIP ...
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PIN FUNCTION DESCRIPTION 4.1.1 TRANSMIT SIDE PINS Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 1.544 MHz primary clock. Used to clock data through the transmit side formatter. Signal Name: TSER Signal Description: Transmit Serial Data ...
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... Signal Type: Input / Output A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via TCR2.2, the DS21352/552 can be programmed to output either a frame or multiframe pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output double–wide pulses at signaling frames. See Section 20 for details. ...
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TRANSMIT SIDE PINS (cont.) Signal Name: TNEGO Signal Description: Transmit Negative Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit side formatter. This pin is normally tied to ...
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RECEIVE SIDE PINS Signal Name: RLINK Signal Description: Receive Link Data Signal Type: Output Updated with either FDL data (ESF bits (D4 bits (ZBTSI) one RCLK before the start of a frame. See Section 20 ...
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RECEIVE SIDE PINS (cont.) Signal Name: RFSYNC Signal Description: Receive Frame Sync Signal Type: Output An extracted 8 kHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries. Signal Name: RMSYNC Signal Description: Receive Multiframe ...
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Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI. Signal Name: RNEGO Signal Description: Receive Negative Data Input Signal Type: Output Updated on the rising edge of ...
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... Signal Description: Framer Mode Select Signal Type: Input Selects the DS2152 mode when high or the DS21352/552 mode when low. If high, the JTRST is internally pulled low. If low, JTRST has normal JTAG functionality. This pin has a 10k pull up resistor. Signal Name: TEST Signal Description: 3– ...
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PARALLEL CONTROL PORT PINS (cont.) Signal Name: CS* Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS active low signal. Signal Name: ALE(AS)/A7 Signal Description: Address Latch Enable(Address ...
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JTAG TEST ACCESS PORT PINS Signal Name: JTRST Signal Description: IEEE 1149.1 Test Reset Signal Type: Input If FMS = 1: JTAG functionality is not available and JTRST is held LOW internally. If FMS = 0: JTAG functionality is ...
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LINE INTERFACE PINS Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A 1.544 MHz (50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and ...
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... Should be tied to the DVDD and TVDD pins. Signal Name: TVDD Signal Description: Transmit Analog Positive Supply Signal Type: Supply 5.0 volts +/-5% (DS21552) or 3.3 volts +/-5% (DS21352). Should be tied to the RVDD and DVDD pins. Signal Name: DVSS Signal Description: Digital Signal Ground Signal Type: Supply Should be tied to the RVSS and TVSS pins ...
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... Line Code Violation Count Line Code Violation Count Path Code Violation Count 1 SEE NOTE Path Code violation Count 2 REGISTER NAME REGISTER NAME 26 of 137 DS21352/DS21552 REGISTER ABBREVIATION HCR HSR HIMR RHIR RBOC RHFR THIR TBOC THFR TEST2 (set to 00h) CCR7 – ...
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... Transmit Channel 5 55 R/W Transmit Channel 6 56 R/W Transmit Channel 7 57 R/W Transmit Channel 8 58 R/W Receive Channel 17 59 R/W Receive Channel 18 REGISTER NAME REGISTER NAME 27 of 137 DS21352/DS21552 REGISTER ABBREVIATION MOSCR2 RFDL RMTCH1 RMTCH2 RCR1 RCR2 RMR1 RMR2 RMR3 CCR3 RIR2 TCBR1 TCBR2 TCBR3 TCR1 TCR2 ...
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... R/W Receive Channel 10 8A R/W Receive Channel 11 8B R/W Receive Channel 12 8C R/W Receive Channel 13 8D R/W Receive Channel 14 8E R/W Receive Channel 15 REGISTER NAME 28 of 137 DS21352/DS21552 RC19 RC20 RC21 RC22 RC23 RC24 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RCBR1 ...
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... The LIRST (CCR7.7) should be toggled from zero to one to reset the line interface circuitry (it will take the DS21352/552 about 40ms to recover from the LIRST bit being toggled). Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bit should be toggled from a zero to a one (this step can be skipped if the elastic stores are disabled) ...
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Bit 6 IDR.6 Bit 6. Bit 5 IDR.5 Bit 5. Bit 4 IDR.4 Bit 4. ID3 IDR.3 Chip Revision Bit 3. MSB of a decimal code that represents the chip revision. ID2 IDR.1 Chip Revision Bit ...
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... Resync. When toggled from low to high, a resynchronization of the receive side framer is initiated. Must be cleared and set again for a subsequent resync. Bit 6 Bit OOF2 SYNCC SYNCT 31 of 137 DS21352/DS21552 Bit (LSB) SYNCE RESYNC ...
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RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex) (MSB) RCS RZBTSI RSDW SYMBOL POSITION RCS RCR2.7 RZBTSI RCR2.6 RSDW RCR2.5 RSM RCR2.4 RSIO RCR2.3 RD4YM RCR2.2 FSBE RCR2.1 MOSCRF RCR2.0 RSM RSIO NAME AND DESCRIPTION Receive Code Select idle ...
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TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex) (MSB) LOTCMC TFPT SYMBOL POSITION LOTCMC TCR1.7 TFPT TCR1.6 TCPT TCR1.5 TSSE TCR1.4 GB7S TCR1.3 TFDLS TCR1.2 TBL TCR1.1 TYEL TCR1.0 NOTE: For a description of how the bits in TCR1 affect the ...
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... I/O pins and parallel port pins force all output pins low (including all I/O pins except parallel port pins force all output pins high (including all I/O pins except parallel port pins) TSDW TSM TSIO 34 of 137 DS21352/DS21552 (LSB) TD4YM TB7ZS ...
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... Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing applications PLB situation, the DS21352/552 will loop the 192 bits of pay-load data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pat- tern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the DS21352/552 ...
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All receive side signals will take on timing synchronous with TCLK instead of RCLKI. Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will cause an unstable condition. CCR2: COMMON ...
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Loss of Transmit Clock (LOTC) RSMS CCR3.4 RSYNC Multiframe Skip Control. Useful in framing format conversions from D4 to ESF. This function is not available when the receive side elastic store is enabled RSYNC will output ...
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... Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits respectively. When the CCR3.3 is set to one, the DS21352 will force the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements ...
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CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex) (MSB) RSRE RPCSI RFSA1 SYMBOL POSITION RSRE CCR4.7 RPCSI CCR4.6 RFSA1 CCR4.5 RFE CCR4.4 RFF CCR4.3 THSE CCR4.2 TPCSI CCR4.1 TIRFS CCR4.0 RFE RFF NAME AND DESCRIPTION Receive Side Signaling Re–Insertion Enable. See ...
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CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex) (MSB) TJC LLB LIAIS SYMBOL POSITION TJC CCR5.7 LLB CCR5.6 LIAIS CCR5.5 TCM4 CCR5.4 TCM3 CCR5.3 TCM2 CCR5.2 TCM1 CCR5.1 TCM0 CCR5.0 TCM4 TCM3 NAME AND DESCRIPTION Transmit Japanese CRC6 Enable ...
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CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex) (MSB) RJC RESA SYMBOL POSITION RJC CCR6.7 RESA CCR6.6 TESA CCR6.5 RCM4 CCR6.4 RCM3 CCR6.3 RCM2 CCR6.2 RCM1 CCR6.1 RCM0 CCR6.0 TESA RCM4 RCM3 NAME AND DESCRIPTION Receive Japanese CRC6 Enable ...
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... RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO pins. Data will continue to pass through the receive side framer of the DS21352/552 as it would normally and the data from the transmit side formatter will be ignored. Please see Figure 3-1 for more details. ...
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... The user will always proceed a read of any of the nine registers with a write. The byte written to the register will inform the DS21352/552 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on ...
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RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex) (MSB) COFA 8ZD SYMBOL POSITION COFA RIR1.7 8ZD RIR1.6 16ZD RIR1.5 RESF RIR1.4 RESE RIR1.3 SEFE RIR1.2 B8ZS RIR1.1 FBE RIR1.0 RIR2: RECEIVE INFORMATION REGISTER 2 (Address=31 Hex) (MSB) RLOSC LRCLC TESF SYMBOL ...
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... Not Assigned. Could be any value when read. – RIR3.0 Not Assigned. Could be any value when read. Table 7-1 RECEIVE T1 LEVEL INDICATION RL1 RL0 TYPICAL LEVEL RECEIVED 137 DS21352/DS21552 + –7.5 dB –7 –15 dB – –22.5 dB less than –22.5 dB ...
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SR1: STATUS REGISTER 1 (Address=20 Hex) (MSB) LUP LDN LOTC SYMBOL POSITION LUP SR1.7 LDN SR1.6 LOTC SR1.5 RSLIP SR1.4 RBL SR1.3 RYEL SR1.2 LRCL SR1.1 RLOS SR1.0 RSLIP RBL NAME AND DESCRIPTION Loop Up Code Detected. Set when the ...
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... The blue alarm criteria in the DS21352/552 has been set to achieve this performance recommended that the RBL bit be qualified with the RLOS bit. ...
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... Receive FDL Match Occurrence. Set when the RFDL matches either RFDLM1 or RFDLM2. Receive FDL Abort. Set when eight consecutive one’s are received in the FDL. Receive Signaling Change. Set when the DS21352/552 detects a change of state in any of the robbed–bit signaling bits 137 ...
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IMR1: INTERRUPT MASK REGISTER 1 (Address=7F Hex) (MSB) LUP LDN LOTC SYMBOL POSITION LUP IMR1.7 LDN IMR1.6 LOTC IMR1.5 SLIP IMR1.4 RBL IMR1.3 RYEL IMR1.2 LRCL IMR1.1 RLOS IMR1.0 SLIP RBL NAME AND DESCRIPTION Loop Up Code Detected ...
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IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex) (MSB) RMF TMF SYMBOL POSITION RMF IMR2.7 TMF IMR2.6 SEC IMR2.5 RFDL IMR2.4 TFDL IMR2.3 RMTCH IMR2.2 RAF IMR2.1 RSC IMR2.0 8. ERROR COUNT REGISTERS There are a set of three counters that ...
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... LCV12 LCV11 LCV10 LCV4 LCV3 LCV2 B8ZS ENABLED (CCR2.2) no BPVs no BPVs + 16 consecutive zeros yes BPVs (B8ZS code words not counted) yes BPV’ consecutive zeros 51 of 137 DS21352/DS21552 (LSB) LCV9 LCV8 LCVCR1 LCV1 LCV0 LCVCR2 WHAT IS COUNTED IN THE LCVCRs ...
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... ESF (note 1) CRC/FB11 CRC/FB10 CRC/FB4 CRC/FB3 CRC/FB2 COUNT Fs ERRORS (RCR2.1) no errors in the Ft pattern yes errors in both the Ft & Fs patterns don’t care errors in the CRC6 code words 52 of 137 DS21352/DS21552 (LSB) CRC/FB9 CRC/FB8 PCVCR1 CRC/FB1 CRC/FB0 PCVCR2 WHAT IS COUNTED IN THE PCVCRs ...
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... CRC/FB3 CRC/FB2 COUNT MOS OR F–BIT ERRORS (RCR2.0) MOS number of multiframes out of sync F–Bit errors in the Ft pattern MOS number of multiframes out of sync F–Bit errors in the FPS pattern 53 of 137 DS21352/DS21552 (LSB) (note 1) (note 1) MOSCR1 CRC/FB1 CRC/FB0 MOSCR2 WHAT IS COUNTED IN THE MOSCRs ...
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DS0 MONITORING FUNCTION The device has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which ...
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TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=1A Hex) (MSB SYMBOL POSITION B1 TDS0M.7 B2 TDS0M.6 B3 TDS0M.5 B4 TDS0M.4 B5 TDS0M.3 B6 TDS0M.2 B7 TDS0M.1 B8 TDS0M.0 CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex) [repeated here from section 6 ...
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B5 RDS0M.3 B6 RDS0M.2 B7 RDS0M.1 B8 RDS0M.0 10. SIGNALING OPERATION Processor based (i.e., software based) signaling access and hardware based access are available. Processor based access and hardware based access can be used simultaneously if necessary. The processor based ...
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RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address= Hex) (MSB) A(8) A(7) A(6) A(16) A(15) A(14) A(24) A(23) A(22) B(8) B(7) B(6) B(16) B(15) B(14) B(24) B(23) B(22) A/C(8) A/C(7) A/C(6) A/C(16) A/C(15) A/C(14) A/C(24) A/C(23) A/C(22) B/D(8) B/D(7) ...
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TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address= Hex (MSB) A(8) A(7) A(6) A(16) A(15) A(14) A(24) A(23) A(22) B(8) B(7) B(6) B(16) B(15) B(14) B(24) B(23) B(22) A/C(8) A/C(7) A/C(6) A/C(16) A/C(15) A/C(14) A/C(24) A/C(23) A/C(22) B/D(8) B/D(7) ...
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In this mode, the elastic store must be enabled however the backplane clock can be either 1.544 MHz or 2.048 MHz. If the signaling re–insertion mode is enabled, the user can control which channels have signaling re– insertion ...
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TRANSMIT SIDE CODE GENERATION In the transmit direction there are two methods by which channel data from the backplane can be overwritten with data generated by the framer. The first method which is covered in Section 11.1 was a ...
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TC1 TO TC24: TRANSMIT CHANNEL REGISTERS (Address= and Hex) (for brevity, only channel one is shown; see Table 5-1 for other register address) (MSB SYMBOL POSITION C7 TC1.7 C0 TC1.0 TCC1/TCC2/TCC3: TRANSMIT ...
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FIXED PER-CHANNEL IDLE CODE INSERTION The first method on the receive side involves using the Receive Mark Registers (RMR1/2/3) to determine which of the 24 T1 channels should be overwritten with either a 7Fh idle code or with a ...
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RCC1/RCC2/RCC3: RECEIVE CHANNEL CONTROL REGISTER (ADDRESS= Hex) (MSB) CH8 CH7 CH6 CH16 CH15 CH14 CH24 CH23 CH22 SYMBOL POSITION CH24 RCC3.7 CH1 RCC1.0 12. PER–CHANNEL LOOPBACK The Transmit Idle Registers (TIRs) have an alternate function that allows them ...
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ELASTIC STORES OPERATION The device contains dual two–frame (386 bits) elastic stores, one for the receive direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the ...
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TRANSMIT SIDE The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic store is enabled via CCR1.7. A 1.544 MHz (CCR1.4=0) or 2.048 MHz (CCR1.4=1) clock can be applied to the ...
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... BOC controller which can be used for the FDL or for DS0s. Using the HDLC controller for the FDL is covered in Section 15.3.3. To allow for backward compatibility with earlier devices, legacy functionality is maintained for the FDL, which is covered in Section 15.4. Section 15.5 covers D4 and SLC–96 operation. TBOC.6 TDC1 137 DS21352/DS21552 TCR1 ...
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Firmware, which can /Telecom/t1_e1_tools.html), was developed to implement the FDL. incorporates the LAPD protocol and can be used with any of the 51/52/352/552 SCTs. The code for the DS2152 can be used with the 52/352/552 SCTs. 15.3 HDLC AND BOC ...
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... HDLC function when used on DS0 channels status information on transmit HDLC controller enables/disables transmission of BOC codes access to 64–byte HDLC FIFO in transmit direction controls the HDLC function when used on DS0 channels controls the HDLC function when used on DS0 channels 68 of 137 DS21352/DS21552 ...
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Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from the interrupt ...
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TRANSMIT AN HDLC MESSAGE 1) Make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the FIFO is empty by reading the TEMPTY status bit in the TPRM register. 2) Enable ...
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RPE HSR.6 RPS HSR.5 RHALF HSR.4 RNE HSR.3 THALF HSR.2 TNF HSR.1 TMEND HSR.0 NOTE: The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read. Receive Packet End. Set when the HDLC controller detects either ...
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HIMR: HDLC INTERRUPT MASK REGISTER (Address=02 Hex) (MSB) RBOC RPE SYMBOL POSITION RBOC HIMR.7 RPE HIMR.6 RPS HIMR.5 RHALF HIMR.4 RNE HIMR.3 THALF HIMR.2 TNF HIMR.1 TMEND FIMR.0 RPS RHALF RNE NAME AND DESCRIPTION Receive BOC Detector Change of State. ...
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RHIR: RECEIVE HDLC INFORMATION REGISTER (Address=03 Hex) (MSB) RABT RCRCE ROVR SYMBOL POSITION RABT RHIR.7 RCRCE RHIR.6 ROVR RHIR.5 RVM RHIR.4 REMPTY RHIR.3 POK RHIR.2 CBYTE RHIR.1 OBYTE RHIR.0 NOTE: The RABT, RCRCE, ROVR, and RVM bits are latched and ...
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RBOC: RECEIVE BIT ORIENTED CODE REGISTER (Address=04 Hex) (MSB) LBD BD BOC5 SYMBOL POSITION LBD RBOC.7 BD RBOC.6 BOC5 RBOC.5 BOC4 RBOC.4 BOC3 RBOC.3 BOC2 RBOC.2 BOC1 RBOC.1 BOC0 RBOC.0 NOTE: 1. The LBD bit is latched and will be ...
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RHFR: RECEIVE HDLC FIFO (Address=05 Hex) (MSB) RHFR7 RHFR6 RHFR5 SYMBOL POSITION RHFR7 RHFR.7 RHFR6 RHFR.6 RHFR5 RHFR.5 RHFR4 RHFR.4 RHFR3 RHFR.3 RHFR2 RHFR.2 RHFR1 RHFR.1 RHFR0 RHFR.0 THIR: TRANSMIT HDLC INFORMATION (Address=06 Hex) (MSB) – – SYMBOL POSITION – ...
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BOC5 TBOC.5 BOC4 TBOC.4 BOC3 TBOC.3 BOC2 TBOC.2 BOC1 TBOC.1 BOC0 TBOC.0 THFR: TRANSMIT HDLC FIFO (Address=08 Hex) (MSB) THFR7 THFR6 THFR5 SYMBOL POSITION THFR7 THFR.7 THFR6 THFR.6 THFR5 THFR.5 THFR4 THFR.4 THFR3 THFR.3 THFR2 THFR.2 THFR1 THFR.1 THFR0 THFR.0 ...
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RD1 RDC1.1 DS0 Channel Select Bit 1. RD0 RDC1.0 DS0 Channel Select Bit 0. LSB of the DS0 channel select 137 ...
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RDC2: RECEIVE HDLC DS0 CONTROL REGISTER 2 (Address=91 Hex) (MSB) RDB8 RDB7 RDB6 SYMBOL POSITION RDB8 RDC2.7 RDB7 RDC2.6 RDB6 RDC2.5 RDB5 RDC2.4 RDB4 RDC2.3 RDB3 RDC2.2 RDB2 RDC2.1 RDB1 RDC2.0 RDB5 RDB4 NAME AND DESCRIPTION DS0 Bit 8 Suppress ...
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TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address=92 Hex) (MSB) TDS0E - TDS0M SYMBOL POSITION TDS0E TDC1.7 - TDC1.6 TDS0M TDC1.5 TD4 TDC1.4 TD3 TDC1.3 TD2 TDC1.2 TD1 TDC1.1 TD0 TDC1.0 TD4 TD3 NAME AND DESCRIPTION HDLC DS0 Enable. 0 ...
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... LEGACY FDL SUPPORT 15.4.1 OVERVIEW In order to provide backward compatibility to the older DS2152 device, the DS21352/552 maintains the circuitry that existed in the previous generation of the T1 Quad Framer. Sections 15.4.2 and 15.4.3 cover the circuitry and operation of this legacy functionality. In new applications recommended that the HDLC controller and BOC controller described in Section 15 ...
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... If enabled via CCR2.0, the DS21352/552 will automatically look for 5 ones in a row, followed by a zero finds such a pattern, it will automatically remove the zero. If the zero destuffer sees six or more ones in a row followed by a zero, the zero is not removed ...
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... If it finds such a pattern, it will automatically insert a zero after the five ones. The CCR2.0 bit should always be set to a one when the framer is inserting the FDL. More on how to use the DS21352/552 in FDL applications is covered in a separate Application Note. TFDL: TRANSMIT FDL REGISTER (Address=7E Hex) [also used to insert Fs framing pattern in D4 framing mode ...
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... The DS21352/552 contains a digital clock recovery system. See Figure 3-1 and Figure 16-1 for more details. The DS21352/552 couples to the receive T1 twisted pair via a 1:1 transformer. See for details. The 1.544 MHz clock applied to the MCLK pin is internally multiplied by 16 via an internal PLL and fed to the clock recovery system ...
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... Table 16-3. 16.3 JITTER ATTENUATOR The DS21352/552 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register (LICR). The 128 bit mode is used in applications where large excursions of wander are expected ...
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... TRANSFORMER 1. 1. RECOMMENDED VALUE 1:1(receive) and1:2(transmit) 5% 1:1(receive) and1:1.15 or1:1.36(transmit) 5% 600mH minimum 1.0mH maximum 40 pF maximum 1.2 Ohms maximum 85 of 137 DS21352/DS21552 DS21352 / 552 0.1uF DVDD DVSS 0.01uF RVDD 0.1uF RVSS TVDD 0.1uF TVSS XTALD NC 1.544MHz MCLK RESISTOR Rt 0 ohms Ideal, 2 ...
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... Figure 16-2 OPTIONAL CRYSTAL CONNECTIONS DS21352/552 XTALD MCLK NOTES and C2 should lower than two times the nominal loading capacitance of the crystal to adjust for the input capacitance of the DS21352/552. 1.544MHz 137 ...
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Figure 16-3 TRANSMIT WAVEFORM TEMPLATE 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 T1.102/87, T1.403, -0 119 (O ct. 79), & I.431 Tem plate -0.3 -0.4 -0.5 -500 -400 -300 -200 -100 ...
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Table 16-4 PULSE TEMPLATE CORNER POINTS TIME (ns) UI -500 -0.77 -255 -0.39 -175 -0.27 -175 -.027 -150 -0.23 -150 -0.23 -100 -75 -0.12 0 0.00 100 0.15 150 0.23 150 0.23 175 0.27 225 0.35 300 0.46 430 0.66 ...
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Figure 16-4 JITTER TOLERANCE 1K 100 olerance T R 62411 ( Figure 16-5 JITTER ATTENUATION ...
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PROTECTED INTERFACES In certain applications, such as connecting to the PSTN required that the network interface be protected from and resistant to certain electrical conditions. These conditions are divided into two categories, surge and power line cross. ...
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Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21552 R1 Fuse Transmit R2 Line Fuse R3 Fuse Receive R4 Line Fuse Note: The 68uf cap is required to maintain VDD during a transient event. COMPONET D1 – D4 Schottky Diode, International ...
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... Figure 16-7 PROTECTED INTERFACE EXAMPLE FOR THE DS21352 2:1 Fuse Transmit Line Fuse X1 1:1 Fuse Receive Line Fuse X2 Note: The 68uf cap is required to maintain VDD levels during a transient event. COMPONET D1 – D4 Schottky Diode, International Rectifier 11DQ04 C1 0.1uf ceramic in parallel with 10uf tantalum C2 .47 uf, non polarized ceramic construction Fuse 1 ...
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... This, along with the 100 ohm termination (Rt), produces 20dB of loss. The receiver of the DS21352/552 can provide gain to overcome the resistive loss of a monitor connection. This is a purely resistive loss/gain and should not be confused with the cable loss characteristics transmission line ...
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... PROGRAMMABLE IN–BAND LOOP CODE GENERATION AND DETECTION Each framer in the DS21352/552 has the ability to generate and detect a repeating bit pattern that is from one to eight bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition (TCD) register and select the proper length of the pattern by setting the TC0 and TC1 bits in the In– ...
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... RUP1/ RDN1 RUP0/ RDN0 137 DS21352/DS21552 LENGTH SELECTED 0 1 bits 1 2 bits 0 3 bits 1 4 bits 0 5 bits 1 6 bits 0 7 bits 1 8 bits C2 C1 ...
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RUPCD: RECEIVE UP CODE DEFINITION REGISTER (Address=14 Hex) (MSB SYMBOL POSITION C7 RUPCD.7 C6 RUPCD.6 C5 RUPCD.5 C4 RUPCD.4 C3 RUPCD.3 C2 RUPCD.2 C1 RUPCD.1 C0 RUPCD.0 RDNCD: RECEIVE DOWN CODE DEFINITION REGISTER (Address=15 Hex) (MSB ...
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... The DS21352/552 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See Figure 19-1. The DS21352/552 contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. ...
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... The DS21352/552 are enhanced versions of the DS2152 and are backward pin-compatible. The JTAG feature uses pins that had no function in the DS2152. When using the JTAG feature, be sure FMS (pin 76) is tied LOW enabling the newly defined pins of the DS21352/552. Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins ...
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TAP CONTROLLER STATE MACHINE The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 19-1. TEST-LOGIC-RESET Upon power up, the TAP Controller will be in ...
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SELECT-IR-SCAN All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the ...
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... IR state with JTMS HIGH will move the controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS21352/552 with their respective operational binary codes are shown in Table 19-1. 1 ...
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... A rising edge on JTCLK with JTMS LOW, will put the controller in the Run-Test- Idle state. With JTMS HIGH, the controller will enter the Select-DR-Scan state. Selected Register Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification 102 of 137 DS21352/DS21552 Instruction Codes 010 111 000 011 100 001 This instruction supports two ...
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... IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An optional test register has been included with the DS21352/552 design. This test register is the identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller ...
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IDENTIFICATION REGISTER The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic- Reset state. See Table 19-2. Table 19-3 ...
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– ...
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RFSYNC 6 – RSYNC.cntl 5 98 RSYNC 4 99 RLOS/LOTC 3 100 RSYSCLK O – RSYNC an input 1 = RSYNC an output I 106 of 137 ...
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... INTERLEAVED PCM BUS OPERATION In many architectures, the outputs of individual framers are combined into higher speed serial buses to simplify transport across the system. The DS21352/552 can be configured to allow data and signaling buses to be multiplexed into higher speed data and signaling buses eliminating external hardware saving board space and cost ...
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... Master device with 3 slave devices (8.192 MHz bus rate) Reserved CI RSYSCLK TSYSCLK RSYNC TSSYNC SLAVE #2 RSIG TSIG TSER CO RSER CI RSYSCLK TSYSCLK RSYNC TSSYNC SLAVE #3 RSIG TSIG TSER CO RSER 108 of 137 DS21352/DS21552 Function 8.192MHz System Clock In System 8KHz Frame Sync In PCM Signaling Out PCM Signaling In PCM Data In PCM Data Out ...
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CHANNEL INTERLEAVE In channel interleave mode data is output to the PCM Data Out bus one channel at a time from each of the connected SCTs until all channels of frame n from all each SCT has been place ...
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Figure 21-2 RECEIVE SIDE ESF TIMING FRAME# 1 RSYNC RFSYNC 2 RSYNC 3 RSYNC 4 RLCLK 5 RLINK 6 TLCLK 7 TLINK Notes: 1. RSYNC in frame mode (RCR2 and double wide ...
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Figure 21-3 RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled) RCLK CHANNEL 23 RSER RSYNC RFSYNC CHANNEL RSIG RCHCLK RCHBLK 1 RLCLK RLINK 2 Notes: 1. RCHBLK is programmed to block channel 24 2. Shown is RLINK/RLCLK ...
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Figure 21-5 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) RSYSCLK CHANNEL 31 1 RSER 2 RSYNC RMSYNC 3 RSYNC A RSIG RCHCLK 4 RCHBLK Notes: 1. RSER data in channels 13, 17, 21, 25, ...
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... FRAMER 0, CHANNEL 113 of 137 FR0 CH2 FR1 CH2 FR0 CH2 FR1 CH2 FR0 CH2 FR1 CH2 FR2 CH2 FR0 CH2 FR1 CH2 FR2 CH2 FRAMER 1, CHANNEL 1 MSB LSB FRAMER 1, CHANNEL DS21352/DS21552 FR3 CH2 FR3 CH2 LSB ...
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... RSYNC is in the input mode (RCR1.5 = 0). FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 BIT DETAIL FRAMER 0, CHANNEL 1 MSB LSB FRAMER 0, CHANNEL C/A D/B 114 of 137 DS21352/DS21552 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FRAMER 0, CHANNEL 2 MSB LSB FRAMER 0, CHANNEL C/A D/B LSB ...
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Figure 21-8 TRANSMIT SIDE D4 TIMING FRAME TSYNC TSSYNC 2 TSYNC 3 TSYNC TLCLK 4 TLINK Notes: 1. TSYNC in the frame mode (TCR2 and double-wide frame sync is not enabled (TCR2 ...
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Figure 21-9 TRANSMIT SIDE ESF TIMING FRAME TSYNC TSSYNC 2 TSYNC 3 TSYNC 4 TLCLK TLINK 5 TLCLK 6 TLINK Notes: 1. TSYNC in frame mode (TCR2 and double-wide frame sync ...
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Figure 21-10 TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) TCLK TSER LSB F MSB 1 TSYNC 2 TSYNC TSIG D/B TCHCLK 3 TCHBLK TLCLK 4 TLINK Notes: 1. TSYNC is in the output mode (TCR2 TSYNC ...
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Figure 21-12 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) TSYSCLK CHANNEL 31 1 TSER TSSYNC CHANNEL 31 A TSIG TCHCLK 2,3 TCHBLK Notes: 1. TSER data in channels 13, 17, 21, 25, and 29 ...
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Figure 21-13 TRANSMIT SIDE INTERLEAVE BUS OPERATION, BYTE MODE TSSYNC 1 FR1 CH32 TSER 1 FR1 CH32 TSIG 2 FR2 CH32 FR3 CH32 FR0 CH1 TSER 2 FR2 CH32 FR3 CH32 FR0 CH1 TSIG TSYSCLK 3 TSSYNC FRAMER 3, CHANNEL ...
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... MHz bus configuration. 2. 8.192 MHz bus configuration. FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 BIT DETAIL FRAMER 0, CHANNEL 1 LSB MSB FRAMER 0, CHANNEL 1 C/A D 120 of 137 DS21352/DS21552 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FRAMER 0, CHANNEL 2 LSB MSB FRAMER 0, CHANNEL 2 A C/A D/B LSB B C/A D/B ...
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RECEIVE AND TRANSMIT DATA FLOW DIAGRAMS Figure 22-1 RECEIVE DATA FLOW RSYNC RMR1 to RMR3 RCBR1 to RCBR3 Per Channel Signaling Re-Insert Enable (CCR4.6) Signaling Re-insertion enable (CCR4.7) RNEGI RPOSI B8ZS Decoder 0 1 Receive Mark Code Insertion 0 ...
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Figure 22-2 TRANSMIT DATA FLOW TCBR1/2/3 CCR4.1 DS0 insertion enable (TDC1.7) DS2152 TRANSMIT DATA FLOW Figure 15.11 0 TCD1 4:0 TCHBLK 1 TDC1.5 TIR Function Select (CCR4.0) 0 TIDR RSER (note#1) 1 Software Signaling Enable (TCR1.4) TTR1 to TTR3 Global ...
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... DS21352L/DS21552L; -40°C to +85°C for DS21352LN/DS21552LN) MAX UNITS 5.5 V +0.8 V 3.465 V 5.25 V MAX UNITS 3.3V ± 5% for DS21352L; (0°C to 70° 5.0V ± 5% for DS21552L; 0°C to 70° 3.3V ± 5% for DS21352LN 5.0V ± 5% for DS21552LN) DD MAX UNITS ...
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... ASED t 20 DDR t 50 DSW 124 of 137 = 3.3V ± 5% for DS21352L; (0°C to 70° 5.0V ± 5% for DS21552L; 0°C to 70° 3.3V ± 5% for DS21352LN; -40°C to +85° 5.0V ± 5% for DS21552LN) -40°C to +85° MAX UNITS ...
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Figure 24-1 INTEL BUS READ TIMING (BTS=0 / MUX = 1) ALE t ASD WR* RD* PW CS* AD0-AD7 Figure 24-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) ALE t ASD RD* t ASD WR* PW CS* AD0-AD7 t CYC ...
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Figure 24-3 MOTOROLA BUS TIMING (BTS = 1 / MUX = ASD R/W* AD0-AD7 (read) CS* AD0-AD7 (write) PW ASH t ASED t RWS t ASL t AHL ASL t AHL ...
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... V MIN TYP 127 of 137 = 3.3V ± 5% for DS21352L; (0°C to 70° 5.0V ± 5% for DS21552L; 0°C to 70° 3.3V ± 5% for DS21352LN 5.0V ± 5% for DS21552LN) DD MAX UNITS NOTES ...
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Figure 24-4 INTEL BUS READ TIMING (BTS=0 / MUX= WR* t1 CS* 0ns min. RD* Figure 24-5 INTEL BUS WRITE TIMING (BTS=0 / MUX= RD* t1 CS* 0ns ...
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... Figure 24-7 MOTOROLA BUS WRITE TIMING (BTS=1 / MUX= R/W* t1 CS* 0ns min. DS* Address Valid 5ns min. / 20ns max. 0ns min 75ns max. Address Valid 10ns min. 0ns min 75ns min. 129 of 137 DS21352/DS21552 Data Valid t5 t4 0ns min. 10ns t7 t8 min. t4 0ns min. ...
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... RSYSCLK = 2.048 MHz. 5. RSYSCLK = 4.096 MHz 6. RSYSCLK = 8.192 MHz 130 of 137 = 3.3V ± 5% for DS21352L 5.0V ± 5% for DS21552L 3.3V ± 5% for DS21352LN 5.0V ± 5% for DS21552LN) DD MAX UNITS NOTES ...
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RCLK t D1 RSER / RDATA / RSIG RCHCLK RCHBLK RFSYNC / RMSYNC 1 RSYNC 2 RLCLK RLINK Notes: 1. RSYNC is in the output mode (RCR2.3 = 0). 2. Shown is RLINK/RLCLK in the ESF framing mode 3. No ...
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... RSYNC 2 RSYNC CI Notes: 1. RSYNC is in the output mode (RCR2 RSYNC is in the input mode (RCR2 F-BIT when CCR1 MSB of TS0 when CCR1 SEE NOTE 132 of 137 DS21352/DS21552 ...
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Figure 24-10 RECEIVE LINE INTERFACE TIMING RCLKO t DD RPOSO, RNEGO t R RCLKI RPOSI, RNEGI 133 of 137 ...
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... 134 of 137 = 3.3V ± 5% for DS21352L 5.0V ± 5% for DS21552L; 0°C to 70° 3.3V ± 5% for DS21352LN 5.0V ± 5% for DS21552LN) DD MAX UNITS – – ...
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Figure 24-11 TRANSMIT SIDE TIMING t R TCLK TESO TSER / TSIG / TDATA t D2 TCHCLK TCHBLK 1 TSYNC 2 TSYNC 5 TLCLK TLINK Notes: 1. TSYNC is in the output mode (TCR2.2 = 1). 2. TSYNC is in ...
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Figure 24-12 TRANSMIT SIDE TIMING, ELASTIC STORE ENABLED t R TSYSCLK TSER t D3 TCHCLK TCHBLK TSSYNC Notes: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and ...
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MECHANICAL DESCRIPTION 137 of 137 ...