DS80CH10 Maxim Integrated Products, DS80CH10 Datasheet
DS80CH10
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DS80CH10 Summary of contents
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... Green Energy Manager PRODUCT SPECIFICATION V2.5 DS80CH10 DS80CH10 020299 1/94 ...
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... DS80CH10 1.0 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 DETAILED FEATURE SUMMARY 1.3 CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... DS80CH10 41 43 ...
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... DS80CH10 12.0 PULSE WIDTH MODULATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 FUNCTION OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 PRESCALER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... A/D converter with external refer- ence so that its firmware can perform battery manage- ment tasks without burdening the host CPU. A four– DS80CH10 channel 8–bit pulse–width modulator allows digital control of functions such as LCD contrast and bright- ness. An 8–bit port is provided for key scan inputs. A ...
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... DS80CH10 KEYBOARD CONTROLLER BLOCK DIAGRAM Figure 1–1 P7.7 / AMI.7 / LED.7 XTAL1 XTAL2 3 PORT 7 / VCC uC ACT. MONITOR / CLK OSC. LED DRIVERS VPFW VRST 3 GND SCRATCHPAD SYS. CLOCK REGISTERS CONTROL (256 BYTES) EA ALE PSEN RST SPECIAL WATCHDOG FUNCTION TIMER REGISTERS P3 P3 TIMER 2 P3 TIMER 1 P3 ...
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... Eight–channel, 10–bit A/D with power down mode supports charging NiMH rechargeable cells – 4–channel, 8–bit PWM supports LCD brightness and contrast control DS80CH10 2–Wire Bi–directional Serial Bus – Master/slave multi–drop operation – Manages on–board slaves or external I/O devices Mouse / Detached Keyboard Ports – ...
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... DS80CH10 2.0 PIN DESCRIPTION 128–TQFP PIN ASSIGNMENT Figure 2–1 P9.7 / KSO.15 1 P9.6 / KSO.14 2 P9.5 / KSO.13 3 P9.4 / KSO.12 4 P9.3 / KSO.11 5 P9.2 / KSO.10 6 P9.1 / KSO.9 7 P9.0 / KSO.8 8 P8.7 / KSO.7 9 P8.6 / KSO.6 10 P8.5 / KSO.5 11 P8.4 / KSO P8.3 / KSO.3 14 P8.2 / KSO.2 15 P8.1 / KSO.1 16 P8.0 / KSO.0 17 GND 18 VCC 19 P6.7 / SOC 20 P6.6 P6.5 / PWI P6.4 / PWI.0 23 P6.3 / PWO.3 24 P6.2 / PWO.2 P6.1 / PWO.1 25 P6.0 / PWO.0 26 P5.7 / AI.7 27 P5.6 / AI.6 28 P5.5 / AI.5 29 P5.4 / AI.4 30 P5.3 / AI.3 31 P5.2 / AI.2 32 P5.1 / AI.1 33 P5.0 / AI.0 34 GND ...
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... The internal RAM is still accessible as determined by register settings. 17 GND Digital circuit ground 117 47 HGND Host Interface Ground HVCC Host Interface VCC IOR I/O Read: Input. I/O Read is used to signal a read operation is in effect on the host address/data bus. DS80CH10 DESCRIPTION 020299 9/94 ...
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... DS80CH10 PIN SYMBOL 37 IOW I/O Write: Input. I/O Write is used to signal a write operation is in effect on the host address/data bus. 42 KBCS Keyboard Chip Select: (Input, active low). This is a chip select signal used to enable the keyboard control host interface port. 40 KBOBF Keyboard Output Buffer Full: (Output, active high). This signal is set when the key- board control host interface data buffer contains data to be read by the host ...
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... PWO.2 P6.3 PWO.3 P6.4 PWI.0 P6.5 PWI.1 P6.6 (none) P6.7 SOC DS80CH10 Description Serial Port 0 Input Serial Port 0 Output External Interrupt 0 External Interrupt 1 Timer 0 External Input Timer 1 External Input External Data Memory Write Strobe External Data Memory Read Strobe Description PWM 0 output (active high drive when enabled) ...
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... DS80CH10 PIN SYMBOL 69 P7.0 (AMI.0) Port 7 / AMI.7–0 / LED.7–0: – I/O / Activity Monitor Inputs / LED drive outputs. Port 7 (LED.0) provides eight lines which can serve as a psuedo–bi–directional I/O port pins with inter- 70 P7.1 (AMI.1) nal pull–ups or as Activity Monitor inputs. When used as Activity Monitor inputs, these (LED ...
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... VCC has dropped below the VRST voltage threshold. 118 XTAL1 C Crystal Oscillator Inputs. XTAL1 and XTAL2 provide support for parallel resonant, 119 XTAL2 AT cut crystals. XTAL1 acts also as an input if there is an external clock source in place of a crystal. XTAL2 serves as the output of the crystal amplifier. DS80CH10 DESCRIPTION 020299 13/94 ...
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... DS80CH10 2.2 PIN CHARACTERISTICS POWER DOWN PIN NAME MODE STATE 36 A0 – 43 AGND – 106 ALE Low 46 AVCC – 57 CX1 (note 2) 56 CX2 (note 2) 108 EA – 17 GND – 35 GND – 86 GND – 117 GND – 60 HGND – 66 HGND – 47 HGND – 68 HVCC – ...
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... Hold 96 P3.1 / TXD0 Hold 97 P3.2 / INT0 Hold 98 P3.3 / INT1 Hold 99 P3 Hold DS80CH10 I/O BUFFER TYPE RESET STATE Open–Drain (port) High–Z CMOS drive (bus) Open–Drain (port) High–Z CMOS drive (bus) Open–Drain (port) High–Z CMOS drive (bus) Open–Drain (port) High– ...
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... DS80CH10 2.2 PIN CHARACTERISTICS (cont’d) POWER DOWN PIN NAME MODE STATE 100 P3 Hold 103 P3 Hold 104 P3 Hold 77 P4.0 / KSI.0 Hold 78 P4.1 / KSI.1 Hold 79 P4.2 / KSI.2 Hold 80 P4.3 / KSI.3 Hold 81 P4.4 / KSI.4 Hold 82 P4.5 / KSI.5 Hold 83 P4.6 / KSI.6 Hold 84 P4.7 / KSI.7 Hold 34 P5.0 / AI.0 Hold 33 P5.1 / AI.1 Hold 32 P5.2 / AI.2 Hold 31 P5.3 / AI.3 Hold 30 P5.4 / AI.4 Hold 29 P5.5 / AI.5 Hold 28 P5.6 / AI.6 Hold 27 P5.7 / AI.7 Hold 26 P6 ...
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... P9.7 / KSO.15 Hold 41 PMCS – 107 PSEN Low 105 RST – 55 SD0 (note 2) DS80CH10 I/O BUFFER TYPE RESET STATE Pull–up Weak High Pull–up Weak High Pull–up Weak High Pull–up Weak High Pull–up Weak High Pull–up Weak High Pull– ...
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... DS80CH10 2.2 PIN CHARACTERISTICS (cont’d) POWER DOWN PIN NAME MODE STATE 54 SD1 (note 2) 53 SD2 (note 2) 52 SD3 (note 2) 51 SD4 (note 2) 50 SD5 (note 2) 49 SD6 (note 2) 48 SD7 (note 2) 39 SMI Hold 18 VCC – 85 VCC – 120 VCC – ...
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... However, counter/timers default to run at the older 12 clocks per increment. Therefore, while soft- ware runs at higher speed, timer–based events need no modification to operate as before. Timers can be set to DS80CH10 run at 4 clocks per increment cycle to take advantage of higher speed operation. The relative time of two instructions might be different in the new architecture than it was previously. For exam- ple, in the original architecture, the “ ...
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... DS80CH10 INSTRUCTION SET SUMMARY Table 3–1 (cont’d) OSCILLATOR INSTRUCTION BYTE CYCLES Arithmetic Instructions: ADD ADD A, direct 2 8 ADD A, @ ADD A, #data 2 8 ADDC ADDC A, direct 2 8 ADDC A, @ ADDC A, #data 2 8 SUBB SUBB A, direct ...
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... The following table summarizes the speed improve- ment of the High Speed Micro core over a standard 12 clock / machine cycle 8052 device. #Opcodes Speed Improvement 159 2.4 x 255 Average: 2.5 DS80CH10 ANL C, bit ANL C, bit ORL C, bit 2 8 ORL C, bit 2 8 MOV C, bit 2 ...
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... DS80CH10 3.6 INTERRUPT CONTROL The GEM provides 16 sources of interrupt with three priority levels. The Power–fail Interrupt (PFI), if enabled, always has the highest priority. There are two remaining user selectable priorities: high and low. If two interrupts that have the same priority occur simulta- INTERRUPT PRIORITY Table 3– ...
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... ENABLE LOC. PRIORITY E2W EIE.0 P2W EAD EIE.1 PAD EMS EIE.2 PMS EKB EIE.3 PKB EPB EIE.4 PPB KDF.7–0 EKD EIE.5 PKD EWDI EIE.6 PWDI EDK EIE.7 PDK DS80CH10 PRIORITY LOC. EIP.0 EIP.1 EIP.2 EIP.3 EIP.4 EIP.5 EIP.6 EIP.7 020299 23/94 ...
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... DS80CH10 4.0 MEMORY RESOURCES 4.1 OVERVIEW The GEM contains the following memory resources and features: 256 bytes of on–chip direct (scratchpad) RAM 256 bytes of on–chip MOVX data RAM Off–chip program and data memory expansion Software enable/disable of on–chip data memory 4.2 DATA MEMORY ACCESS Unlike many 8051 derivatives, the GEM contains on– ...
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... DIRECT (SCRATCHPAD) RAM ACCESS The GEM incorporates a full 256 bytes of direct RAM. This RAM is accessed in a manner identical to that of a DS80CH10 standard 80C52 compatible device. A full description of this memory along with the instructions that access it is contained in the Dallas High Speed Micro User’s Guide. ...
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... DS80CH10 SPECIAL FUNCTION REGISTER RESET VALUES Table 4–2 * New functions are in bold EIP F8h 00000000 B F0h 00000000 EIE E8h 00000000 ACC E0h 00000000 WDCON MSDAT MSCON D8h 0X0X0XX0 00000000 00000000 PSW DKDAT DKCON D0h 00000000 00000000 00000000 T2CON T2MOD RCAP2L RCAP2H ...
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... P2.4 P2.3 P2.2 P2.1 P2.0 P4.4 P4.3 P4.2 P4.1 P4.0 KDE4 KDE3 KDE2 KDE1 KDE0 KDF4 KDF3 KDF2 KDF1 KDF0 ES0 ET1 EX1 ET0 EX0 DS80CH10 ADDRESS 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 90h 91h 92h 93h 94h 95h 98h 99h 9Ah ...
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... DS80CH10 SPECIAL FUNCTION REGISTER LOCATIONS Table 4–3 (cont’d) * New functions are in bold REGISTER BIT 7 BIT 6 BIT 5 PORT5 P5.7 P5.6 P5.5 KBSTAT KST7 KST6 KST5 KBDIN KBDOUT PORT3 P3.7 P3.6 P3.5 ADCON1 STRT/ EOC CONT/ BSY SS ADCON2 OUTCF MUX2 MUX1 ADC9/ ADC8/ ADC7/ ADMSB ADLSB ADC7 ...
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... PW3EN EPB EKB EMS EAD E2W P9.4 P9.3 P9.2 P9.1 P9.0 PW2 PW3 PW3 PW3 PW3 T T/C PPB PKB PMS PAD P2W DS80CH10 ADDRESS D5h D6h D7h D8h D9h DAh DDh DEh DFh E0h E4h E5h E6h E7h E8h ECh EDh EEh EFh F0h F8h 020299 29/94 ...
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... DS80CH10 5.0 CORE I/O RESOURCES The GEM incorporates a full complement of the 80C52–compatible I/O resources as well as a number of specialized I/O resources which are associated with the Dallas High–Speed micro core. These features are described in this section. 5.1 PROGRAMMABLE TIMERS Three programmable timers are included which are compatible with the standard 80C52 ...
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... I serve the alternate function. In order to use the alternate function, the associated port latch must be programmed The alternate func- tions are summarized in Table 5–2 below. ALTERNATE FUNCTION(S) DS80CH10 020299 31/94 ...
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... DS80CH10 PORT PIN ALTERNATE FUNCTIONS Table 5–2 (cont’d) P3.0 RXD0 UART Receive P4.7 – P4.0 KSI.7 – KSI.0 Keyboard scan inputs P5.7 – P5.0 AI.7 – AI.0 A/D analog inputs P6.7 SOC A/D start of conversion input P6.6 – (None) P6.5 – P6.4 PWI.1 – PWI.0 PWM channels 1 and 0 inputs P6.3 – P6.0 PWO.3 – PWO.0 PWM channels and 0 outputs P7.7 – ...
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... STATUS R/W REGISTER EN 09EH 2WSTAT2 – STATUS RD EN REGISTER 09FH 2WDAT – RECEIVE RD DATA BUFFER EN 09BH DOUT SHIFT ACK DIN WR REGISTER EN 09BH MSB LSB TIMING & ARBITRATION CONTROL LOGIC LOGIC SERIAL CLOCK GEN. DS80CH10 SDA PIN SCL PIN 020299 33/94 ...
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... DS80CH10 6.2 REGISTER DESCRIPTION The microcontroller interface to the 2–wire serial port consists of six Special Function Registers (SFR’s) 6.2.1 2WFS – 2–Wire Frequency Select Register 2WFS; SFR ADDR.=09CH BIT 7 BIT 6 BIT 5 BIT 4 Read/Write Access: Unrestricted. Initialization: 00H on any type of reset The 2–Wire Frequency Select Register is an 8–bit read/ write register which is used by the microcontroller to set the 2– ...
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... START condition will be asserted at the end of the byte transfer. Again, TSTA will be set when the repeat start is successfully asserted. If STA is cleared further START or repeat START will be attempted. DS80CH10 BIT 3 BIT 2 BIT 1 BIT 0 BMM ANAK – ...
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... DS80CH10 receive the subsequent address and data bytes on the bus, and will finally be notified of a transmitted STOP condition. 6.2.5 2WSTAT1 – 2–Wire Status Register 1 2WSTAT1; SFR ADDR.=09EH BIT 7 BIT 6 BIT 5 BIT 4 BER ARL RSTO TXI Read/Write Access: Unrestricted. Initialization: 00H on any type of reset BER – ...
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... Master transmitter, Master receiver, Slave trans- mitter, and Slave Receiver. Operating the port in these four modes is described in detail below. Following any type of reset, the 2–Wire port will be configured in slave receive mode DS1621 8–BIT uC DIGITAL w/ 2–WIRE I/F THERMOMETER DS80CH10 020299 37/94 ...
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... DS80CH10 DATA TRANSFER ON THE 2–WIRE BUS Figure 6–3 R/W DIR. BIT SDA MSB SLAVE ADDRESS RECEIVER SCL CLOCK LINE HELD LOW XMIT: UNTIL SHIFT REG. LOAD START RECEIVE: REC. BUF. FULL CONDITION 6.3.1 Master Transmit In the master transmit mode, the GEM is configured as a master device and transfers a number of data bytes to a slave receiver. A timing diagram in Figure 6– ...
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... STO. After the STOP condi- tion is sent, the STO bit will be automatically cleared and X/R will be cleared to 0. DS80CH10 In the Master transmit mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the 2–Wire bus. If another device on the bus over- ...
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... DS80CH10 MASTER RECEIVE OPERATION TIMING Figure 6–5 Ç Ç É É É É Ç Ç S SDA/SCL Ç Ç Ç Ç É É É É SLAVE ADDR. Ç Ç Ç Ç (Sr) É É É É STA BIT TSTA BIT X/R BIT DATA BUF: ...
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... Figure 6–7 illustrates the timing for Slave Transmit mode operation. In this mode the GEM, addressed as a slave, transfers one or more bytes to the bus master. The transfer is initiated by the external master beginning with either a START or Repeat START condition, fol- lowed by the transmission of the GEM’s slave address DS80CH10 020299 41/94 ...
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... DS80CH10 with the direction bit set to 1. This byte will be shifted in and loaded into the receive buffer register at the time the acknowledge bit is returned to the master, resulting in SLAVE TRANSMIT OPERATION TIMING Figure 6–7 Ç Ç Ç Ç É É É É ...
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... Slave Receive operation as shown in Figure 6–6. The exceptions to this timing are summa- rized as follows additional interrupt will be gener- DS80CH10 ated when a Receive START condition is detected as indicated by RSTA = 1. This will inform the firmware of the start of a message and allow it to identify the next byte as an address ...
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... DS80CH10 7.0 A/D CONVERTER 7.1 OVERVIEW A self–contained A/D converter is provided on the GEM. Its major features are summarized below: 10–bit resolution True 9–bit accuracy: total error no greater than + 2 LSB’s Monotonic with no missing codes eight multiplexed inputs Shared analog/digital pins with 60 dB isolation Digital window comparator / alarm Low power consumption The A/D subsystem consists of a 10– ...
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... If the DAC output is greater than the analog input the bit is reset. After all bits have been tested and set or reset accordingly, the binary value in SAR[9.. digital representation of the ana- log input value. DS80CH10 STADC 020299 45/94 ...
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... DS80CH10 SAR A/D SIMPLIFIED BLOCK DIAGRAM Figure 7–2 ACLK START CONTROL LOGIC EOC RESOLUTION ANALOG IN REFHI REFLO ZRO (SAMPLE) 7.5 CONVERSION TIME An internal clock signal called ACLK is used to clock the successive approximation logic in performing the A/D conversion. ACLK is derived from the microcontroller clock signal through divide–down logic. A total of 16 clock cycles are required to perform the conversion ...
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... This feature allows software to ignore uninteresting results without actually reading the con- verter result. User software can select two 8–bit comparator values. These values will be compared against the most signifi- DS80CH10 12.000 16.000 20.000 25.000 33.000 ...
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... DS80CH10 WINDOW COMPARATOR OPERATION Figure 7–3 3FFH WINHI WINLO 000H WINHI WINLO VALUE VALUE >ADR9–2 >ADR9–2 >ADR9–2 <ADR9–2 <ADR9–2 >ADR9–2 <ADR9–2 <ADR9–2 Note that there is no hardware significance to upper and lower designations. The upper comparison value can be selected as less than the lower comparison value, although doing so provides no additional function ...
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... BSY bit to indicate that a conversion has started. When ADEX = 1, the STRT bit can still be used. WCQ – Window Comparator Qualifier. Setting this bit enables the window comparator qualifier function. When WCQ = 1, an interrupt can DS80CH10 BIT 3 BIT 2 BIT 1 BIT 0 WCQ ...
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... DS80CH10 7.8.2 ADCON2 – A/D Control Register 2 ADCON2; SFR ADDR.=0B3H BIT 7 BIT 6 BIT 5 BIT 4 OUTCF MUX2 MUX1 MUX0 Read/Write Access: Unrestricted. Initialization: 00h on any type of reset OUTCF – Output Conversion Format. Selects whether the conversion output most–significant 8–bits or the most–significant 2–bits are presented in the A/D MSB register ...
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... BIT 6 BIT 5 BIT 4 Read/Write Access: Unrestricted. Initialization: 00h on any type of reset Lower limit for the window comparator. These 8–bits are compared against the most significant 8–bits of the previous A/D result. A match of the desired magnitude DS80CH10 BIT 3 BIT 2 BIT 1 BIT 0 ADR3 ADR2 ADR1 ...
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... DS80CH10 8.0 ACTIVITY MONITOR 8.1 OVERVIEW During periods of inactivity, varying levels of standby and suspend modes of operation can be initiated by the GEM. Inactivity can be detected by the GEM and then action can be taken to reduce the power consumption of the system and thereby conserve operating power. Activity monitoring is performed by the special logic pro- vided as an alternate function on all lines of Port 7 ...
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... AME2 AME1 cleared to 0, the associated pin is disabled as an inter- rupt source. The associated Port 7 latch bit must be set to 1 when a pin programmed as an activity moni- tor input. BIT 3 BIT 2 BIT 1 AMQ3 AMQ2 AMQ1 DS80CH10 BIT 0 AME0 BIT 0 AMQ0 020299 53/94 ...
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... DS80CH10 When an AMQ bit is set to 1, the corresponding activity monitor input pin is qualified with IOR or IOW result, the corresponding AMF bit will not be set unless the programmed state on the AMI.n pin is accompanied 8.5 AMP – ACTIVITY MONITOR POLARITY REGISTER AMP; SFR ADDR.=094H ...
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... PMCS line selects the identical power management interface port. Each set of system interface registers occupy three DS80CH10 inputs as it does with the 8042 in these systems. The other port can be assigned as a communication channel to the GEM to support power management and/or other functions ...
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... DS80CH10 SYSTEM DATA TRANSFER SUMMARY Table 9–1 REGISTER REGISTER KBCS KBCS PMCS PMCS A0 A0 IOR IOR IOW IOW SELECTED Undefined KBDOUT KBSTAT KBDIN KBDIN PMDOUT PMSTAT ...
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... Buffer Full. The KIBF or PIBF flag is set to 1 whenever the host sys- tem writes data into the associated input data register. DS80CH10 command or data by reading the command/data flag, i.e., KC/D or PC/D, in the status register followed by a read of the input data register. The contents of the input data registers are unaffected by any type of reset ...
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... DS80CH10 9.5 KBDOUT / PMDOUT – OUTPUT DATA REGISTERS KBDOUT; SFR ADDR.=0AFH BIT 7 BIT 6 BIT 5 BIT 4 PMDOUT; SFR ADDR.=0BFH BIT 7 BIT 6 BIT 5 BIT 4 Read/Write Access: Unrestricted. Initialization: Undefined on any type of reset The output data registers can be read or written by the GEM but are read only to the host When the GEM writes ...
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... Upon receipt of the interrupt, the system should read this register to deter- mine on which scan line the key closure occurred. The DS80CH10 capable of generating an interrupt on a low–going tran- sition result, the GEM can initiate a keyboard scan only when a key is pressed instead of doing it periodi- cally ...
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... DS80CH10 11.0 MOUSE / DETACHED KEYBOARD SERIAL I/O 11.1 OVERVIEW The GEM incorporates two identical serial ports which provide hardware support for industry standard serial communication to a PS/2 style mouse or detached key- board. The major features of these hardware ports include: Byte–oriented transfers to / from external mouse / keyboard ...
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... Data Bit 7 (most significant) 10 Parity Bit (always odd) 11 Stop Bit (always 1) DS80CH10 nate function of P1.4 and P1.5 general purpose parallel I/O port pins, respectively. DKCLK and DKDIO are the alternate function of the P1.6 and P1.7, respectively . In order to use either serial port, the associated Port 1 latch bits must both be programmed with a “1”. ...
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... DS80CH10 11.4.1 MSDAT / DKDAT – Data Registers MSDAT; SFR ADDR.=0D9H BIT 7 BIT 6 BIT 5 BIT 4 DKDAT; SFR ADDR.=0D1H BIT 7 BIT 6 BIT 5 BIT 4 Read/Write Access: Unrestricted. Initialization: 00H on any type of reset The Data Register provides access to the shift register during transmit and to the receive buffer during receive. ...
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... PMS bit (EIP.2, 0F8H). Similarly, interrupts for the detached keyboard serial port are enabled via the EDK bit (EIE.7, 0E8H) and priority is controlled via the PDK DS80CH10 bit (EIP.7, 0F8H). Each ports xBI, xTXI, and xRXI flag bits are all potential interrupt sources when the associated interrupt enable bit ...
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... DS80CH10 within 15 ms, the firmware should then initiate the 2 ms timeout count for the entire word to be shifted out; also specified for PS/2 input device. These timeout checks can be accomplished using one of the program- mable timers operating as an interval timer. During a normal transmit, the input device will generate 10 clock pulses to clock out data bits 0– ...
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... When a value of 00H is programmed into the counter the input clock frequency will be passed through as the clock output to the channel’s pulse genera- tor. A value of 0FFH will result in the clock input being divided by 256 and output to the pulse generator. DS80CH10 If 020299 65/94 ...
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... DS80CH10 PWM CHANNEL CLOCK GENERATOR ( Figure 12–2 /1 1/4 /4 /16 EN /64 PWI.n 12.4 PWM PULSE GENERATORS Figure 12–3 illustrates the pulse generators for each of the four PWM channels. Each pulse generator has an 8–bit free running timer which accepts a clock input from the associated PWM clock generator. The timer value is compared to zero and to a user selectable value ...
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... PIN FUINCTION) BIT 3 BIT 2 BIT 1 PW1S2 PW1S1 PW1S0 BIT 3 BIT 2 BIT 1 PW3S2 PW3S1 PW3S0 PWM n CLOCK PWnS2 PWnS1 PWnS0 MCLK MCLK PWI.n pin* DS80CH10 BIT 0 PW1EN BIT 0 PW3EN FREQ MCLK * 4 MCLK * 020299 67/94 ...
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... DS80CH10 *Note: For channels 0 and 2, this selection assigns PWI.0 as the input clock source. For channels 1 and 3, this selection assigns PWI.1 as the input clock source. PWnEN – PWM n Frequency Generator Enable. Enables the frequency generator for PWM n. When PWnEN = 1, the frequency generator operates from the 12.5.2 PW01CON / PW23CON – ...
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... BIT 6 BIT 5 BIT 4 PWM1; SFR ADDR.=0DFH BIT 7 BIT 6 BIT 5 BIT 4 PWM2; SFR ADDR.=0EEH BIT 7 BIT 6 BIT 5 BIT 4 DS80CH10 BIT 3 BIT 2 BIT 1 BIT 0 BIT 3 BIT 2 BIT 1 BIT 0 BIT 3 BIT 2 BIT 1 BIT 0 value for the frequency generator’s 8–bit auto–reload- able timer. The timer’ ...
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... DS80CH10 PWM3; SFR ADDR.=0EFH BIT 7 BIT 6 BIT 5 BIT 4 Read/Write Access: Unrestricted. Initialization: 00H on any type of reset Used to access the PWM n timer and the PWM n compare values that selects the PWM duty cycle. This register provides read/write access to both. The selec- tion of the active function is controlled by the PWnT/C bit ...
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... LOW POWER OPERATING MODES Along with the standard IDLE and power down (STOP) modes of the standard 80C52, the GEM provides the DS80CH10 Slow Clock mode. This mode allows the processor to continue functioning, yet save power compared with full operation mode. ...
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... DS80CH10 SLOW CLOCK MODE INSTRUCTION CYCLE RATE Table 13–1 FULL SPEED CRYSTAL SPEED (4 CLOCKS) 1.8432 MHz 460.8 KHz 11.0592 MHz 2.765 MHz 22 MHz 5.53 MHz 25 MHz 6.25 MHz 33 MHz 8.25 MHz SLOW CLOCK MODE OPERATING CURRENT ESTIMATES Table 13–2 FULL SPEED CRYSTAL SPEED (4 CLOCKS) 1 ...
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... Status register features several new flags that are useful. These are described below. DS80CH10 13.2.1.5 Status Information in the Status register assists decisions about switching into Slow Clock Mode. This register contains information about the level of active interrupts and the activity on the serial ports ...
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... DS80CH10 disable the crystal amplifier. This process requires two steps. Reversing the process also requires two steps. The XT/RG bit (EXIF.3) selects the crystal or ring as the clock source. Setting XT/ selects the crystal. Setting XT/ selects the ring. The RGMD (EXIF.2) bit serves as a status bit by indicating the active clock source ...
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... CD1, CD0=11 FOR 1024 OPERATE N WITHOUT CRYSTAL ? DONE Y XT/RG=0 N DISABLE CRYSTAL? (NO FAST SWITCH TO XTAL) DONE Y XTOFF = 1 LOWEST POWER OPERATING STATE DS80CH10 EXITING SLOW CLOCK MODE SOFTWARE DECIDES SWB=1 AND EXTERNAL TO EXIT ACTIVITY OCCURS HARDWARE AUTOMATICALLY CD1, CD0 = 01 FOR 4 SWITCHES CD1, CD0 CHECK N STATUS=0 ? DONE Y N ...
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... DS80CH10 SLOW CLOCK MODE CONTROL AND STATUS BIT SUMMARY Table 13–3 BIT NAME LOCATION FUNCTION XT/RG EXIF.3 Control. XT/RG=1, runs from crystal or external clock; XT/RG=0, runs from internal Ring Oscillator. RGMD EXIF.2 Status. RGMD=1, CPU clock = ring; RGMD=0, CPU clock = crystal. CD1, CD0 PMR.7, Control. CD1,0=01, 4 clocks ...
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... However, the ring oscillator will start instantly. Running from the ring, the user can DS80CH10 perform a simple operation and return to sleep in less time than it takes to start the crystal user selects the ring to provide the start– ...
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... DS80CH10 RING OSCILLATOR EXIT FROM STOP MODE Figure 13–2 STOP MODE WITHOUT RING STARTUP uC OPERATING Ì Ì Ì Ì Ì CRYSTAL OSCILLATION Ì Ì Ì Ì Ì uC ENTERS STOP MODE POWER STOP MODE WITH RING STARTUP uC OPERATING CRYSTAL Ì Ì Ì Ì Ì ...
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... C to +125 C 260 C for 10 seconds ( =5.0 CC MIN TYP MAX UNITS 4.5 5.0 5.5 V 4.30 4.38 4.55 V 4.0 4.13 4. 100 A –0.3 +0.8 V –0.3 +0.6 V –0.3 +0 2 3 3 0.15 0.45 V 0.15 0.45 V 0.15 0.8 V 2.4 V DS80CH10 10%) NOTES 020299 79/94 ...
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... DS80CH10 14.2 MICROCONTROLLER DC ELECTRICAL CHARACTERISTICS (cont’d) Output High Voltage: Ports 1.0, Ports 1.1, Ports transition mode, and Ports V OH2 6.0–Ports 6.3 pins with PWM channel enabled @ I = –1 Output High Voltage: Port 0 V OH3 (bus mode – Input Low Current: Ports 1.0, Ports 1 ...
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... CLCL 10 (t /2)–5 CLCL 10 (t /2)–5 CLCL 56 2.5t –20 CLCL 10 (t /2)–5 CLCL 56 2t –5 CLCL 41 2t –20 CLCL –5 CLCL 70 3t –20 CLCL 81 3.5t –25 CLCL 0 0 DS80CH10 10%) UNITS UNITS MHz 020299 81/94 ...
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... DS80CH10 14.3.2 MOVX USING STRETCH MEMORY CYCLES PARAMETER PARAMETER SYMBOL SYMBOL Data Access ALE Pulse Width t LHLL2 Address Hold after ALE Low for t LLAX2 MOVX Write RD Pulse Width t RLRH WR Pulse Width t WLWH RD Low to Valid Data In t RLDV Data Hold after Read t RHDX ...
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... =5.0 CC MIN TYP MAX UNITS =5.0 CC MIN TYP MAX UNITS 12t ns CLCL 4t ns CLCL 10t ns CLCL 3t ns CLCL 2t ns CLCL t ns CLCL t ns CLCL t ns CLCL 11t ns CLCL 3t ns CLCL DS80CH10 10%) NOTES 10%) NOTES 020299 83/94 ...
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... DS80CH10 14.3.5 POWER CYCLE TIMING CHARACTERISTICS PARAMETER SYMBOL Cycle Start–up Time t CSU Power–on Reset Delay t POR NOTES: 1. Start–up time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592 MHz crys- tal manufactured by Fox. 2. Reset delay is a synchronous counter of crystal oscillations after crystal start–up MHz, this time is 1.99 ms. EXTERNAL PROGRAM MEMORY READ CYCLE Figure 14– ...
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... LLAX2 WR t AVLL INSTRUCTION ADDRESS PORT 0 IN A0–A7 t AVWL1 PORT 2 t AVWL2 t LLDV t WHLH t RLRH t RLDV t RHDZ t RHDX DATA IN t AVDV1 t AVDV2 ADDRESS A8–A15 OUT t WHLH LLWL t WLWH t WHQX DATA OUT t QVWX ADDRESS A8–A15 OUT DS80CH10 ADDRESS A0–A7 ADDRESS A0–A7 020299 85/94 ...
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... DS80CH10 DATA MEMORY WRITE WITH STRETCH=1 Figure 14–4 Last Cycle of First Previous Machine Instruction Cycle CLK ALE PSEN WR PORT 0 A0–A7 D0–D7 A0–A7 D0–D7 MOVX Next Instr. Instruction Address Address MOVX Next Instruction Instruction Read PORT 2 A8–A15 A8– ...
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... SERIAL PORT 0 (SYNCHRONOUS MODE) SM2=0=>TXD CLOCK=XTAL/12 ALE PSEN WRITE TO SBUF RXD D0 DATA OUT TXD CLOCK TI WRITE TO SCON TO CLEAR RI RXD DATA IN TXD CLOCK RI t CLCL t CHCX t CLCH t CLCX XHDX 1/(XTAL FREQ/12 DS80CH10 TRANSMIT RECEIVE D7 020299 87/94 ...
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... DS80CH10 POWER CYCLE TIMING Figure 14– PFW V RST V SS INTERRUPT SERVICE ROUTINE XTAL1 INTERNAL RESET 14.4 SYSTEM INTERFACE DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Power Supply Voltage HVCC Average HVCC Power HICC1 Supply Current Input Logic Input Logic Input Leakage Current (Any ...
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... BUS TIMING FOR WRITE CYCLE TO HOST I/F REGISTERS Figure 14–9 KBCS, PMCS A0 t CIO IOW SD7–SD0 (INPUT =5.0 CC MIN TYP MAX UNITS 160 CYC t t IOL IOH t IOCH t IWDS t IWDH DS80CH10 10%) NOTES 020299 89/94 ...
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... DS80CH10 BUS TIMING FOR READ CYCLE TO HOST I/F REGISTERS Figure 14–10 KBCS, PMCS A0 t CIO IOR t IRD SD7–SD0 (OUTPUT) OUTPUT LOAD Figure 14–11 DEVICE UNDER TEST 1K 020299 90/94 t CYC t t IOL IOH t IOCH t IRDH t IRDZ V = +5. ...
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... XTAL oscillator should be greater than 5 MHz for 400Kbps operation. 2–WIRE SERIAL I/O TIMING Figure 14– SDA t 2DS t STAH SCL t t SCL SCH DS80CH10 ( =5.0 CC INPUT OUTPUT (1) > (4) > 1.0 s CLK (1) > (4) > 1.3 s CLK (1) > (4) > 0.6 s ...
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... DS80CH10 14.7 MOUSE/DETACHED KEYBOARD SERIAL TIMING CHARACTERISTICS PARAMETER SYMBOL “x”DIO, CLK Rise, Fall Time “x”CLK Low Time t XCL “x”CLK High Time t XCH “x”DIO Input Data Setup t XDS Time to Falling Clock “x”DIO Input Data Hold Time ...
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... VCC +0.2 V –0.2V GND–0.2 GND +0.2 V GND–0.2 VCC +0.2 V AGND AVCC+0.2 V –0.2 =AVCC =5.0 10% AGND = GND = 0V) CC MIN TYP MAX UNITS 600 A 150 A VRL VRH Bits + 0.3 + 0.75 LSB + 0.2 + 1.0 LSB + 0.25 + 1.0 LSB + 0.25 + 1.0 % –60 dB DS80CH10 NOTES NOTES 020299 93/94 ...
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... DS80CH10 128–PIN TQFP PKG 128–PIN DIM MIN MAX A – 1.60 A1 0.05 – A2 1.35 1.45 B 0.17 0.27 C 0.09 0.20 D 21.80 22.20 D1 20.00 BSC E 15.80 16.20 E1 14.00 BSC e 0.50 BSC L 0.45 0.75 56–G4011–000 020299 94/94 ...