MPC930  

Manufacturer Part Number  MPC930 
Manufacturer  Freescale Semiconductor, Inc 
MPC930 datasheet 

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MPC930 MPC931
Programming the MPC930/931
The MPC930/931 clock driver outputs can be configured
into several frequency relationships, in addition the external
feedback option allows for a great deal of flexibility in
establishing unique input to output frequency relationships.
The output dividers for the three output groups allows the
user to configure the outputs into 1:1, 2:1, 3:1, 3:2 and 3:2:1
frequency ratios. The use of even dividers ensures that the
output duty cycle is always 50%. Table 1 illustrates the
various output configurations, the table describes the outputs
using the VCO frequency as a reference. As an example for a
3:2:1 relationship the Qa outputs would be set at VCO/2, the
Qb’s at VCO/4 and the Qc’s at VCO/6. These settings will
provide output frequencies with a 3:2:1 relationship.
The division settings establish the output relationship, but
one must still ensure that the VCO will be stable given the
frequency of the outputs desired. The VCO lock range can be
found in the specification tables. The feedback frequency
and the Power_Dn pin can be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL is such that for output frequencies between 25 and
180MHz the MPC930/931 can generally be configured into a
stable region.
Table 2. Input Reference/Output Frequency Relationships (Internal Feedback Only)
INPUTS
Div_Sela
Div_Selb
Div_Selc
Power_Dn=0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MOTOROLA
APPLICATIONS INFORMATION
The relationship between the input reference and the
output frequency is also very flexible. Table 2 shows the
multiplication factors between the inputs and outputs when
the internal feedback option is used. For external feedback
Table 1 can be used to determine the multiplication factor,
there are too many potential combinations to tabularize the
external feedback condition. Figure 5 through Figure 10
illustrates several programming possibilities, although not
exhaustive it is representative of the potential applications.
Table 1. Programmable Output Frequency Relationships
(Power_Dn = ‘0’)
INPUTS
Div_Sela
Div_Selb
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
OUTPUTS
Qa
Qb
Power_Dn=1
Power_Dn=0
Power_Dn=1
4x
2x
4x
4x
2x
4x
4x
2x
2x
4x
2x
2x
2x
x
4x
2x
x
4x
2x
x
2x
2x
x
2x
6
OUTPUTS
Div_Selc
Qa
Qb
Qc
0
VCO/2
VCO/2
VCO/4
1
VCO/2
VCO/2
VCO/6
0
VCO/2
VCO/4
VCO/4
1
VCO/2
VCO/4
VCO/6
0
VCO/4
VCO/2
VCO/4
1
VCO/4
VCO/2
VCO/6
0
VCO/4
VCO/4
VCO/4
1
VCO/4
VCO/4
VCO/6
Qc
Power_Dn=0
Power_Dn=1
2x
2x
x
2x
4/3x
2/3x
x
2x
x
x
4/3x
2/3x
2x
2x
x
2x
4/3x
2/3x
x
2x
x
x
4/3x
2/3x
TIMING SOLUTIONS
BR1333 — Rev 6
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