VSC7135 Vitesse Semiconductor Corp., VSC7135 Datasheet
VSC7135
Available stocks
Related parts for VSC7135
VSC7135 Summary of contents
Page 1
... It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes it onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency. The VSC7135 also samples serial receive data on the RX PECL differential inputs, recovers the clock and data, deserializes it onto the 10-bit receive data bus, outputs two recovered clocks at one-twentieth of the incoming baud rate and detects “ ...
Page 2
... Serializer The VSC7135 accepts TTL input data as a parallel 10 bit character on the T0:9 bus which is latched into the input latch on the rising edge of REFCLK. This data will be serialized and transmitted on the TX PECL differ- ential outputs at a baud rate of ten times the frequency of the REFCLK input, with bit T0 transmitted first. User data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel specifi ...
Page 3
... RCLK and RCLKN. If serial input data is not present, or does not meet the required baud rate, the VSC7135 will continue to produce a recovered clock so that downstream logic may continue to function. The RCLK and RCLKN output frequency under these circumstances may differ from their expected frequency by no more than +1% ...
Page 4
... Receiving Two Consecutive K28.5+TChar Transmission Words RCLK RCLKN COM_DET R0:9 Potentially Corrupted Page 4 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION K28.5 TChar TChar TChar K28.5 TChar TChar VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 TChar K28.5 TChar G52146-0, Rev. 4.0 5/28/98 ...
Page 5
... Data Sheet VSC7135 AC Characteristics REFCLK T0:9 Data Valid 10 Bit Data Table 1: Transmit AC Characteristics Parameters Description T0:9 Setup time to the rising T 1 edge of REFCLK T0:9 hold time after the T 2 rising edge of REFCLK T ,T TX+/TX- rise and fall time SDR SDF Latentcy from rising edge of T REFCLK to T0 appearing on ...
Page 6
... — 2.4 15bc + 2ns 34bc + 2ns — 2.0 599 370 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 T 3 Data Valid Units Conditions ns. Measured between the 1.4V point of RCLK or RCLKN and a valid level of R0:9. All outputs driving 10pF load. ns. Nominal delay is 10 bit times. ps. Tested on sample basis ...
Page 7
... Data Sheet VSC7135 REFCLK Table 3: Reference Clock Requirements Parameters Description FR Frequency Range FO Frequency Offset DC REFCLK duty cycle T ,T REFCLK rise and fall time RCR RCF REFCLK Jitter Power REFCLK 5MHz Jitter PhaseNoise 100 Hz G52146-0, Rev. 4.0 5/28/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 ...
Page 8
... VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 Units Conditions – 2 mVp-p (TX – 2 mVp-p (TX+ - TX-) Internally biased to Vdd/2 mVp-p (RX+ - RX-) V — ...
Page 9
... Data Sheet VSC7135 Figure 7: Parametric Measurement Information Serial Input Rise and Fall Time T r Receiver Input Eye Diagram Jitter Tolerance Mask Serial Output Load G52146-0, Rev. 4.0 5/28/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION TTL Input and Output Rise and Fall Time ...
Page 10
... Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Figure 8: Input Structures V +3 Current Limit R R GND REFCLK and TTL Inputs +3.3 V All Resistors 3.3K GND High Speed Differential Input (RX+/RX-) B VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 G52146-0, Rev. 4.0 5/28/98 ...
Page 11
... Data Sheet VSC7135 Package Pin Descriptions V SSD DDD DDD SSD V SSD N/C (Top View) Table 4: Pin Identification Pin # Name INPUTS - TTL 2-4, 6-9, T0:9 10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of 11-13 REFCLK. The data bit corresponding transmitted first. ...
Page 12
... VDDT TTL Output Ground 32, 33, 46 VSST PECL I/O Power Supply 53, 60, 63 VDDP 16,17,27, No Connection. These pins are not internally connected. N/C 48,49,64 Page 12 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Description VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 G52146-0, Rev. 4.0 5/28/98 ...
Page 13
... Data Sheet VSC7135 Package Information TYP TYP 0.30 RAD. TYP. 0.20 RAD G52146-0, Rev. 4.0 5/28/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION 64 PQFP Package Dimensions TYP . 0.17 MAX. b 0.25 L NOTES: All drawings not to scale All units in mm unless otherwise noted ...
Page 14
... Gigabit Ethernet Transceiver Package Thermal Considerations The VSC7135 is packaged conventional PQFP with an internal heat spreader. This package use an industry-standard EIAJ footprint, but have been enhanced to improve thermal dissipation. The construction of the packages are as shown in Figure 12. Figure 10: Package Cross Section - 14 mm package ...
Page 15
... Data Sheet VSC7135 Ordering Information The part number for this product is formed by a combination of the device number and the package style: Device Type: VSC7135: 1.25 Gbps Transceiver Package Style (64-pin) QN: 14x14mm PQFP QU: 10x10mm PQFP Marking Information The package is marked with three lines of text as shown below (QU Package): Pin Identifi ...
Page 16
... Gigabit Ethernet Transceiver Page 16 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC7135 G52146-0, Rev. 4.0 5/28/98 ...