MAX3752 Maxim Integrated Products, MAX3752 Datasheet

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MAX3752

Manufacturer Part Number
MAX3752
Description
Manufacturer
Maxim Integrated Products
Datasheet
The MAX3752 quad-port bypass IC is designed for use
in the Fibre Channel Arbitrated Loop topology. This
device consists of four serially connected port bypass
circuits (PBCs) and a repeater that provides clock and
data recovery (CDR).
The quad-port bypass circuit allows connection of up to
four Fibre Channel L-Ports, which can each be enabled
or bypassed by controlling the PBC select inputs.
Additional quad PBCs can be cascaded for applica-
tions requiring more than four L-Ports. To reduce the
external parts count, all signal inputs and outputs have
internal termination resistors.
The MAX3752 complies with Fibre Channel jitter toler-
ance requirements and can recover data signals with up
to 0.7 unit intervals (UIs) of high-frequency jitter. When
the repeater is not needed, it can be disabled to reduce
power consumption. A fully integrated phase-locked loop
(PLL) provides a frequency lock indication and does not
need an external reference clock.
19-1701; Rev 2; 2/01
Typical Operating Circuit appears at end of data sheet.
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
________________________Applications
2.125Gbps Fibre Channel
Fibre Channel Data Storage Systems
Storage Area Networks
Fibre Channel Hubs
________________________________________________________________ Maxim Integrated Products
General Description
Quad-Port Bypass with Repeater
o Four High-Speed Data Ports
o Meets Fibre Channel Jitter Tolerance
o Large Output Signal Swing (>1000mVp-p)
o +3.0V to +3.6V Single-Supply Voltage
o On-Chip Termination Resistors Compatible with
*EP = Exposed pad
* Exposed pad is connected to ground.
MAX3752CCM
LOUT1+
Requirements
75Ω Transmission Lines at All Ports
LOUT1-
CLKEN
LIN1+
LIN1-
GND
GND
GND
GND
GND
IN+
IN-
PART
10
11
12
1
2
3
4
5
6
7
8
9
2.125Gbps, 3.3V
TEMP. RANGE
Ordering Information
0°C to +70°C
TQFP-EP*
MAX3752
Pin Configuration
PIN-PACKAGE
48 TQFP-EP*
Features
36
35
34
33
32
31
30
29
28
27
26
25
GND
LOUT4+
LOUT4-
GND
LIN4+
LIN4-
GND
GND
OUT-
OUT+
GND
LOCK
1

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MAX3752 Summary of contents

Page 1

... Rev 2; 2/01 General Description The MAX3752 quad-port bypass IC is designed for use in the Fibre Channel Arbitrated Loop topology. This device consists of four serially connected port bypass circuits (PBCs) and a repeater that provides clock and data recovery (CDR). The quad-port bypass circuit allows connection four Fibre Channel L-Ports, which can each be enabled or bypassed by controlling the PBC select inputs ...

Page 2

Quad-Port Bypass with Repeater ABSOLUTE MAXIMUM RATINGS Supply Voltage, V ..............................................-0.5V to +5.0V CC Current into OUT+, OUT-, LOUT1+, LOUT1-, LOUT2+, LOUT2-, LOUT3+, LOUT3-, LOUT4+, LOUT4- ......................0 to 22mA Voltage at OUT+, OUT-, LOUT1+, LOUT1-, LOUT2+, LOUT2-, LOUT3+, ...

Page 3

... AC ELECTRICAL CHARACTERISTICS—MAX3752 Operating at 2.125Gbps (V = +3.0V to +3.6V 0°C to +70°C. Typical values are at +3.3V PARAMETER Data Rate Output Edge Speed 20% to 80% Pattern = K28.7+, CDR disabled Random Jitter at OUT± Pattern = K28.7+, CDR enabled Pattern = CRPAT, CDR enabled (Note 8) Pattern = K28.5, CDR disabled Deterministic Jitter at OUT± ...

Page 4

Quad-Port Bypass with Repeater AC ELECTRICAL CHARACTERISTICS (continued) Note 1: Includes output currents. Note 2: AC characteristics are guaranteed by design and characterization. Note 3: K28.7+ Pattern: 0011 1110 00. Note 4: Fibre Channel Random Pattern in hex ...

Page 5

V = +3.3V, unless otherwise noted OUTPUT JITTER—BATHTUB PLOT 1.00E+00 2Gbps CRPAT (NO JITTER ON INPUTS) 1.00E+02 1.00E+04 1.00E+06 1.00E+08 1.00E+10 1.00E+12 1.00E+14 0.0 0.1 0.2 0.3 0.4 0.5 DATA SAMPLING TIME RELATIVE TO ...

Page 6

Quad-Port Bypass with Repeater PIN NAME 11, 26, 29, 30, 33, 36, GND Electrical Ground 39, 42, 43 LIN1- Inverted Data Input for L-Port 1 3 LIN1+ Noninverted Data Input for L-Port ...

Page 7

... TTLIN CDREN Figure 1. Functional Diagram Detailed Description The MAX3752 quad PBC consists of an input buffer, a clock/data recovery circuit (for optional data recovery), four serially connected port bypass circuits, and an output buffer (Figure 1). The circuit design is optimized for both high-speed (2Gbps) and low-voltage (+3.3V) operation ...

Page 8

... Figure 2 shows the disk array. Figures 3 and 4 show models for the MAX3752 inputs and outputs. PORT BYPASS 0 SERIAL ...

Page 9

... Figure 3. MAX3752 Input Structure Cascading Port Bypass Circuits Two or more MAX3752 quad PBCs can be cascaded by directly connecting the OUT+ and OUT- pins of one quad PBC to the IN+ and IN- pins of the next quad PBC. See Typical Operating Circuit. Interfacing to 50Ω Systems ...

Page 10

... Filter voltage sup- plies, keep ground connections short, and use multiple 2.2nH vias where possible. Use controlled impedance trans- OUT+ mission lines to interface with the MAX3752 high-speed 0.4pF 0.2pF inputs and outputs. Power-supply decoupling capaci- tors should be placed very close ...

Page 11

... LOCKEN CFM 2 2 DISK DRIVE 2.125Gbps, 3.3V Typical Operating Circuit DISK DISK DRIVE DRIVE L_PORT n+4 L_PORT n+5 IN OUT SEL IN OUT SEL CDREN LOCK N.C. OUT+ MAX3752 OUT- CLKEN LOCKEN OUT SEL IN OUT SEL L_PORT n+6 L_PORT n+7 DISK DISK DRIVE DRIVE 11 ...

Page 12

Quad-Port Bypass with Repeater 12 ______________________________________________________________________________________ Package Information ...

Page 13

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 13 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products ...

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