AT90S8515

Manufacturer Part NumberAT90S8515
Description8-bit microcontroller with 8K bytes in-system programmable flash, 2.7-6.0V
ManufacturerATMEL Corporation
AT90S8515 datasheet
 
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Page 61/112:

External SRAM Connected to the AVR

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0841G–09/01
Default, the external SRAM access, is a 3-cycle scheme as depicted in Figure 43. When
one extra wait state is needed in the access cycle, set the SRW bit (one) in the MCUCR
register. The resulting access scheme is shown in Figure 44. In both cases, note that
PORTA is data bus in one cycle only. As soon as the data access finishes, PORTA
becomes a low-order address bus again.
For details of the timing for the SRAM interface, please refer to Figure 68, Table 37,
Table 38, Table 39 and Table 40, beginning on page 92. Refer to “Architectural Over-
view” on page 7 for a description of the memory map, including address space for
SRAM.
Figure 42. External SRAM Connected to the AVR
Port A
ALE
AVR
Port C
RD
WR
Figure 43. External Data SRAM Memory Cycles without Wait State
T1
System Clock Ø
ALE
Address [15..8]
Prev. Address
Data/Address [7..0]
Prev. Address
WR
Data/Address [7..0]
Prev. Address
RD
AT90S8515
D[7:0]
D
Q
A[7:0]
G
A[15:8]
RD
WR
T2
T3
Address
Address
Data
Address
Data
SRAM
Address
Address
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