ST7FLITE19F1M6 STMicroelectronics, ST7FLITE19F1M6 Datasheet
ST7FLITE19F1M6
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ST7FLITE19F1M6 Summary of contents
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MCU WITH SINGLE VOLTAGE FLASH MEMORY, Memories ■ – 4 Kbytes single voltage extended Flash (XFlash) Program memory with read-out pro- tection, In-Circuit Programming and In-Appli- cation programming (ICP and IAP). 10K write/ erase cycles guaranteed, data retention: 20 ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7LITE1 16.5 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 129 16.6 USING PB4 AS EXTERNAL INTERRUPT . . . . . . . . . . . . . ...
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INTRODUCTION The ST7LITE1 is a member of the ST7 microcon- troller family. All ST7 devices are based on a com- mon industry-standard 8-bit core, featuring an en- hanced instruction set. The ST7LITE1 features FLASH memory with byte-by-byte In-Circuit Programming ...
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ST7LITE1 2 PIN DESCRIPTION Figure 2. 20-Pin SO Package Pinout SS/AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 CLKIN/AIN4/PB4 AIN5/PB5 AIN6/PB6 6/131 RESET ei0 ei3 ...
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PIN DESCRIPTION (Cont’d) Legend / Abbreviations for Type input output supply In/Output level CMOS 0.3V T Output level 20mA high sink (on N-buffer only) Port and control configuration: – Input: ...
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ST7LITE1 Pin Pin Name No. PA6 /MCO/ 12 I/O ICCCLK/BREAK PA5 / 13 I/O C ICCDATA 14 PA4 I PA3/ATPWM1 I PA2/ATPWM0 I PA1/ATIC I PA0/LTIC I OSC2 O 20 ...
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REGISTER & MEMORY MAP As shown in Figure 3, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 256 bytes of RAM, 128 ...
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ST7LITE1 Table 2. Hardware Register Map Address Block Register Label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h PBDR 0004h Port B PBDDR 0005h PBOR 0006h 0007h 0008h LTCSR2 0009h LTARR LITE 000Ah LTCNTR TIMER 2 000Bh LTCSR1 000Ch ...
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Address Block Register Label 0037h ITC EICR 0038h MCC MCCSR 0039h Clock and RCCR 003Ah Reset SICSR 003Bh 003Ch ITC EISR 003Dh to 0048h 0049h AWUPR AWU 004Ah AWUCSR 004Bh DMCR 004Ch DMSR 004Dh DMBK1H 3) DM 004Eh DMBK1L 004Fh ...
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ST7LITE1 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The XFlash devices ...
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FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC interface ICP needs a minimum of 4 and pins to be connected to the programming tool. These pins are: – RESET: device reset – device power supply ground SS ...
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ST7LITE1 FLASH PROGRAM MEMORY (Cont’d) 4.5 Memory Protection There are two different types of memory protec- tion: Read Out Protection and Write/Erase Protec- tion which can be applied individually. 4.5.1 Read out Protection Readout protection, when selected provides a pro- ...
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DATA EEPROM 5.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non volatile back- up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. Figure 5. EEPROM Block ...
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ST7LITE1 DATA EEPROM (Cont’d) 5.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEP- ROM Control/Status register (EECSR). The flow- chart in Figure 6 describes these different memory access modes. Read ...
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DATA EEPROM (Cont’d) 2 Figure 7. Data E PROM Write Operation ⇓ Row / Byte ⇒ ROW DEFINITION Byte 1 Byte 2 Writing data latches E2LAT bit Set by USER application E2PGM bit Note programming cycle is interrupted ...
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ST7LITE1 DATA EEPROM (Cont’d) 5.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on ex- ecution of the WFI instruction of the microcontrol- ler or when the microcontroller enters Active-HALT mode.The DATA EEPROM will immediately enter ...
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DATA EEPROM (Cont’d) 5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EEC- SR) Read/Write Reset Value: 0000 0000 (00h Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This ...
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ST7LITE1 6 CENTRAL PROCESSING UNIT 6.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 MAIN FEATURES 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 main addressing ...
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CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This ...
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ST7LITE1 CPU REGISTERS (Cont’d) STACK POINTER (SP) Read/Write Reset Value: 01FFh SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free location ...
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SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. Main features Clock ...
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ST7LITE1 PHASE LOCKED LOOP (Cont’d) Figure 11. PLL Output Frequency Timing Diagram LOCKED bit set 4/8 x input freq. t LOCK t STARTUP When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs ...
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Figure 12. Clock Management Block Diagram CR7 CR6 CR5 Tunable 1% RC OSC,PLLOFF, OSCRANGE[2:0] Option bits CLKIN CLKIN CLKIN CLKIN OSC /OSC1 1-16 MHZ OSC2 or 32kHz f OSC /32 DIVIDER CR4 CR3 CR2 CR1 CR0 f CPU Oscillator PLL ...
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ST7LITE1 7.4 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multi- oscillator block (1 to 16MHz or 32kHz): an external source ■ 5 crystal or ceramic resonator oscillators ■ ...
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RESET SEQUENCE MANAGER (RSM) 7.5.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ These sources act on ...
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ST7LITE1 RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in the electrical characteris- tics section. 7.5.3 External ...
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SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Volt- age Detector (AVD) functions managed by the SICSR register. Note: A reset can also be triggered following the detection ...
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ST7LITE1 Figure 17. Reset and Supply Management Block Diagram RESET SEQUENCE RESET MANAGER (RSM 30/131 1 WATCHDOG TIMER (WDG) SYSTEM INTEGRITY MANAGEMENT SICSR WDGRF STATUS FLAG AVD Interrupt Request LOCKED LVDRF AVDF AVDIE ...
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SYSTEM INTEGRITY MANAGEMENT (Cont’d) 7.6.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between reference value and the V IT+(AVD) ply voltage (V ). The V AVD IT-(AVD) for falling ...
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ST7LITE1 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 7.6.3 Low Power Modes Mode Description No effect on SI. AVD interrupts cause the WAIT device to exit from Wait mode. The SICSR register is frozen. HALT The AVD remains active. 7.6.3.1 Interrupts The AVD ...
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SYSTEM INTEGRITY MANAGEMENT (Cont’d) 7.6.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 0000 0xx0 (0xh) 7 WDG LOCKED LVDRF AVDF AVDIE RF Bit 7:5 = Reserved, must be kept cleared. Bit 4 = ...
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ST7LITE1 8 INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in ...
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INTERRUPTS (Cont’d) Figure 19. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION Table 5. Interrupt Mapping Source N° Block RESET Reset TRAP Software Interrupt 0 AWU Auto Wake Up Interrupt 1 ei0 External Interrupt 0 2 ei1 External Interrupt 1 3 ...
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ST7LITE1 INTERRUPTS (Cont’d) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS31 IS30 IS21 IS20 IS11 Bit 7:6 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei3 (Port B0) according to Table Bit ...
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INTERRUPTS (Cont’d) Bit 3:2 = ei1[1:0] ei1 pin selection These bits are written by software. They select the Port A I/O pin used for the ei1 external interrupt ac- cording to the table below. External Interrupt I/O pin selection ei11 ...
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ST7LITE1 9 POWER SAVING MODES 9.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, five main pow- er saving modes are implemented in the ST7 (see Figure 20): Slow ■ Wait ...
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POWER SAVING MODES (Cont’d) 9.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT ...
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ST7LITE1 POWER SAVING MODES (Cont’d) 9.4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when ACTIVE-HALT is disabled (see section 9.5 on page 41 when the ...
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POWER SAVING MODES (Cont’d) 9.4.1 Halt Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O ...
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ST7LITE1 POWER SAVING MODES (Cont’d) Figure 25. ACTIVE-HALT Timing Overview ACTIVE 256 OR 4096 CPU RUN HALT CYCLE DELAY RESET OR HALT INTERRUPT INSTRUCTION [Active Halt Enabled] Figure 26. ACTIVE-HALT Mode Flow-chart OSCILLATOR PERIPHERALS HALT INSTRUCTION CPU (Active Halt enabled) ...
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POWER SAVING MODES (Cont’d) Similarities with Halt mode The following AWUFH mode behaviour is the same as normal Halt mode: – The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or a re- ...
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ST7LITE1 POWER SAVING MODES (Cont’d) Figure 29. AWUFH Mode Flow-chart HALT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) ENABLE 0 1) WDGHALT 1 AWU RC OSC WATCHDOG MAIN OSC RESET PERIPHERALS CPU I[1:0] BITS INTERRUPT AWU RC OSC Y MAIN ...
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POWER SAVING MODES (Cont’d) 9.6.0.1 Register Description AWUFH CONTROL/STATUS REGISTER (AWUCSR) Read/Write Reset Value: 0000 0000 (00h Bits 7:3 = Reserved. Bit 1= AWUF Auto Wake Up Flag This bit is set by hardware ...
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ST7LITE1 10 I/O PORTS 10.1 INTRODUCTION The I/O ports allow data transfer. An I/O port can contain pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may ...
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I/O PORTS (Cont’d) Figure 30. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS From on-chip periphera ALTERNATE ENABLE BIT DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT REQUEST ( SENSITIVITY ...
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ST7LITE1 I/O PORTS (Cont’d) Table 9. I/O Configurations PAD PAD PAD Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function ...
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I/O PORTS (Cont’d) Analog alternate function Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected ...
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ST7LITE1 I/O PORTS (Cont’d) 10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION The I/O port register configurations are summa- rised as follows. Standard Ports PA7:0, PB6:0 MODE floating input pull-up input open drain output push-pull output Table 10. Port Configuration (Standard ports) Port ...
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ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program ...
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ST7LITE1 WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. This downcounter is free- running: it counts down even if the watchdog is disabled. The ...
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WATCHDOG TIMER (Cont’d) 11.1.5 Interrupts None. 11.1.6 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware ...
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ST7LITE1 WATCHDOG TIMER (Cont’d) Table 13. Watchdog Timer Register Map and Reset Values Address Register Label (Hex.) WDGCR WDGA 002Eh Reset Value 54/131 ...
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AUTORELOAD TIMER 2 (AT2) 11.2.1 Introduction The 12-bit Autoreload Timer can be used for gen- eral-purpose timing functions based on a free- running 12-bit upcounter with an input capture reg- ister and four PWM output channels. ...
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ST7LITE1 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.3 Functional Description PWM Mode This mode allows up to four Pulse Width Modulat- ed signals to be generated on the PWMx output pins. The PWMx output signals can be enabled or disabled using the ...
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AUTORELOAD TIMER (Cont’d) Figure 36. PWM Signal from 0% to 100% Duty Cycle f COUNTER COUNTER FFDh DCRx=000h DCRx=FFDh DCRx=FFEh DCRx=000h Output Compare Mode To use this function, load a 12-bit value in the DCRxH and DCRxL registers. When ...
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ST7LITE1 Figure 37. Block Diagram of Break Function BREAK pin (Active Low) BA PWM0 PWM1 PWM2 PWM3 Note: The BREAK pin value is latched by the BA bit. 11.2.3.1 Input Capture The 12-bit ATICR register is used to latch the ...
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AUTORELOAD TIMER (Cont’d) 11.2.4 Low Power Modes Mode Description The input frequency is divided SLOW by 32 WAIT No effect on AT timer AT timer halted except if CK0=1, ACTIVE-HALT CK1=0 and OVFIE=1 HALT AT timer halted 11.2.5 Interrupts ...
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ST7LITE1 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATCSR) Read / Write Reset Value: 0x00 0000 (x0h ICF ICIE CK1 CK0 Bit 7 = Reserved. Bit 6 = ICF Input Capture Flag. This ...
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AUTORELOAD TIMER (Cont’d) AUTORELOAD REGISTER (ATRH) Read / Write Reset Value: 0000 0000 (00h ATR11 ATR10 ATR9 AUTORELOAD REGISTER (ATRL) Read / Write Reset Value: 0000 0000 (00h) 7 ATR7 ATR6 ATR5 ATR4 ATR3 ...
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ST7LITE1 12-BIT AUTORELOAD TIMER (Cont’d) Bit 4 = BPEN Break Pin Enable. This bit is read/write by software and cleared by hardware after Reset. 0: Break pin disabled 1: Break pin enabled Bit 3:0 = PWM[3:0] Break Pattern. These bits ...
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AUTORELOAD TIMER (Cont’d) Table 14. Register Map and Reset Values Address Register Label (Hex.) ATCSR 0D Reset Value CNTRH 0E Reset Value CNTRL CNTR7 0F Reset Value ATRH 10 Reset Value ATRL ATR7 11 Reset Value PWMCR 12 Reset ...
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ST7LITE1 Address Register Label (Hex.) TRANCR 21 Reset Value BREAKCR 22 Reset Value 64/131 BPEN PWM3 PWM2 PWM1 ...
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LITE TIMER 2 (LT2) 11.3.1 Introduction The Lite Timer can be used for general-purpose timing functions based on two free-running 8- bit upcounters, an 8-bit input capture register. 11.3.2 Main Features Realtime Clock ■ – One 8-bit ...
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ST7LITE1 LITE TIMER (Cont’d) 11.3.3 Functional Description 11.3.3.1 Timebase Counter 1 The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from frequency of f overflow event ...
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LITE TIMER (Cont’d) – The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure advised to clear all occurrences of the data value 0x8E from memo- ry. For ...
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ST7LITE1 LITE TIMER (Cont’d) LITE TIMER COUNTER 2 (LTCNTR) Read only Reset Value: 0000 0000 (00h) 7 CNT7 CNT7 CNT7 CNT7 CNT3 Bits 7:0 = CNT[7:0] Counter 2 Reload Value. This register is read by software. The LTARR val- ue ...
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LITE TIMER (Cont’d) Table 15. Lite Timer Register Map and Reset Values Address Register Label (Hex.) LTCSR2 08 Reset Value LTARR AR7 09 Reset Value LTCNTR CNT7 0A Reset Value LTCSR1 ICIE 0B Reset Value LTICR ICR7 0C Reset Value ...
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ST7LITE1 11.4 SERIAL PERIPHERAL INTERFACE (SPI) 11.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 42. The MOSI pins are connected together and the MISO pins are connected together. In this ...
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ST7LITE1 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The ...
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ST7LITE1 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 45). Note: The idle state of SCK must correspond to the polarity ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.5 Error Flags 11.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set and an ...
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ST7LITE1 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.5.4 Single Master Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using a as the master and ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the Device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ation ...
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ST7LITE1 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.4.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when ...
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ST7LITE1 Table 17. SPI Register Map and Reset Values Address Register Label (Hex.) SPIDR MSB 0031h Reset Value SPICR SPIE 0032h Reset Value SPICSR SPIF 0033h Reset Value 80/131 SPE SPR2 MSTR 0 ...
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A/D CONVERTER (ADC) 11.5.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer ...
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ST7LITE1 10-BIT A/D CONVERTER (ADC) (Cont’d) 11.5.3.2 Input Voltage Amplifier The input voltage can be amplified by a factor enabling the AMPSEL bit in the ADCDRL regis- ter. When the amplifier is enabled, the input range is ...
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A/D CONVERTER (ADC) (Cont’d) 11.5.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 CH3 Bit 7 = EOC End of Conversion This bit is set by ...
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ST7LITE1 Bit 2 = AMPSEL Amplifier Selection Bit This bit is set and cleared by software. 0: Amplifier is not selected 1: Amplifier is selected Table 18. ADC Register Map and Reset Values Address Register Label (Hex.) ADCCSR 0034h Reset ...
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INSTRUCTION SET 12.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) ...
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ST7LITE1 ST7 ADDRESSING MODES (Cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait ...
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ST7 ADDRESSING MODES (Cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register ...
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ST7LITE1 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift ...
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INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL ...
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ST7LITE1 INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset ...
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ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 13.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ...
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ST7LITE1 13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 13.2.1 Voltage Characteristics ...
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OPERATING CONDITIONS 13.3.1 General Operating Conditions: Suffix 6 Devices T = -40 to +85°C unless otherwise specified. A Symbol Parameter V Supply voltage DD External clock frequency on f CLKIN CLKIN pin Figure 51. f Maximum Operating Frequency Versus ...
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ST7LITE1 13.3.2 Operating Conditions with Low Voltage Detector (LVD -40 to 85°C, unless otherwise specified A Symbol Parameter Reset release threshold V (LVD) IT+ (V rise) DD Reset generation threshold V (LVD) IT- (V fall LVD ...
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OPERATING CONDITIONS (Cont’d) The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables. 13.3.4.1 Devices with ‘”6” order code suffix (tested for T Symbol Parameter Internal RC oscillator fre quency Accuracy of Internal RC ...
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ST7LITE1 OPERATING CONDITIONS (Cont’d) 13.3.4.2 Devices with ‘”6” order code suffix (tested for T Symbol Parameter Internal RC oscillator fre quency Accuracy of Internal RC ACC oscillator when calibrated RC with RCCR=RCCR1 RC oscillator current con- I DD(RC) ...
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OPERATING CONDITIONS (Cont’d) Figure 52. RC Osc Freq vs V (Calibrated with RCCR1 25°C) 1.00 0.90 0.80 0.70 0.60 0.50 2.4 2.6 2.8 3 3.2 VDD (V) Figure 54. Typical RC oscillator Accuracy vs temperature @ V =5V ...
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ST7LITE1 OPERATING CONDITIONS (Cont’d) Figure 56. PLL ∆f /f CPU CPU ∆f /f CPU CPU Max 0 Min Figure 57. PLLx4 Output vs CLKIN frequency 7.00 6.00 5.00 4.00 3.00 2.00 1.00 1 1.5 External Input Clock Frequency (MHz) Note: ...
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SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- 13.4.1 Supply Current T = -40 ...
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ST7LITE1 SUPPLY CURRENT CHARACTERISITCS (Cont’d) Figure 61. Typical I in WAIT vs 4.5 4.0 8Mhz 3.5 4Mhz 3.0 2.5 1MHz 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 Vdd (V) Figure 62. Typical I in SLOW-WAIT ...
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CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 13.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = ∆t v(IT v(IT) c(INST) Notes: 1. Guaranteed by Design. Not ...
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ST7LITE1 13.6 MEMORY CHARACTERISTICS T = -40°C to 85°C, unless otherwise specified A 13.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 13.6.2 FLASH Program Memory Symbol Parameter V Operating voltage for Flash write/erase DD Programming time ...
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EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed ...
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... Dynamic latch-up class Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...
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I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V 1) hys hysteresis I Input leakage current ...
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ST7LITE1 I/O PORT PIN CHARACTERISTICS (Cont’d) 13.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 70) 1) ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 69. Typical 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 0. lio (mA) Figure 71. Typical 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 ...
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ST7LITE1 I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 74. Typical 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.01 -1 lio (mA) Figure 75. Typical 1.20 1.00 0.80 0.60 0.40 0.20 0.00 ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 79. Typical V vs 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 2.4 2.7 VDD (V) Figure 80. Typical V vs 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 2.4 ...
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ST7LITE1 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin T = -40°C to 85°C, unless otherwise specified A Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys V Output ...
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CONTROL PIN CHARACTERISTICS (Cont’d) Figure 82. RESET pin protection when LVD is enabled. EXTERNAL RESET Recommended Figure 83. RESET pin protection when LVD is disabled. Recommended V DD 0.01µF USER EXTERNAL RESET CIRCUIT 0.01µF Required 1. The reset network protects ...
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ST7LITE1 13.10 COMMUNICATION INTERFACE CHARACTERISTICS 13.10.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f SCK = SPI clock frequency 1/t c(SCK) t r(SCK) SPI ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 85. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=0 CPOL=0 CPHA=0 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t MOSI INPUT Figure 86. SPI Master Timing ...
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ST7LITE1 13.11 10-BIT ADC CHARACTERISTICS Subject to general operating condition for V Symbol Parameter f ADC clock frequency ADC V Conversion voltage range AIN R External input resistor AIN C Internal sample and hold capacitor ADC t Stabilization time after ...
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ADC CHARACTERISTICS (Cont’d) ADC Accuracy with V =5.0V DD Symbol Parameter |E | Total unadjusted error Offset error Gain Error Differential linearity error Integral linearity error ...
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ST7LITE1 ADC CHARACTERISTICS (Cont’d) Figure 89. ADC Accuracy Characteristics with amplifier enabled Digital Result ADCDR 704 V – 1LSB = ------------------------------- - IDEAL 1024 LSB 108 62.5mV ...
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ADC CHARACTERISTICS (Cont’d) Symbol Parameter V Amplifier operating voltage DD(AMP) V Amplifier input voltage IN V Amplifier output offset voltage OFFSET V Step size for monotonicity STEP Linearity Output Voltage Response Gain factor Amplified Analog input Gain Vmax Output Linearity ...
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ST7LITE1 14 PACKAGE CHARACTERISTICS 14.1 PACKAGE MECHANICAL DATA Figure 90. 20-Pin Plastic Small Outline Package, 300-mil Width 118/131 h x 45× inches Dim. Min Typ Max Min A 2.35 2.65 ...
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PACKAGE CHARACTERISTICS (Cont’d) Table 21. THERMAL CHARACTERISTICS Symbol Package thermal resistance R thJA (junction to ambient) P Power dissipation D T Maximum junction temperature Jmax Notes: 1. The power dissipation is obtained from the formula P and P is the ...
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ST7LITE1 14.2 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines. Figure 91. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) 250 200 150 Temp. [°C] 100 PREHEATING PHASE Figure 92. Recommended ...
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DEVICE CONFIGURATION Each device is available for production in user pro- grammable versions (FLASH). 15.1 OPTION BYTES The two option bytes allow the hardware configu- ration of the microcontroller to be selected. The option bytes can be accessed only ...
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ST7LITE1 OPTION BYTES (Cont’d) OPTION BYTE 1 OPT7 = PLLx4x8 PLL Factor selection. 0: PLLx4 1: PLLx8 OPT6 = PLLOFF PLL disable. 0: PLL enabled 1: PLL disabled (by-passed) OPT5 = PLL32OFF 32MHz PLL disable. 0: PLL32 enabled 1: PLL32 ...
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... DEVICE ORDERING INFORMATION Table 24. Supported part numbers Program Part Number Memory (Bytes) ST7FLITE10F1M6 ST7FLITE15F1M6 4K FLASH ST7FLITE19F1M6 Data RAM EEPROM (Bytes) (Bytes) 256 - - -40°C to 85°C 128 ST7LITE1 Temp. Package Range SO20 SO20 SO20 123/131 ...
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... ST7LITE1 15.3 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 micro- controller family. Full details of tools available for the ST7 from third party manufacturers can be ob- tained from the STMicroelectronics Internet site: http//www.st.com. Tools from these manufacturers include C compli- ers, evaluation tools, emulators and programmers ...
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ST7 APPLICATION NOTES Table 26. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY ...
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ST7LITE1 Table 26. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1526 ST7FLITE0 QUICK REFERENCE NOTE AN1709 EMC DESIGN FOR ST MICROCONTROLLERS AN1752 ST72324 QUICK REFERENCE NOTE PRODUCT EVALUATION AN 910 PERFORMANCE BENCHMARKING AN 990 ...
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Table 26. ST7 Application Notes IDENTIFICATION DESCRIPTION PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO- AN1179 GRAMMING) AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY AN1478 PORTING AN ...
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ST7LITE1 16 IMPORTANT NOTES 16.1 EXECUTION OF BTJX INSTRUCTION When testing the address $FF with the "BTJT" or "BTJF" instructions, the CPU may perform an in- correct operation when the relative jump is nega- tive and performs an address page ...
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REVISION HISTORY Table 27. Revision History Date Revision Changed Added note on RC oscillator in 7.1 on page July 03 1.3 Changed Added note in Changed Added note in the description of OSC option bit and in Revision number ...
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ST7LITE1 Changed FMP_R option bit description in Changed “DEVELOPMENT TOOLS” on page 124 Added notes indicating that PB4 cannot be used as an external interrupt in HALT mode, tion 16.6 on page 128 Dec-2004 2.0 Added “NEGATIVE INJECTION IMPACT ON ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. Australia – ...