DS80CH11 Maxim Integrated Products, DS80CH11 Datasheet
DS80CH11
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DS80CH11 Summary of contents
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... System Energy Manager PRODUCT SPECIFICATION V2.1 DS80CH11 DS80CH11 011200 1/88 ...
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... DS80CH11 1.0 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 DETAILED FEATURE SUMMARY 1.3 CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... DS80CH11 41 ...
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... DS80CH11 12.1.1 Microcontroller Power Fail Reset 12.2 LOW POWER OPERATING MODES 12.2.1 Slow Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1.1 Crystaless Slow Clock Mode 12.2.1.2 Slow Clock Mode Operation 12.2.1.3 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... A/D converter with external refer- ence so that its firmware can perform battery manage- ment tasks without burdening the host CPU. A four– DS80CH11 channel 8–bit pulse–width modulator allows digital control of functions such as LCD contrast and bright- ness. An 8–bit port is provided for key scan inputs. A ...
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... DS80CH11 CONTROLLER BLOCK DIAGRAM Figure 1–1 P7.7 / AMI.7 / LED.7 XTAL1 XTAL2 3 PORT 7 / VCC uC ACT. MONITOR / CLK OSC. LED CONTROL VPFW VRST 3 GND SCRATCHPAD SYS. CLOCK REGISTERS CONTROL ALE (256 BYTES) PSEN RST SPECIAL WATCHDOG FUNCTION TIMER REGISTERS P3 P3 TIMER 2 P3 TIMER 1 P3 TIMER 0 P3 ...
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... Port 10: GPIO Analog Input/Output: – Eight–channel, 10–bit A/D with power down mode supports charging NiMH rechargeable cells DS80CH11 – 4–channel, 8–bit PWM supports LCD brightness and contrast control 2–Wire Bi–directional Serial Buses – Master/slave multi–drop operation – Manages on–board slaves or external I/O ...
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... DS80CH11 2.0 PIN DESCRIPTION 128–TQFP PIN ASSIGNMENT Figure 2–1 P9.7 / KSO.15 1 P9.6 / KSO.14 2 P9.5 / KSO.13 3 P9.4 / KSO.12 4 P9.3 / KSO.11 5 P9.2 / KSO.10 6 P9.1 / KSO.9 7 P9.0 / KSO.8 8 P8.7 / KSO.7 9 P8.6 / KSO.6 10 P8.5 / KSO.5 11 P8.4 / KSO P8.3 / KSO.3 14 P8.2 / KSO.2 15 P8.1 / KSO.1 16 P8.0 / KSO.0 17 GND 18 VCC 19 P6.7 / SOC 20 P6.6 P6.5 / PWI P6.4 / PWI.0 23 P6.3 / PWO.3 24 P6.2 / PWO.2 P6.1 / PWO.1 25 P6.0 / PWO.0 26 P5.7 / AI.7 27 P5.6 / AI.6 28 P5.5 / AI.5 29 P5.4 / AI.4 30 P5.3 / AI.3 31 P5.2 / AI.2 32 P5.1 / AI.1 33 P5.0 / AI.0 34 GND ...
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... This bus is used to read external ROM and read/write external RAM memory 126 P0.5 (AD5) or peripherals. When used as a memory bus, the port provides active high drivers. The 127 P0.6 (AD6) reset condition of Port 0 is tri–state. Pull–up resistors are required when using Port 0 as 128 P0.7 (AD7) an I/O port. DS80CH11 DESCRIPTION 011200 9/88 ...
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... DS80CH11 PIN SYMBOL 87 P1.0 (T2) Port 1/ (Alternate Functions): – I/O. Port 1 provides eight lines which can be individu- 88 P1.1 (T2EX) ally selected as bi–directional I/O port pins or as the alternate functions listed below: 89 P1.2 SCL1 90 P1.3 SDA1 Alternate 91 P1.4 SCL2 Port Function 92 P1.5 SDA2 P1 P1.6 P1.1 T2EX 94 P1.7 P1.2 SCL1 P1.3 SDA1 P1.4 SCL2 P1.5 SDA2 P1 ...
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... P8.4 (KSO.4) 11 P8.5 (KSO.5) 10 P8.6 (KSO.6) 9 P8.7 (KSO.7) DS80CH11 DESCRIPTION Description PWM 0 output (active high drive when enabled) PWM 1 output (active high drive when enabled) PWM 2 output (active high drive when enabled) PWM 3 output (active high drive when enabled) Optional clock input for PWM channels 0 and 2 ...
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... DS80CH11 PIN SYMBOL 8 P9.0 (KSO.8) Port 9 / KSO.15–8: – I/O. Port 9 provides eight lines of open–drain psuedo–bi–direc- 7 P9.1 (KSO.9) tional I/O port pins. Typically, these lines are used for key–scan outputs. 6 P9.2 (KSO.10) 5 P9.3 (KSO.11) 4 P9.4 (KSO.12) 3 P9.5 (KSO.13) 2 P9.6 (KSO.14) 1 P9.7 (KSO.15) 60 P10.0 Port10: –I/O. Port 10 provides eight lines of general purpose Input or Output. ...
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... VCC has dropped below the VRST voltage threshold. 118 XTAL1 C Crystal Oscillator Inputs. XTAL1 and XTAL2 provide support for parallel resonant, 119 XTAL2 AT cut crystals. XTAL1 acts also as an input if there is an external clock source in place of a crystal. XTAL2 serves as the output of the crystal amplifier. DS80CH11 DESCRIPTION 011200 13/88 ...
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... DS80CH11 2.2 PIN CHARACTERISTICS POWER DOWN PIN NAME MODE STATE 36 A0 – 43 AGND – 106 ALE Low 46 AVCC – 17 GND – 35 GND – 86 GND – 117 GND – 47 HGND – 68 HVCC – 38 IOR – 37 IOW – 42 KBCS – 40 KBOBF Hold 57 NC – ...
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... P4.6 / KSI.6 Hold 84 P4.7 / KSI.7 Hold 34 P5.0 / AI.0 Hold 33 P5.1 / AI.1 Hold 32 P5.2 / AI.2 Hold 31 P5.3 / AI.3 Hold DS80CH11 RESET I/O BUFFER TYPE STATE Open–drain High–Z Open–drain High–Z Open–drain High–Z Open–drain High–Z Pull–up Weak High Pull–up Weak High Pull–up Weak High Pull– ...
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... DS80CH11 2.2 PIN CHARACTERISTICS (cont’d) POWER DOWN PIN NAME MODE STATE 30 P5.4 / AI.4 Hold 29 P5.5 / AI.5 Hold 28 P5.6 / AI.6 Hold 27 P5.7 / AI.7 Hold 26 P6.0 / PWO.0 Hold 25 P6.1 / PWO.1 Hold 24 P6.2 / PWO.2 Hold 23 P6.3 / PWO.3 Hold 22 P6.4 / PWI.0 Hold 21 P6.5 / PWI.1 Hold 20 P6.6 Hold 19 P6.7 / SOC Hold 69 P7.0 / AMI.0 / Hold LED.0 70 P7.1 / AMI.1 / Hold LED.1 71 P7.2 / AMI.2 / Hold LED.2 72 P7.3 / AMI.3 / Hold LED ...
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... SMI1 Hold 58 SMI2 Hold 18 VCC – 85 VCC – 120 VCC – DS80CH11 RESET I/O BUFFER TYPE STATE Open–drain High–Z Open–drain High–Z Open–drain High–Z Open–drain High–Z Open–drain High–Z Open–drain High–Z Open– ...
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... DS80CH11 2.2 PIN CHARACTERISTICS (cont’d) POWER DOWN PIN NAME MODE STATE 101 VPFW (note 3) 44 VRH – 45 VRL – 102 VRST (note 3) 118 XTAL1 – 119 XTAL2 H PIN STATE DESCRIPTIONS High–Z High Impedance Enabled Power applied; electrically functioning input Unchanged ...
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... However, counter/timers default to run at the older 12 clocks per increment. Therefore, while soft- ware runs at higher speed, timer–based events need no modification to operate as before. Timers can be set to DS80CH11 run at 4 clocks per increment cycle to take advantage of higher speed operation. The relative time of two instructions might be different in the new architecture than it was previously. For exam- ple, in the original architecture, the “ ...
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... DS80CH11 INSTRUCTION SET SUMMARY Table 3–1 (cont’d) OSCILLATOR INSTRUCTION BYTE CYCLES Arithmetic Instructions: ADD ADD A, direct 2 8 ADD A, @ ADD A, #data 2 8 ADDC ADDC A, direct 2 8 ADDC A, @ ADDC A, #data 2 8 SUBB SUBB A, direct ...
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... The following table summarizes the speed improve- ment of the High Speed Micro core over a standard 12 clock / machine cycle 8052 device. #Opcodes Speed Improvement 159 2.4 x 255 Average: 2.5 DS80CH11 ANL C, bit ANL C, bit ORL C, bit 2 8 ORL C, bit 2 8 MOV C, bit 2 ...
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... DS80CH11 3.6 INTERRUPT CONTROL The SEM provides 16 sources of interrupt with three priority levels. The Power–fail Interrupt (PFI), if enabled, always has the highest priority. There are two remaining user selectable priorities: high and low. If two interrupts that have the same priority occur simulta- INTERRUPT PRIORITY Table 3– ...
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... ENABLE LOC. PRIORITY E2W1 EIE.0 P2W1 EAD EIE.1 PAD E2W2 EIE.2 P2W2 EKB EIE.3 PKB EPB1 EIE.4 PPB1 KDF.7–0 EKD EIE.5 PKD EWDI EIE.6 PWDI EPB2 EIE.7 PPB2 DS80CH11 PRIORITY LOC. EIP.0 EIP.1 EIP.2 EIP.3 EIP.4 EIP.5 EIP.6 EIP.7 011200 23/88 ...
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... DS80CH11 4.0 MEMORY RESOURCES 4.1 OVERVIEW The SEM contains the following memory resources and features: 256 bytes of on–chip direct (scratchpad) RAM 256 bytes of on–chip MOVX data RAM Off–chip program and data memory expansion Software enable/disable of on–chip data memory 4.2 DATA MEMORY ACCESS Unlike many 8051 derivatives, the SEM contains on– ...
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... DIRECT (SCRATCHPAD) RAM ACCESS The SEM incorporates a full 256 bytes of direct RAM. This RAM is accessed in a manner identical to that of a DS80CH11 standard 80C52 compatible device. A full description of this memory along with the instructions that access it is contained in the Dallas High Speed Micro User’s Guide. ...
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... DS80CH11 SPECIAL FUNCTION REGISTER RESET VALUES Table 4–2 * New functions are in bold EIP F8h 00000000 B F0h 00000000 EIE E8h 00000000 ACC E0h 00000000 WDCON 2WCON2 2WSTAT12 2WSTAT22 D8h 0X0X0XX0 00000000 00000000 00000000 PSW 2WSADR2 2WDAT2 2WFS2 D0h 00000000 00000000 00000000 00000000 ...
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... P2.4 P2.3 P2.2 P2.1 P2.0 P4.4 P4.3 P4.2 P4.1 P4.0 KDE4 KDE3 KDE2 KDE1 KDE0 KDF4 KDF3 KDF2 KDF1 KDF0 ES0 ET1 EX1 ET0 EX0 DS80CH11 ADDRESS 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 90h 91h 92h 93h 94h 95h 98h 99h 9Ah ...
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... DS80CH11 SPECIAL FUNCTION REGISTER LOCATIONS Table 4–3 (cont’d) * New functions are in bold REGISTER BIT 7 BIT 6 BIT 5 PORT5 P5.7 P5.6 P5.5 KBSTAT KST7 KST6 KST5 KBDIN KBDOUT PORT3 P3.7 P3.6 P3.5 ADCON1 STRT/ EOC CONT/ BSY SS ADCON2 OUTCF MUX2 MUX1 ADC9/ ADC8/ ADC7/ ADMSB ADLSB ADC7 ...
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... PW3 PW3 PW3 PW3 T T/C P10.4 P10.3 P10.2 P10.1 P10.0 PC/D2 P2ST2 PIBF2 POBF2 PPB1 PKB P2W2 PAD P2W1 DS80CH11 ADDRESS D5h D6h D7h D8h D9h DAh DBh DDh DEh DFh E0h E4h E5h E6h E7h E8h ECh EDh EEh EFh F0h ...
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... DS80CH11 5.0 CORE I/O RESOURCES The SEM incorporates a full complement of the 80C52–compatible I/O resources as well as a number of specialized I/O resources which are associated with the Dallas High–Speed micro core. These features are described in this section. 5.1 PROGRAMMABLE TIMERS Three programmable timers are included which are compatible with the standard 80C52 ...
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... I serve the alternate function. In order to use the alternate function, the associated port latch must be programmed The alternate func- tions are summarized in Table 5–2 below. ALTERNATE FUNCTION(S) DS80CH11 011200 31/88 ...
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... DS80CH11 PORT PIN ALTERNATE FUNCTIONS Table 5–2 (cont’d) P3.0 RXD0 UART Receive P4.7 – P4.0 KSI.7 – KSI.0 Keyboard scan inputs P5.7 – P5.0 AI.7 – AI.0 A/D analog inputs P6.7 SOC A/D start of conversion input P6.6 – (None) P6.5 – P6.4 PWI.1 – PWI.0 PWM channels 1 and 0 inputs P6.3 – P6.0 PWO.3 – PWO.0 PWM channels and 0 outputs P7.7 – ...
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... REGISTER EN 0DAH 2WSTAT2x – STATUS RD EN REGISTER 09FH 0DBH 2WDATx – RECEIVE RD DATA BUFFER 09BH EN 0D2H DOUT SHIFT WR ACK DIN REGISTER 09BH EN 0D2H MSB LSB TIMING & ARBITRATION CONTROL LOGIC LOGIC SERIAL CLOCK GEN. DS80CH11 SDAx PIN SCLx PIN 011200 33/88 ...
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... DS80CH11 6.2 REGISTER DESCRIPTION The microcontroller interface to either 2–Wire serial port consists of six Special Function Registers (SFR’s), per 6.2.1 2WFSx – 2–Wire Frequency Select Registers 2WFS1; SFR ADDR.=09CH, 2WFS2; SFR ADDR.=0D3H BIT 7 BIT 6 BIT 5 BIT 4 Read/Write Access: Unrestricted. Initialization: 00H on any type of reset The 2– ...
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... If the STAx bit remains set while in the master mode throughout the time that a byte is being transmitted or received, then a repeat START condition will be asserted at the end of the byte transfer. Again, TSTAx will be set when the repeat start is successfully asserted. DS80CH11 BIT 3 BIT 2 BIT 1 BIT 0 BMMx ANAKx – ...
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... DS80CH11 port will generate an interrupt for every action on the bus even when it is not operating as a master or being addressed as a slave result, when a transfer takes place between an external master and slave, the port will be notified of a transmitted START condition, will receive the subsequent address and data bytes on the 6 ...
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... Both on–chip 2–Wire ports support four modes of operation: Master transmitter, Master receiver, Slave transmitter, and Slave Receiver. Operating the ports in these four modes is described in detail below. Following any type of reset, both 2–Wire ports will be configured in slave receive mode DS1621 8–BIT uC DIGITAL w/ 2–Wire I/F THERMOMETER DS80CH11 011200 37/88 ...
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... DS80CH11 DATA TRANSFER ON EITHER 2–WIRE BUS Figure 6–3 R/W DIR. BIT SDAx MSB SLAVE ADDRESS RECEIVER SCLx CLOCK LINE HELD LOW XMIT: UNTIL SHIFT REG. LOAD START RECEIVE: REC. BUF. FULL CONDITION 6.3.1 Master Transmit In the master transmit mode, the SEM is configured as a master device and transfers a number of data bytes to a slave receiver. A timing diagram in Figure 6– ...
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... STOx. After the STOP condi- tion is sent, the STOx bit will be automatically cleared and X/Rx will be cleared to 0. DS80CH11 In the Master transmit mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the 2–Wire bus. If another device on the bus over- ...
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... DS80CH11 MASTER RECEIVE OPERATION TIMING Figure 6–5 Ç Ç É É É É Ç Ç S SDAx/SCLx Ç Ç Ç Ç É É É É SLAVE ADDR. Ç Ç Ç Ç (Sr) É É É É STAx BIT TSTAx BIT X/Rx BIT DATA BUF: ...
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... Slave Transmit Figure 6–7 illustrates the timing for Slave Transmit mode operation. In this mode the SEM, addressed as a slave, transfers one or more bytes to the bus master. The transfer is initiated by the external master beginning with either a START or Repeat START condition, fol- DS80CH11 011200 41/88 ...
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... DS80CH11 lowed by the transmission of the SEM’s slave address with the direction bit set to 1. This byte will be shifted in and loaded into the receive buffer register at the time the acknowledge bit is returned to the master, resulting in SLAVE TRANSMIT OPERATION TIMING Figure 6–7 Ç ...
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... Slave Receive operation as shown in Figure 6–6. The exceptions to this timing are summa- rized as follows additional interrupt will be gener- DS80CH11 ated when a Receive START condition is detected as indicated by RSTAx = 1. This will inform the firmware of the start of a message and allow it to identify the next byte as an address ...
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... DS80CH11 7.0 A/D CONVERTER 7.1 OVERVIEW A self–contained A/D converter is provided on the SEM. Its major features are summarized below: 10–bit resolution True 9–bit accuracy: total error no greater than + 2 LSB’s Monotonic with no missing codes eight multiplexed inputs Shared analog/digital pins with 60 dB isolation Digital window comparator / alarm Low power consumption The A/D subsystem consists of a 10– ...
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... If the DAC output is greater than the analog input the bit is reset. After all bits have been tested and set or reset accordingly, the binary value in SAR[9.. digital representation of the ana- log input value. DS80CH11 STADC 011200 45/88 ...
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... DS80CH11 SAR A/D SIMPLIFIED BLOCK DIAGRAM Figure 7–2 ACLK START CONTROL LOGIC EOC RESOLUTION ANALOG IN REFHI REFLO ZRO (SAMPLE) 7.5 CONVERSION TIME An internal clock signal called ACLK is used to clock the successive approximation logic in performing the A/D conversion. ACLK is derived from the microcontroller clock signal through divide–down logic. A total of 16 clock cycles are required to perform the conversion ...
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... The state of the WCM flag can be expressed by the following Boolean equa- tion: WCM = WCIO (WINHI < ADR9–2) ADR9–2) Figure 7–3 illustrates the ranges that can be examined using the window comparator. DS80CH11 25.000 MHz – – – – – ...
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... DS80CH11 WINDOW COMPARATOR OPERATION Figure 7–3 3FFH WINHI WINLO 000H WINHI WINLO VALUE VALUE >ADR9–2 >ADR9–2 >ADR9–2 <ADR9–2 <ADR9–2 >ADR9–2 <ADR9–2 <ADR9–2 Note that there is no hardware significance to upper and lower designations. The upper comparison value can be selected as less than the lower comparison value, although doing so provides no additional function ...
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... BSY bit to indicate that a conversion has started. When ADEX = 1, the STRT bit can still be used. WCQ – Window Comparator Qualifier. Setting this bit enables the window comparator qualifier function. When WCQ = 1, an interrupt can DS80CH11 BIT 3 BIT 2 BIT 1 BIT 0 WCQ ...
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... DS80CH11 7.8.2 ADCON2 – A/D Control Register 2 ADCON2; SFR ADDR.=0B3H BIT 7 BIT 6 BIT 5 BIT 4 OUTCF MUX2 MUX1 MUX0 Read/Write Access: Unrestricted. Initialization: 00h on any type of reset OUTCF – Output Conversion Format. Selects whether the conversion output most–significant 8–bits or the most–significant 2–bits are presented in the A/D MSB register ...
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... BIT 6 BIT 5 BIT 4 Read/Write Access: Unrestricted. Initialization: 00h on any type of reset Lower limit for the window comparator. These 8–bits are compared against the most significant 8–bits of the previous A/D result. A match of the desired magnitude DS80CH11 BIT 3 BIT 2 BIT 1 BIT 0 ADR3 ADR2 ADR1 ...
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... DS80CH11 8.0 ACTIVITY MONITOR/LED CONTROL 8.1 OVERVIEW During periods of inactivity, varying levels of standby and suspend modes of operation can be initiated by the SEM. Inactivity can be detected by the SEM and then action can be taken to reduce the power consumption of the system and thereby conserve operating power. Activity monitoring is performed by the special logic pro- vided as an alternate function on all lines of Port 7 ...
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... AME2 AME1 cleared to 0, the associated pin is disabled as an inter- rupt source. The associated Port 7 latch bit must be set to 1 when a pin programmed as an activity moni- tor input. BIT 3 BIT 2 BIT 1 AMQ3 AMQ2 AMQ1 DS80CH11 BIT 0 AME0 BIT 0 AMQ0 011200 53/88 ...
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... Part 7 can also be used to control LED’s by turning them on or off. To turn on an LED, the Port 7.X bit must be pro- grammed to a logic 0 allowing current to sink into the DS80CH11. To turn off an LED the Port 7.X but must be programmed to a logic 1, preventing any current flow 011200 54/88 with a valid IOR or IOW signal ...
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... PM1CS line selects the identical power management#1 inter- face port and the PM2CS line selects the power man- DS80CH11 inputs as it does with the 8042 in these systems. The other two ports can be assigned as communication channels to the SEM to support power management and/or other functions ...
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... DS80CH11 SYSTEM DATA TRANSFER SUMMARY Table 9–1 KBCS PM1CS KBCS PM1CS PM2CS PM2CS A0 A0 IOR IOW IOR IOW ...
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... BIT 4 P2ST7 P2ST6 P2ST5 P2ST4 Read/Write Access: Unrestricted. Initialization: XXXXXX00B on any type of reset The operation of the bits in the status registers of both ports are summarized below: DS80CH11 BIT 3 BIT 2 BIT 1 BIT 0 BIT 3 BIT 2 BIT 1 BIT 0 Upon interrupt, the SEM’s firmware should check to see if the incoming byte is a command or data by reading the command/data flag, i ...
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... DS80CH11 KST7–KST4, KST2/P1ST7–4, P1ST2, P2ST7–4, P2ST2–Keyboard / Power Mgr. #1 and #2 Status. KST7–4, KST2, P1ST7–4, P1ST2, P2ST7–4, P2ST2 bits are RAM locations which can be used to communi- cate user–defined status conditions to the host system. They are read/write by the microcontroller and read– ...
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... Upon receipt of the interrupt, the system should read this register to deter- mine on which scan line the key closure occurred. The DS80CH11 capable of generating an interrupt on a low–going tran- sition result, the SEM can initiate a keyboard scan only when a key is pressed instead of doing it periodi- cally ...
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... DS80CH11 11.0 PULSE WIDTH MODULATORS 11.1 FUNCTIONAL OVERVIEW The SEM includes four independent timer channels which can generate pulse–width modulated outputs. All four pulse width modulator channels incorporate a clock selector which generates an independent clock source PWM BLOCK DIAGRAM Figure 11– PRESCALER ...
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... All PWM functions described above are duplicated for all four PWM channels. For each, there is a single value SFR used to access the channel’s Timer value and a PWM value registers, a timer/compare select bit, an out- put enable bit override bit, and a rollover flag bit. DS80CH11 011200 61/88 ...
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... DS80CH11 PWM CHANNEL BLOCK DIAGRAM Figure 11–3 8–BIT TIMER PWM n CLOCK ZERO COMPARATOR BIT S Q PWn DC 11.5 PWM SPECIAL FUNCTION REGISTERS A total of 12 SFR’s are used to control the four PWM channels. The operation of these registers are summa- rized below: 11.5.1 PW01CS / PW23CS – PWM PWM 2, 3 Clock Select Registers PW01CS ...
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... The port pin’s normal psuedo–bi–directional function is switched over to a full 11.5.3 PWnFG – PWM n Frequency Generator Registers PW0FG; SFR ADDR.=0D6H BIT 7 BIT 6 BIT 5 BIT 4 DS80CH11 clock selected by PWnS2–0. When PWnEN = 0, no clock is generated. BIT 3 BIT 2 BIT 1 BIT 0 PW1 ...
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... DS80CH11 PW1FG; SFR ADDR.=0D7H BIT 7 BIT 6 BIT 5 BIT 4 PW2FG; SFR ADDR.=0E6H BIT 7 BIT 6 BIT 5 BIT 4 PW3FG; SFR ADDR.=0E7H BIT 7 BIT 6 BIT 5 BIT 4 Read/Write Access: Unrestricted. Initialization: 00H on any type of reset The PWM channel n operating frequency is derived from the frequency selected by PWnS2–0 (described above) divided by the value of (PWnFG ...
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... The selec- tion of the active function is controlled by the PWnT/C bit. When PWnT then PWM n register accesses the PWM compare value. Writing a new value to PWM n will then select a new duty cycle. The new value will be DS80CH11 BIT 3 BIT 2 BIT 1 BIT 0 loaded from the register into the PWM comparator when the timer reaches the previous PWM compare value ...
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... DS80CH11 12.0 MICROCONTROLLER POWER MANAGEMENT 12.1 POWER–DOWN / POWER–UP OPERATION The SEM incorporates a complete on–chip power moni- toring and control function which performs the following tasks: Power Fail Reset generation Power Fail Warning interrupt 12.1.1 Microcontroller Power Fail Reset The SEM incorporates a precision band–gap voltage reference and internal monitoring circuit to determine if VCC is out of tolerance ...
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... Lastly, soft- ware can disable the crystal amplifier if desired. There are two ways of exiting Slow Clock Mode. Soft- ware can remove the condition by reversing the proce- dure that invoked Slow Clock Mode or hardware can DS80CH11 SLOW CLOCK SLOW CLOCK (64 CLOCKS) (1024 CLOCKS) 28 ...
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... DS80CH11 are minor restrictions on accessing the clock selection bits. The processor must be running clock state to select either 64 (Slow Clock Mode1) or 1024 (Slow Clock Mode2) clocks. This means software cannot go directly from divide–by–64 to divide–by–1024 or vise versa. It must return clock rate first. ...
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... XTUP bit (STATUS. when the crystal is ready for use. Then software should write XT/ begin operating from the crystal. Hardware prevents writing DS80CH11 XT/ before XTUP = 1. The delay between XTOFF = 0 and XTUP = 1 will be 65,536 crystal clocks. Switchback has no effect on the clock source. If soft- ware selects a reduced clock divider and enables the ring, a Switchback will only restore the divider speed ...
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... DS80CH11 Table 12– summary of the bits relating to Slow Clock Mode and its operation. ENTERING / EXITING SLOW CLOCK MODE Figure 12–1 ENTER SLOW CLOCK MODE ALLOW N HARDWARE TO CAUSE A SWITCHBACK ? Y SET SWB=1 CHECK N STATUS=0 ? CHECK AND CLEAR IMPENDING ACTIVITY Y INVOKE SLOW CLOCK MODE ...
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... The ICC of a standard STOP mode is approximately 1 uA (but is specified in the Electrical Specifications). The CPU will exit STOP mode from an external interrupt or a reset condition. Internally generated interrupts (timer, DS80CH11 RESET WRITE ACCESS only when ...
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... DS80CH11 the system under the control of the VRST pin is pre- pared for a power down condition should it occur while STOP with the band–gap disabled is in effect. The control of the band–gap reference is located in the Extended Interrupt Flag register (EXIF; 91h). Setting BGS (EXIF. will keep the band– ...
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... RING OSCILLATION uC ENTERS STOP MODE POWER DIAGRAM ASSUMES THAT THE OPERATION FOLLOWING STOP REQUIRES LESS THAN COMPLETE. DS80CH11 4– OPERATING Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì INTERRUPT; CLOCK uC ENTERS ...
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... DS80CH11 13.0 +5.0V ELECTRICAL SPECIFICATIONS 13.1 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability ...
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... I/O mode. 0.15 0 =5.0 CC 2.4 V 2.4 V –55 A –650 A –10 +10 A –300 +300 A 50 250 =RST=+6.0V. All other pins discon- CC =+6.0V, RST at ground, all other CC =+5.5V, all other pins disconnected. This value CC DS80CH11 10 011200 75/88 ...
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... DS80CH11 7. During transition, a one–shot drives the ports hard for two oscillator clock cycles. This measurement reflects port in transition mode. In addition, this specification applies to any of the Port 6.0–Port 6.3 pins when the associated PWM channel is enabled. 8. Ports 1, 2, and 3 source transition current when being pulled down externally. Current reaches its maximum at approximately 2V. 9. 0.45< ...
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... CLCL –0.5t –5 ns CLCL – CLCL CLCL MOVX CYCLES 2 machine cycles 3 machine cycles (default) 4 machine cycles 5 machine cycles 6 machine cycles 7 machine cycles 8 machine cycles 9 machine cycles DS80CH11 10 MCS t >0 MCS t =0 MCS t >0 MCS t =0 MCS t >0 MCS t =0 MCS t > ...
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... DS80CH11 13.3.3 EXTERNAL CLOCK CHARACTERISTICS PARAMETER SYMBOL Clock High Time t CHCX Clock Low Time t CLCX Clock Rise Time t CLCH Clock Fall Time t CHCL 13.3.4 SERIAL PORT MODE 0 TIMING CHARACTERISTICS PARAMETER SYMBOL Serial Port Clock Cycle Time t XLXL SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle ...
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... LLIV ALE t AVLL t PLIV PSEN t LLPL t PLAZ t LLAX1 ADDRESS PORT 0 A0–A7 t AVIV1 t AVIV2 PORT 2 ADDRESS A8–A15 OUT ( =5.0 CC MIN TYP MAX UNITS 1.8 ms 65536 t CLCL t PLPH t PXIZ t PXIX INSTRUCTION ADDRESS IN A0–A7 ADDRESS A8–A15 OUT DS80CH11 10%) NOTES 1 2 011200 79/88 ...
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... DS80CH11 EXTERNAL DATA MEMORY READ CYCLE Figure 13–2 t LHLL2 ALE t LLWL t LLAX1 PSEN RD t AVLL t RLAZ t AVWL1 INSTRUCTION ADDRESS PORT 0 IN A0–A7 PORT 2 t AVWL2 EXTERNAL DATA MEMORY WRITE CYCLE Figure 13–3 ALE t PSEN t LLAX2 WR t AVLL INSTRUCTION ADDRESS PORT 0 IN A0– ...
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... A8–A15 Second Third Fourth Machine Machine Cycle Cycle Cycle MOVX Instruction D0–D7 MOVX Data A8–A15 STRETCH VALUE=2 DS80CH11 Next Instruction A0–A7 D0–D7 A8–A15 Next Instruction Machine Cycle A0–A7 D0–D7 A8–A15 011200 81/88 ...
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... DS80CH11 EXTERNAL CLOCK DRIVE Figure 13–6 XTAL1 t CHCL SERIAL PORT MODE 0 TIMING Figure 13–7 SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH SPEED OPERATION SM2=1=>TXD CLOCK=XTAL/4 ALE PSEN t QVXH t WRITE TO SBUF XHQX RXD DATA OUT TXD CLOCK t XLXL TI WRITE TO SCON TO CLEAR RI RXD ...
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... Applies to system interface outputs which are powered via the HVCC supply; KBOBF, SMI1, SMI2, and SD7 – SD0. t CSU t POR ( =5.0 CC MIN TYP MAX UNITS 4.5 5.0 5.5 V 600 A 2 –0.3 0.6 V – 2.4 V 0.4 V DS80CH11 10%) NOTES 011200 83/88 ...
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... DS80CH11 13.5 HOST I/F AC TIMING CHARACTERISTICS PARAMETER SYMBOL Cycle Time t CYC Input Rise and Fall Time Chip Select, A0 Setup t CIO Time Before IOR IOW , IOR, IOW Low Time t IOL IOR, IOW High Time t IOH Delay From IOR to Data t IRD Data Hold Time After IOR ...
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... BUS TIMING FOR READ CYCLE FROM HOST I/F REGISTERS Figure 13–10 KBCS, PM1CS PM2CS A0 t CIO IOR t IRD SD7–SD0 (OUTPUT) OUTPUT LOAD Figure 13–11 DEVICE UNDER TEST 1K DS80CH11 t CYC t t IOL IOH t IOCH t IRDH t IRDZ V = +5. 011200 85/88 ...
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... DS80CH11 13.6 2–WIRE AC TIMING CHARACTERISTICS PARAMETER SYMBOL START Condition Hold Time t STAH SCLx Low Time t SCL SCLx High Time t SCH SCLx, SDAx Rise Time t SR SCLx, SDAx Fall Time t SF Data Setup Time t 2DS Data Hold Time t 2DH Repeated START Setup Time ...
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... VCC +0.2 V –0.2V GND–0.2 GND +0.2 V GND–0.2 VCC +0.2 V AGND AVCC+0.2 V –0.2 =AVCC =5.0 10% AGND = GND = 0V) CC MIN TYP MAX UNITS 1.0 mA 100 A VRL VRH Bits + 0.3 + 0.75 LSB + 0.2 + 1.0 LSB + 0.25 + 1.0 LSB + 0. DS80CH11 NOTES NOTES 011200 87/88 ...
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... DS80CH11 128–PIN TQFP PKG 128–PIN DIM MIN MAX A – 1.60 A1 0.05 – A2 1.35 1.45 B 0.17 0.27 C 0.09 0.20 D 21.80 22.20 D1 20.00 BSC E 15.80 16.20 E1 14.00 BSC e 0.50 BSC L 0.45 0.75 56–G4011–000 011200 88/88 ...