DS5001FP Maxim Integrated Products, DS5001FP Datasheet
DS5001FP
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DS5001FP Summary of contents
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... P0.0/AD0 11 VCC0 12 VCC 13 MSEL 14 P1.0 15 BA14 16 P1.1 17 BA12 18 P1.2 19 BA7 20 P1.3 21 PE3 22 PE4 23 BA6 MQFP MQFP DS5001FP 64 P2.6/A14 63 CE3 62 CE4 61 BD3 60 P2.5/A13 59 BD2 58 P2.4/A12 57 BD1 56 P2.3/A11 55 BD0 54 VLI 53 BA15 52 GND 51 P2.2/A10 50 P2.1/ ...
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... ROM are automatically write-protected by the microprocessor. Combining program and data storage in one device saves board space and cost. The DS5001FP offers several bank switches for access to even more memory. In addition to the primary data area of 64kB, a peripheral selector creates a second 64kB data space with four accompanying chip enables ...
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... Figure 1. BLOCK DIAGRAM DS5001FP ...
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... At this PSEN time, is pulled down externally. This should only be done once the DS5001FP PSEN is already in a reset state. The device that pulls down should be open drain since it must not interfere with under normal operation. ...
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... CE3 . LI is lithium-backed and remains at a logic high to battery-backed functions only. PE1 is lithium-backed and remains at a logic PE2 to battery-backed functions only. PE2 is not lithium-backed and can be connected PE3 is not lithium-backed and can be connected PE4 DS5001FP through . LI < < < ...
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... SRAM, a lithium cell, and a real-time clock. This is packaged in a 72-pin SIMM module. MEMORY ORGANIZATION Figure 2 illustrates the memory map accessed by the DS5001FP. The entire 64k of program and 64k of data are potentially available to the byte-wide bus. This preserves the I/O ports for application use. The user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program range and data range ...
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... Figure 2. MEMORY MAP IN NONPARTITIONABLE MODE ( DS5001FP ...
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... Figure 3. MEMORY MAP IN PARTITIONABLE MODE ( NOTE: PARTITIONABLE MODE IS NOT SUPPORTED WHEN MSEL PIN = 0 (128kB MODE DS5001FP ...
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... Figure 4. MEMORY MAP WITH PES = DS5001FP ...
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... RAM chip Figure 6 shows a similar system with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The bidirectional byte-wide data bus connects the data I/O lines of the SRAM. Figure 5. CONNECTION TO 128k x 8 SRAM DS5001FP ...
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... Low power SRAMs should be used for this reason. When using the DS5001FP, the user must select the appropriate battery to match the RAM data retention current and the desired backup lifetime. Note that the lithium cell is only loaded when V more information on this topic ...
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... SYMBOL MIN V -0 2.0 IH1 V 3.5 IH2 V OL1 ) , V OL2 V 2.4 OH1 , PSEN V 2.4 OH2 , and TYP MAX UNITS + 0.15 0.45 V 0.15 0.45 V 4.8 V 4.8 V -50 µA -500 µA -600 µA DS5001FP + 0.5V 0V. In NOTES ...
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... V CC CCMIN V 2 IDLE I IDLE I STOP CCO1 -0. CCO2 -0. CCO2 -0.9 I CCO1 4.0 3.85 4 DS5001FP MAX UNITS NOTES +10 µA 150 kW 180 µ ...
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... CLK CLK 9t - 165 CLK 9t - 105 CLK CLK CLK 4t - 130 CLK CLK 7t - 150 CLK CLK CLK CLK CLK DS5001FP UNITS MHz ...
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... EXPANDED PROGRAM-MEMORY READ CYCLE EXPANDED DATA-MEMORY READ CYCLE DS5001FP ...
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... EXPANDED DATA-MEMORY WRITE CYCLE DS5001FP ...
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... PARAMETER 28 External Clock-High Time 29 External Clock-Low Time 30 External Clock-Rise Time 31 External Clock-Fall Time EXTERNAL CLOCK TIMING SYMBOL at 12MHz t CLKHPW at 16MHz at 12MHz t CLKLPW at 16MHz at 12MHz t CLKR at 16MHz at 12MHz t CLKF at 16MHz DS5001FP MIN MAX UNITS ...
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... AC CHARACTERISTICS: POWER CYCLE TIME ( ±10 0°C to +70°C PARAMETER 32 Slew Rate from V CCMIN 33 Crystal Startup Time 34 Power-On Reset Delay POWER CYCLE TIMING SYMBOL CSU t POR DS5001FP MIN MAX UNITS 130 µs (Note 9) 21,504 t CLK ...
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... Output-Data Hold After Rising-Clock Edge 38 Clock-Rising Edge to Input-Data Valid 39 Input-Data Hold After Rising-Clock Edge SERIAL PORT TIMING—MODE 0 SYMBOL MIN t 12t SPCLK CLK t 10t - 133 DOCH CLK 117 CHDO CLK t CHDV t 0 CHDIV DS5001FP MAX UNITS µ 10t - 133 ns CLK ns ...
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... CE1HPA CLK OVCE1H CLK t 0 CE1HOV CEHDA CLK CELDA CLK DACEH CLK t 0 CEHDV AVRWL CLK t 20 RWLDV CEHDV CLK t 0 RWHDV RWLPW CLK DS5001FP UNITS ...
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... Data Setup Data Hold After WR SYMBOL MIN 160 RDZ SYMBOL MIN 160 WW t 130 DS5001FP MAX UNITS 130 ns 130 MAX UNITS ...
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... DRQ Cleared CHARACTERISTICS ±10 0°C to +70°C PARAMETER 69 Low to Active PROG 70 High to Inactive PROG SYMBOL t ACC t CAC t ACD t CRQ PROG SYMBOL t PRA t PRI DS5001FP MIN MAX UNITS 130 ns 110 ns MIN MAX UNITS 48 CLKS 48 CLKS ...
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... RPC TIMING MODE DS5001FP ...
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... This parameter applies to industrial temperature operation. 11) pin operation is specified with input when and < and a maximum load of 10µ ³ 3.0V. BAT MSEL = RST = MSEL = XTAL2 not CC = +25° normal operation. CCO is disconnected. CCO . CCO DS5001FP , CLKR , CLKR ...
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... PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) 80-PIN MQFP MM DIM MIN MAX A - 3. 2.55 2.87 B 0.30 0.50 C 0.13 0.23 D 23.70 24.10 D1 19.90 20.10 E 17.70 18.10 E1 13.90 14.10 e 0.80 BSC L 0.65 0.95 56-G4005-001 DS5001FP ...
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... MQFP DS5001FP ...
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... The following represent the key differences between the 051099 and 052499 version of the DS5001FP data sheet. Please review this summary carefully. 1) Minor markups and ready for approval. The following represent the key differences between the 052499 and 052302 version of the DS5001FP data sheet. Please review this summary carefully. 1) Added information relating to 44-pin package. ...