K4Y50164UC-JCB3 Samsung, K4Y50164UC-JCB3 Datasheet
K4Y50164UC-JCB3
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K4Y50164UC-JCB3 Summary of contents
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... ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply ...
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K4Y5016(/08/04/02)4UC Change History Version 0.1 (May 2005) - Preliminary - First Copy TM - Based on the Rambus XDR DRAMDatasheet Version 0.85 Version 0.2 (June 2005) - Preliminary TM - Based on the Rambus XDR DRAM Datasheet Version 0.88 Version ...
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K4Y5016(/08/04/02)4UC Overview The Rambus XDR DRAM device is a general-purpose high-performance memory device suitable for use in a broad range of applications, including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The ...
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... See “Timing Parameters” on page 60 For bin =4, and for bin B, t RC-R RR-D RC-R RR-D Page 2 Preliminary XDR TM b c,d Part Number Bin A K4Y50164UC-JCA2 B K4Y50164UC-JCB3 C K4Y50164UC-JCC4 A K4Y50084UC-JCA2 B K4Y50084UC-JCB3 C K4Y50084UC-JCC4 A K4Y50044UC-JCA2 B K4Y50044UC-JCB3 C K4Y50044UC-JCC4 A K4Y50024UC-JCA2 B K4Y50024UC-JCB3 C K4Y50024UC-JCC4 /t =5 for bin C, t RC-R RR-D RC-R Version 0 ...
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K4Y5016(/08/04/02)4UC General Description The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins. The ...
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K4Y5016(/08/04/02)4UC Pinouts and Definitions The following table shows the pin assignment of the center-bonded fanout XDR DRAM Package. The mechanical dimensions of this package are shown on page 72. Note - Pin # the A1 postion. Table 1: ...
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K4Y5016(/08/04/02)4UC Pin Description Table2 summarizes the pin functionality of the XDR DRAM device. The first group of pins provide the necessary supply voltages. These include V and GND for the core and interface logic signals. The next group ...
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K4Y5016(/08/04/02)4UC Block Diagram A block diagram of the XDR DRAM device is shown in Figure2. It shows all interface pins and major internal blocks. The CFM and CFMN clock signals are received and used by the clock generation logic to ...
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K4Y5016(/08/04/02)4UC Figure 2 : 512Mb (8x4Mx16) XDR DRAM Block Diagram RQ11..0 VREF 12 1 2/t CYCLE 1:2 Demux 12 12 reg 12 12 Decode COL logic PRE logic ACT logic 7 6 RD,WR PRE delay ACT delay ...
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K4Y5016(/08/04/02)4UC Request Packets A request packet carries address and control information to the memory device. This section contains tables and diagrams for packet formats, field encodings and packet interactions. Request Packet Formats There are five types of request packets: 1. ...
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K4Y5016(/08/04/02)4UC CFM CFM CFMN CFMN t RQ11..0 CYCLE ACT RQ11..0 a0 DQ15..0 DQN15..0 ROWA Packet t CYCLE CFM CFMN OP DEL RQ11 RQ10 ...
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K4Y5016(/08/04/02)4UC Request Field Encoding Operation code fields are encoded within different packet types to specify commands. Table4 through Table7 provides packet type and encoding summaries. Table4 shows the OP field encoding for five packet types. The COLM and ROWA packets ...
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K4Y5016(/08/04/02)4UC The REFH/M/L registers are also refreshed to as the REFr registers. Note that only the bits that are needed for specifying the refresh row(11 bits in all) are implemented in the REFr registers - the rest are reserved. Note ...
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K4Y5016(/08/04/02)4UC Request Field Interactions A summary of request packet interaction is Table8. Each case is limited to request packets with commands that perform memory operations(including refresh commands). This includes all commands in ROWA, ROWP, COL, and COLM packets. The commands ...
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K4Y5016(/08/04/02)4UC The first request is shown along the vertical axis on the left of the table. The second request is shown along the horizontal axis at the top of the table. Each request includes a bank specification “Ba” and “Bb”. ...
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K4Y5016(/08/04/02)4UC Figure 4 : ACT-, RD-, WR-, PRE-to-ACT Packet Interactions CFM CFM CFMN CFMN RQ11..0 ACT ACT RQ11.. DQ15..0 DQ15..0 DQN15..0 DQN15..0 AAd Case (activate-activate-different bank) ...
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K4Y5016(/08/04/02)4UC Figure 5 : ACT-, RD-, WR-, PRE-to-RD Packet Interactions CFM CFMN CFM CFMN RQ11..0 ACT RD RQ11.. DQ15..0 No limit DQN15..0 DQ15..0 DQN15..0 ARd Case (activate-read different ...
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K4Y5016(/08/04/02)4UC Figure 6 : ACT-, RD-, WR-, PRE-to-WR Packet Interactions CFM CFM CFMN CFMN ACT WR RQ11..0 RQ11.. limit DQ15..0 DQ15..0 DQN15..0 DQN15..0 AWd Case (activate-write different ...
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K4Y5016(/08/04/02)4UC Figure 7 : ACT-, RD-, WR-, PRE-to-PRE Packet Interactions CFM CFM CFMN CFMN ACT PRE RQ11..0 RQ11.. limit DQ15..0 DQ15..0 DQN15..0 DQN15..0 APd Case (activate-precharge different ...
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K4Y5016(/08/04/02)4UC Dynamic Request Scheduling Delay fields are present in the ROWA, COL, and ROWP packet. They permit the associated command to optionally wait for a time of one (or more) t before taking effect. This allows a memory controller more ...
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K4Y5016(/08/04/02)4UC ACT w/DEL equivalent 0 to ACT w/DEL CFM CFMN RQ11..0 ACT ACT DEL1 DEL0 DQ15..0 DQN15..0 Note DEL value is specified by DELA ...
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K4Y5016(/08/04/02)4UC Memory Operations Write Transactions Figure9 shows four examples of memory write transactions. A transaction is one or more request packets (and the associated data packets) needed to perform a memory access. The state of the memory core and the ...
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K4Y5016(/08/04/02)4UC CFM CFMN WR WR RQ11.. DQ15..0 D(a1) DQN15..0 t CWD CFM CFMN PRE a3 RQ11..0 ...
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K4Y5016(/08/04/02)4UC Read Transactions Figure10 shows four examples of memory read transactions. A transaction is one or more request packets (and the associated data packets) needed to perform a memory access. The state of the memory core and the address of ...
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K4Y5016(/08/04/02)4UC CFM CFMN RQ11.. DQ15..0 t DQN15..0 CAC Transaction CFM CFMN PRE ...
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K4Y5016(/08/04/02)4UC Interleaved Transactions Figure11 shows two examples of interleaved transactions. Interleaved transactions are overlapped with one another; a transac- tion is started before an earlier one is completed. The timing diagram at the top of the figure shows interleaved write ...
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K4Y5016(/08/04/02)4UC CFM CFMN RQ11..0 ACT ACT (ACT RQ11.. (COL DQ15..0 RCD-W CC D(a1) DQN15..0 RQ11..0 t CWD (PRE) RQ11..0 ACT ...
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K4Y5016(/08/04/02)4UC Read/Write Interaction The previous section described overlapped read transactions and overlapped write transactions in isolation. This section will describe the interaction of read and write transactions and the spacing required to avoid channel and core resource conflicts. Figure12 shows ...
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K4Y5016(/08/04/02)4UC Propagation Delay Figure 13 shows two timing diagrams that display the system-level timing relationships between the memory component and the memory controller. The timing diagram at the top of the figure shows the case of a write-read-write command and ...
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K4Y5016(/08/04/02)4UC in a system with minimum propagation delays RW-BUB XDRDRAM MIN RW-BUB XIO and since equal to t RW-BUB XIO RW-BUB ( ...
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K4Y5016(/08/04/02)4UC Register Operations Serial Transactions The serial interface consists of five pins. This includes RST, SCK, CMD, SDI and SDO. SDO uses CMOS signaling levels. The other four pins use RSL signaling levels. RST, CMD, SDI and SDO use a ...
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K4Y5016(/08/04/02)4UC SCK t CYC,SCK RST Start SCMD CMD ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ SDI (input) SDO (output) Figure 15 : Serial Read Transaction — Selected DRAM S ...
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K4Y5016(/08/04/02)4UC Register Summary Figure17 through Figure42 show the control register in the memory component. The control registers are responsible for config- uring the component’s operating mode, for managing power state transactions, for managing refresh, and for managing calibra- tion operations. ...
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K4Y5016(/08/04/02)4UC SLE SP[1:0] rsrv rsrv SLE - Serial Load enable field WDSL-path-to-memory disabled WDSL-path-to-memory enabled 2 SP[1:0] - Sub page activation field Full Page Activation ...
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K4Y5016(/08/04/02)4UC RQL[7: MBR[1:0] reserved reserved reserved Figure Scan Low (RQL) Register Scan Low ...
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K4Y5016(/08/04/02)4UC R[7: reserved CCVALUE0[5:0] reserved CCVALUE1[5:0] reserved Figure 30 : Impedance Calibration 0 (ZC0) Register ...
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K4Y5016(/08/04/02)4UC FZCVALUE0[5:0] reserved reserved FZCVALUE1[5:0] reserved reserved VENDOR[3:0] reserved BB[1:0] RB[2: WTL WTE reserved 7 ...
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K4Y5016(/08/04/02)4UC reserved reserved reserved reserved CWD[3:0] Figure 43 : Partner-Definable (PART0-PARTF) Registers ...
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K4Y5016(/08/04/02)4UC Maintenance Operations Refresh Transactions Figure44 contains two timing diagrams showing examples of refresh transactions. The top timing diagram shows a single refresh operation. Bank Ba is assumed to be closed (in a precharged state) when a REFA command is ...
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K4Y5016(/08/04/02)4UC CFM CFMN t REFA RQ11..0 a0 DQ15..0 DQN15..0 Transaction a: REF Transaction b: REF Transaction c: REF Bc/Rc = Ba/ ...
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K4Y5016(/08/04/02)4UC Calibration Transactions Figure45 shows the calibration transaction diagrams for the XDR DRAM device. There is one calibration operation supported: calibration of the output current level I The output current calibration sequence is shown in the upper diagram. It begins ...
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K4Y5016(/08/04/02)4UC Power State Management Figure46 shows power state transition diagrams for the XDR DRAM device. There are two power states in the XDR DRAM: Powerdown and Active. Powerdown state used in applications in which it is necessary ...
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K4Y5016(/08/04/02)4UC CFM CFMN t CYCLE CMD RQ11..0 a DQ15..0 t CMD-PDN DQN15..0 Transaction a: Last precharge command Transaction b: PDN SCK RST Start 2’h0,SID[5:0] SCMD CMD ‘1’ ‘1’ ‘0’ ...
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K4Y5016(/08/04/02)4UC Initialization Figure47 shows the topology of the serial interface signals of a XDR DRAM system. The three signals RST, CMD, and SCK are transmitted by the controller and are received by each XDR DRAM device along the bus. The ...
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K4Y5016(/08/04/02)4UC The XDR DRAM [1] device will see SDI sampled zero on edge S zero around the subsequent edge (S The XDR DRAM [2] device will see SDI sampled zero on edge S to zero around the subsequent edge (S ...
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K4Y5016(/08/04/02)4UC Table 11 : XDR DRAM WDSL-to-Core/DQ/SC Map (First Generation x16/x8/x4/x2 XDR DRAM 16) WDSL Core Word Load DQ Pins Used Order Core Word x16 WD[n][15:0] LOGICAL VIEW OF XDR DRAM DQ0 DQ0 DQ0 DQ0 ...
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K4Y5016(/08/04/02)4UC DQ Serialization Order CFM/PCLK Cycle Symbol (Bit) Time t0 t1 Bit Transmitted pins WDSL Byte/Bit Transfer Order Core Word WDSL Byte Order SWD Field of Serial 7 6 Packet Bit Transmitted on CMD D15 D11 ...
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K4Y5016(/08/04/02)4UC Sub-Row (Sub-Page) Sensing The SP[1:0] field of the CFG register controls what fraction of a row is sensed during a ROWA activate operation. This permits the controller to reduce the amount of power consumed by normal transactions if a ...
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K4Y5016(/08/04/02)4UC Special Feature Description Dynamic Width Control This XDR DRAM device includes a feature called dynamic width control. This permits the device to be configured so that read and write data can be accessed through differing widths of DQ pins. ...
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K4Y5016(/08/04/02)4UC The block diagram in Figure 50 indicates that the Dynamic Width logic is positioned after the serial-to-parallel conversion (demux block) in the data receiver block and before the parallel-to-serial conversion (mux block) in the data transmitter block (see also ...
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K4Y5016(/08/04/02)4UC Write Masking Figure 52 shows the logic used by the XDR DRAM device when a write-masked command (WRM) is specified in a COLM packet. This masking logic permits individual byte of a write data packet to be written or ...
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K4Y5016(/08/04/02)4UC Note that other systems might use a data transfer size that is different than the 64 bytes per t in the example in Figure 52. Figure 53 shows the timing of two successive WRM commands in COLM packets. The ...
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K4Y5016(/08/04/02)4UC Multiple Bank sets and the ERAW Feature Figure 56 shows a block diagram of a XDR DRAM in which the banks are divided into two sets (called the even bank set and the odd bank set) according to the ...
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K4Y5016(/08/04/02)4UC Figure 56 : XDR DRAM Block Diagram with Bank Sets Odd Bank Array Bank 16x16*2 *2 ACT ACT ROW ROW PRE Bank 1 PRE 3 Bank (2 -1) 6 16x16*2 16x16*2 ... Sense Amp Array 6 ...
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K4Y5016(/08/04/02)4UC Simultaneous Activation When the XDR DRAM supports multiple bank sets as in Figure 56, another feature may be supported, in addition to ERAW. This feature is simultaneous activation, and the timing of several cases is shown in Figure 57. ...
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K4Y5016(/08/04/02)4UC Simultaneous Precharge When the XDR DRAM supports multiple bank sets as in Figure56, another feature may be supported, in addition to ERAW. This feature is simultaneous precharge, and the timing of several cases is shown in Figure58. The t ...
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K4Y5016(/08/04/02)4UC Operating Conditions Electrical Conditions Table13 summarizes all electrical conditions (temperature and voltage conditions) that may be applied to the memory compo- nent. The first section of parameters is concerned with absolute voltage, storage and operating temperatures, and the power ...
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K4Y5016(/08/04/02)4UC Timing Conditions Table14 summarizes all timing conditions that may be applied to the memory component. The first section of parameters is concerned with parameters for the clock signals. The second section of parameters is concerned with parameters for the ...
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K4Y5016(/08/04/02)4UC Operating Characteristics Electrical Characteristics Table15 summarizes all electrical parameters (temperature, current and voltage) that characterize this memory component. The only exception is the supply current values(I section. The first section of parameters is concerned with the thermal characteristics of ...
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K4Y5016(/08/04/02)4UC Supply Current Profile In this section, Table16 summarizes the supply current (I shown under different operating conditions. Power State and Steady State Symbol Transaction Rates I Device in PDN, self-refresh enabled. DD,PDN Device in STBY. This is for a ...
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K4Y5016(/08/04/02)4UC Timing Characteristics Table 17 summarizes all timing parameters that characterize this memory component. The only exceptions are the core timing parameters that are speed-bin dependent. Refer to the Timing Parameters section for more information. The first section of parameters ...
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K4Y5016(/08/04/02)4UC Timing Parameters Table18 summarizes the timing parameters that characterize the core logic of this memory component.. These timing parame- ters will vary as a function of the component’s speed bin. The four sections deal with the timing intervals between ...
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K4Y5016(/08/04/02)4UC Receive/Transmit Timing Clocking Figure59 shows a timing diagram for the CFM/CFMN clock pins of the memory component. This diagram represents a magni- fied view of these pins. This diagram shows only one clock cycle. CFM and CFMN are differential ...
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K4Y5016(/08/04/02)4UC RSL RQ Receive Timing Figure60 shows a timing diagram for the RQ11...0 request pins of the memory component. This diagram represents a magnified view of the pins and only a few clock cycle (CFM and CFMN are the clock ...
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K4Y5016(/08/04/02)4UC DRSL DQ Receive Timing Figure61 shows a timing diagram for receiving write data on the DQ/DQN data pins of the memory component. This diagram represents a magnified view of the pins and only a few clock cycles are shown ...
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K4Y5016(/08/04/02)4UC t CYCLE CFM CFMN t DOFF,MAX t DOFF,MIN t DOFF,DQ0 DQ0 0 DQN0 t DOFF,DQi DQi 0 DQNi t DOFF,DQ15 DQ15 0 1 DQN15 Figure 61 : DRSL DQ Receive Waveforms i = {0,1,2,3,4,5,...15} [(j)/8]•t CYCLE ...
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K4Y5016(/08/04/02)4UC DRSL DQ Transmit Timing Figure62 shows a timing diagram for transmitting read data on the DQ15...0/DQN15...0 data pins of the memory component. This diagram represents a magnified view of these pins and only a few clock cycles are shown ...
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K4Y5016(/08/04/02)4UC t CYCLE CFM CFMN t QOFF,MAX t QOFF,MIN [(j+0.5)/8]•t [(j-0.5)/8]•t DQ0 t QOFF,DQ0 0 DQN0 [(j+0.5)/8]•t [(j-0.5)/8]•t DQi t QOFF,DQi 0 1 DQni [(j+0.5)/8]•t [(j-0.5)/8]•t DQ7 t QOFF,DQ7 0 1 DQN7 Figure 62 : RSL DQ Transmit Waveforms i ...
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K4Y5016(/08/04/02)4UC Serial Interface Receive Timing Figure63 shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified view of the pins only a few clock cycles. The serial interface pins carry low-true signals: ...
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K4Y5016(/08/04/02)4UC Serial Interface Transmit Timing Figure64 shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified view of the pins and only a few clock cycles are shown. The serial interface pins ...
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K4Y5016(/08/04/02)4UC Package Description Package Parasitic Summary Table19 summarizes inductance, capacitance, and resistance values associated with each pin group for the memory compo- nent. Most of the parameters have maximum values only, however some have both maximum and minimum values. The ...
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K4Y5016(/08/04/02)4UC Symbol Parameter and Other Conditions L V pin - effective input inductance per four bits VTERM TERM L CFM/CFMN pins - effective input capaciance I ,CFM C CFM/CFMN pins - effective input capaciance I ,CFM R CFM/CFMN pins - ...
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K4Y5016(/08/04/02)4UC Figure 65 : Equivalent Circuits for Package Parasitic Pad Pad Pad C I,DQ R I,DQ Pad Pad C I,CFM R I,CFM Pad L I,RQ C I, PKG, PKG,DQ C I,DQ R I,DQ Z ...
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K4Y5016(/08/04/02)4UC Package Mechanical Drawing Figure66 illustrates the XDR DRAM device package and Table20 summarizes the mechanical parameters for that package. Table 20 : XDR DRAM Package Mechanical Parameters Symbol Parameter e1 Ball pitch (x-axis) e2 Ball pitch (y-axis) A Package ...
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K4Y5016(/08/04/02)4UC Table of Contents Overview Features Key Timing Parameters/Part Numbers General Description Pinouts and Definitions Pin Description Block Diagram Request Packets Request Packet Formats Request Field Encoding Request Field Interaction Request Interaction Cases Dynamic Request Scheduling Memory Operations Write Transactions ...
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... All rights reserved. Rambus and Rambus logo are trademarks or registered trademarks of Rambus Inc. XDR is a trademark of Rambus Inc. in the United States and other countries. This document contains advanced information that is subject to change by Samsung Electronics without notice Document Version 0.3ver. Samsung Electronics Co. Ltd. ...