S5H1420X01 Samsung, S5H1420X01 Datasheet
S5H1420X01
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S5H1420X01 Summary of contents
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... Decoder for DVB-S/DSS] DATA SHEET Samsung Electronics Co, Ltd. Note: This documentation is preliminary and is subject to change. Samsung Electronics Co, Ltd. reserves the right to do any kind of modification in this data sheet regarding hardware or software implementations without notice. Samsung Electronics Co, Ltd. Proprietary Information S5H1420 10 Jan ...
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... PACKAGE DIMENSION…………………………………………………………………………………….30 8. Data Sheet Update History…………………………………………………………………………...…….31 Samsung Electronics Co, Ltd. Proprietary Information S5H1420 ...
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... Single power using diode for 2.5V v Compact size package: 64LQFP-1010 1.3 Applications DVB-S Receiver and STB Digital satellite TV PCI satellite Card 1.4 Ordering information Type Number 1. S5H1420X01 64 LQFP-1010 Samsung Electronics Co, Ltd. Proprietary Information 50000 ppm. Package Plastic Low Profile Quad Flat Package; 64 leads (lead length 1.0mm) Body 10x10x1.0 mm ...
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... AVBB_ADC 52 VREF_L 53 VREF_H 54 CML 55 AVSS_ADC 56 AVDD_ADC 57 VSS25 58 VDD25 59 AGC 60 DiSEqC 61 BYTE_CLK 62 VSEL 63 LNB_EN Samsung Electronics Co, Ltd. Proprietary Information Digital Filter Timing Viterbi Phase Decoder Recovery Lock Indicator Clock DiSEqC Generator I 64-LQFP ...
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... AVBB_ADC PLL AVDD_PLL AVSS_PLL AVBB_PLL AVDD_PLL AVSS_PLL IO VSS33 VDD33 Logic VSS25 VDD25 Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS Pin Number Description 1 LNB Over Load Flag 2 H/W Reset (Active Low) 3 Error indicator output 4 Synchronization output 5 Valid data period ...
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... In contrast, f clk (1+ ) fsym < 2 Where is roll-off factor: 0.35 for DVB-S, 0.2 for DSS. Thus Timing NCO frequency word register setting is: NCO frequency word = Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS clk for =1. for = sym 2 f clk ...
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... Also, we can choose Loop Bandwidth (BL), as follows Where is the reference level of the = 2 3.3.2 Carrier lock detector Samsung Electronics Co, Ltd. Proprietary Information is integral gain and is timing factor. t Bandwidth (BL), as follows and . /2 (± f /2). clk sampling is integral gain and is phase factor ...
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... Euclidian distance between the received I and Q and the theoretical symbol value. The puncture rate and phase are estimated on the error rate basis. Several rates are allowed and may be enabled/disabled through register programming: Samsung Electronics Co, Ltd. Proprietary Information S5H1420 DBS Channel Decoder for DVB-S/DSS = 171 octets and G ...
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... Energy dispersal descrambler and output energy dispersal descrambler generator The polynomial is initialized every eight blocks with the sequence 100101010000000. The sync words are unscrambled and the scrambler is reset every 8 packets. Samsung Electronics Co, Ltd. Proprietary Information 1=0 S5H1420 DBS Channel Decoder for DVB-S/DSS - ...
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... The first bit detected in a valid packet may be decoded found on the appropriate edge of BYTE_CLOCK, where SYNC = 1, ERROR = 0, VALID = 1. The following bits only require the assertion of VALID (while VALID = 1,). Outputs remain at low level in serial mode. Samsung Electronics Co, Ltd. Proprietary Information S5H1420 DBS Channel Decoder for DVB-S/DSS ...
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... MPEG_DOUT=1 D0 MPEG_DOUT=0 MPEG_ERR=1 ERROR MPEG_ERR=0 Table 0 Bit1 of 0x39 SER_PAR Parallel 0 1 Serial Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS No Error Uncorrectible Packet Data Parity 1/fclk DATA First bit of the packet Useful Data 1 packet Bit4 of 0x02 MPEG Data ...
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... MCLK 6 F /192 MCLK 7 F /256 MCLK Example1) System Clock Frequency = 88MHZ, Symbol Rate : 44MSps Code Rate 1/2 2/3 3/4 5/6 6/7 7/8 Samsung Electronics Co, Ltd. Proprietary Information 60MHz Symbol Rate Symbol Rate < 25 >= 25 88MHz 80MHz 1 2 [2:0]) MPEG_CLK_INTL MPEG Clock Range Divide (Serial Tmp 2 ...
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... Register setting can program the desired frequency out input frequency, m=M+8, p=P+2, s=2 Register 03, P: Register 04 [5:0], S: Register 04[7:6] Samsung Electronics Co, Ltd. Proprietary Information % B UB" " " " " " " " ...
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... At the beginning, the register set is empty (DiS_RDY =0). This is the idle state soon as set the DiS_RDY =1, the transfer will begin. v After the last transmitted byte, the interface will go into the idle state. Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS 2 ...
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... Note: 1 Byte to transfer in DiSEqC mode Mode LNB_CON (1:0) =10, the DiSEqC pin return to high 2 mode once the transmission is completed. Samsung Electronics Co, Ltd. Proprietary Information 11 Periods 11 Periods Register set Empty DATA=00 Unmodulated tone burst DATA=FFor00 Note 1 xx S5H1420 DBS Channel Decoder for DVB-S/DSS ...
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... DiS06 0X40 DiS07 0X41 DiS08 0X42 DiS09 0X43 DiS10 0X44 DiS11 0x45 Rf01 0X46 Err01 0x47 Err02 0x48 Err03 0x49 Err04 Samsung Electronics Co, Ltd. Proprietary Information bit6 bit5 bit4 bit3 S5H1420_ID 0 SOFT_RST 0 0 SER_SEL DC_EN DUMP_ACC 0 ...
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... Width Property Description PLL01 0x03 M [7:0] (0x50) P [5:0] PLL02 0x04 (0x40) S [7:6] Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS R Revision ID R/W Set to “0” System soft reset mode (active high) R/W [1] Enable [0] Disable R/W Set to “0” R/W Set to “0” DSS/DVB mode selection ...
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... INV_PULSE [7] Pre01 0x07 (0x30) [6] [5] PRE_TH [4:0] [7:6] Post01 0x08 (0x10) POST_TH [5:0] Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS R/W [1] PLL Kicker enable [0] Disable R/W Set to “0” R/W Set to “1” DC offset remove R/W [1] Enable [0] Disable R/W Set to “1” R/W Set to “1” ...
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... Tnco03 0x13 TNCO3 [15:08] [7:0] (0x00) Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS Write TNCO center frequency R/W [0 and then 1] The write operation enabled, when user set WT_TNCO “0” and then “1” Write PNCO center frequency ...
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... Monitor12 0x1F QPSK_OUT [6:1] (0x00) DC_FREEZE [0] (0x20 ~ 0x21) Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS R Reserved R Reserved Timing loop lock (Symbol sync) R [1] Timing loop has locked [0] Timing loop has not locked Phase loop lock (Carrier sync) ...
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... VIT_SR12 [0] PARM_FIX [4] VIT_INV_SPEC [3] VIT9 0x31 (0x00) VIT_FR [2:0] Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS R/W Set to “0” R/W Set to “0” R/W Set to “0” R/W Set to “0” Tmp=(FMClk/FSR) (1/(2 CR)) FMClk: System Clock Frequency FSR: Symbol Rate, CR: Code Rate R/W 0: 1< ...
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... Addr. Signal name Width Property Description (Reset val) BYTE_SYNC [5] Sync02 0x36 [4:1] (0x00) VIT_SYNC [0] Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS Spectrum information monitoring R [1] Inv spectrum [0] Not inv spectrum Viterbi decoder current code rate [0] R=1/2 [1] R=2/3 R [2] R=3/4 [3] R=5/6 [4] R=6/7 ...
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... RCV_EN [7] DIS_LENGTH [6:4] DIS_RDY [3] DiS02 0x3B (0x00) SWICH_CON [2] LNB_CON [1:0] Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS Packet error polarity R/W [1] Active low [0] Active high Sync polarity R/W [1] Active low [0] Active high Data valid polarity R/W [1] Active low [0] Active high CDCLK polarity R/W ...
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... RegName Addr. Signal name Width Property Description (Reset val) Rf01 0x45 SLAVE_ADDR [6:0] (0x61) Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS R/W [1] Disable [0] OLF (active low) R/W [1] LNB down [0] Disable (active high) 13V/18V select register R/W [1] 18V [0] 13V LNB message contents ...
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... Err03 0x48 ERR_CNT_H [7:0] (0x00) Err04 0x49 PARITY_ERR [7:0] (0x00) Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS R/W Set to “1” R/W Set to “1” Error monitoring source [0] QPSK bit errors R/W [1] Viterbi bit errors [2] Viterbi byte errors [3] Packet errors ...
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... Differential Linearity Error OFF Offset Error Voltage GAIN Gain Error Voltage Signal to Noise & SNDR Distortion Ratio FIN Analog Input Bandwidth FS Sampling Frequency Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS Parameter -0.3 to 4.6 -0 +/- 10 -40 to +125 0 to +70 Parameter 3.0 to 3.6 MAX 125 45 ...
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... D[7:0], D/P, STR_OUT, ERROR stable CKH after Figure 6 CLK_OUT D[7:0], D/P STR_OUT, ERROR t CKSU Figure 8 CLK_OUT D[7:0], D/P STR_OUT, ERROR t CKSU Samsung Electronics Co, Ltd. Proprietary Information Parameter Min 300 4 40 2*Tm (1) 2*Tm (1) CLK_OUT Falling Edge 2*Tm (1) 2*Tm (1) CLK_OUT Falling Edge = 90MHz. Refer to Figure 8 CLK 3.5 2 CLK_OUT Falling Edge f = 90M H z. Refer to Figure 9 CLK 3 ...
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... I C bus timing diagram 4 % " ’ %" 45" Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS Test Condition s Min Pull 10% - 0.5 2.0 Pull 10% VIN = -10 0 VOL = 0.5V Normal Mode 0 Standby Mode 0 1 ...
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... DATA5 3 3’4 % " 3’ " @" ’ O ’ Samsung Electronics Co, Ltd. Proprietary Information S5H1420 DBS Channel Decoder for DVB-S/DSS ’ &’ ’ &’ ’ O ’ ...
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... Package Dimension #64 #1 0.50 NOTE: Dimensions are in millimeters. Samsung Electronics Co, Ltd. Proprietary Information 12.00 + 0.20 10.00 + 0.07 0.20 - 0.03 0.08 MAX M S5H1420 DBS Channel Decoder for DVB-S/DSS 0-7 + 0.073 0.127 - 0.037 0.25TYP 0.08 MAX 0.05 MIN 1.40 + 0.05 1.60 MAX - - 30 ...
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... Update chapter : 3.3.1 Loop equation (Page 7). Update chapter : 3.4.9.2 Serial output interface (Page 10). Update chapter : 3.4.9.3 MPEG Clock Control (Page 12). Samsung Electronics Co, Ltd. www.samsung.com T : 82-31-279-7640 Suwon P.O.BOX 416 Maetan-3dong, YoungTong-gu, Suwon-si, Gyeonggi-do, Korea 442-742 Samsung Electronics Co, Ltd. Proprietary Information (Page 16). ’ ...