AD1991ASVRL Analog Devices Inc, AD1991ASVRL Datasheet - Page 5

• Manufacturer Part Number: AD1991ASVRL
• Description: IC AMP AUDIO PWR 40W STER 52TQFP
• Manufacturer: Analog Devices Inc
• Type: Class Dr

Specifications of AD1991ASVRL

• Rohs Status: RoHS non-compliant
• Output Type: 2-Channel (Stereo) or 4-Channel (Quad)
• Max Output Power X Channels @ Load: 40W x 1 @ 4 Ohm; 20W x 2 @ 8 Ohm
• Voltage - Supply: 6.5 V ~ 22.5 V
• Features: Depop, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Package / Case: 52-TQFP, 52-VQFP

Pin No.
1
2, 3, 4
5, 6, 7
8, 9, 10
11, 12, 13
14
15
16
17
18
19
20
21
22
23
24
25
26
27, 28, 29
30, 31, 32
33, 34, 35
36, 37, 38
39, 40, 41, 42 PGND2
43, 45, 48, 49 AGND
44
46
47
50, 51, 52
REV. 0
Mnemonic In/Out
PGND1
OUTA
PV
OUTB
PGND1
ERR3
ERR2
ERR1
ERR0
INA
INB
DV
DGND
MUTE
INC
IND
RST/PDN
CLK
PGND2
OUTD
PV
OUTC
MODE0
AV
MODE1
PGND1
DD1
DD2
DD
DD
O
O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
O
O
I
Description
Negative power supply for high power Transistors A2 and B2.
Output of transistor pair A1 and A2.
Positive power supply for high power Transistors A1 and B1.
Output of transistor pair B1 and B2.
Negative power supply for high power Transistors A2 and B2.
Edge speed setting MSB during RESET/active low thermal shutdown error output during
normal operation.
Edge speed setting Bit 1 during RESET/active low thermal warning error output during
normal operation.
Nonoverlap time setting MSB during RESET/active thermal low shutdown error output
during normal operation.
Nonoverlap time setting Bit 1 during RESET/active low data-loss error output or low-side
transistor disable input during normal operation.
Control pin for Transistors A1 and A2 always; also control pin for B1 and B2 in 2-channel mode.
Edge speed setting LSB during RESET/during normal operation, control pin for Transistors
B1 and B2 in 4-channel mode; no function in 2-channel mode.
Positive power supply for low power digital circuitry.
Negative power supply for low power digital circuitry.
Active low clickless mute input.
Control pin for Transistors C1 and C2 always; also control pin for D1 and D2 in 2-channel mode.
Nonoverlap time setting LSB during RESET/during normal operation, control pin for Transis-
tors D1 and D2 in 4-channel mode; no function in 2-channel mode.
Active low RESET/power-down input.
External clock input in external clock mode.
Negative power supply for high power Transistors C2 and D2.
Output of transistor pair D1 and D2.
Positive power supply for high power Transistors C1 and D1.
Output of transistor pair C1 and C2.
Negative power supply for high power Transistors C2 and D2.
Negative power supply for low power analog circuitry.
Clock source select (referenced to AGND); normally connected to AGND.
Positive power supply for low power analog circuitry.
Channel mode select (referenced to AGND).
Negative power supply for high power Transistors A2 and B2.
PGND1
PGND1
PGND1
PGND1
PV
PV
PV
OUTA
OUTA
OUTA
OUTB
OUTB
OUTB
DD1
DD1
DD1
10
11
12
13
PIN FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48
PIN CONFIGURATION
PIN 1
IDENTIFIER
(Not to Scale)
AD1991
TOP VIEW
47 46 45 44
–5–
43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
PGND2
OUTC
OUTC
OUTC
PV
PV
PV
OUTD
OUTD
OUTD
PGND2
PGND2
PGND2
DD2
DD2
DD2
AD1991