K4R271669F Samsung, K4R271669F Datasheet
K4R271669F
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K4R271669F Summary of contents
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... K4R271669F 128Mbit RDRAM 256K x 16 bit x 32s Banks Direct RDRAM £ TM Version 1.41 January 2004 Page -1 Direct RDRAM (F-die) Version 1.41 Jan. 2004 ™ ...
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... K4R271669F Change History Version 1.4 ( September 2003 ) - First Copy ( Version 1.4 is named to unify the version of component and device operation datasheets) - Based on the 128Mbit E-die RDRAM Version 1.41 ( January 2004 ) - Add the part number for leaded package. £ for short channel Datasheet Version 1.4 Page 0 ™ ...
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... Lead free consumer package. c. “R” - Leaded consumer package. for up Page 1 ™ Direct RDRAM x x CS8 CS8 Speed t RAC Part Number (Row Access Time K4R271669F-T CS8 c 45 K4R271669F-R CS8 Version 1.41 Jan. 2004 ...
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... Top View A b. Top marking example SEC 240 SEC 240 CS8 CS8 x x K4R271669F K4R271669F For consumer package, pin #1(ROW 1, COL A) is located at the A1 position on the top side and the A1 x position is marked by the marker “ CFM CFMN RQ5 DQA2 VDDA ...
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... K4R271669F Signal I/O Type a SIO1,SIO0 I/O CMOS a CMD I CMOS a SCK I CMOS DDa V CMOS GND GNDa b DQA7..DQA0 I/O RSL b CFM I RSL b CFMN I RSL V REF b CTMN I RSL b CTM I RSL RQ7..RQ5 RSL ROW2..ROW0 RQ4..RQ0 RSL COL4..COL0 DQB7.. b I/O RSL DQB0 ...
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... K4R271669F RQ7..RQ5 or DQB7..DQB0 ROW2..ROW0 3 8 RCLK 1:8 Demux Packet Decode ROWR ROWA ROP Match Mux DM Row Decode PRER ACT Sense Amp 32x64 Internal DQB Data Path Figure 2: 128Mbit(256Kx16x32s) RDRAM Device Block Diagram ...
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... K4R271669F General Description Figure block diagram of the 128Mbit RDRAM device. It consists of two major blocks: a “core” block built from banks and sense amps similar to those found in other types TM of DRAM and a Direct Rambus interface block which permits an external controller to access this core ...
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... K4R271669F Packet Format Figure 3 shows the formats of the ROWA and ROWR packets on the ROW pins. Table 3 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM device ...
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... K4R271669F CTM/CFM ROW2 DR4T DR2 BR0 BR3 RsvR R8 ROW1 DR4F DR1 BR1 BR4 RsvR R7 ROW0 DR3 DR0 BR2 RsvB AV=1 R6 ROWA Packet CTM/CFM DC4 S=1 COL4 DC3 COL3 DC2 COP1 COL2 DC1 COP0 COL1 DC0 COP2 COP3 BC3 BC0 ...
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... K4R271669F Field Encoding Summary Table 5 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a ...
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... K4R271669F Table 7 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure 18 for a more detailed description ...
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... K4R271669F Electrical Conditions Symbol Parameter and Conditions T Junction temperature under bias Supply voltage DD, DDA V V Supply voltage droop (DC) during NAP interval (t DD,N, DDA Supply voltage ripple (AC) during NAP interval (t DD,N, DDA,N Supply voltage for CMOS pins (2.5V controllers CMOS Supply voltage for CMOS pins (1.8V controllers) ...
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... K4R271669F Electrical Characteristics Symbol Parameter and Conditions 4 Junction-to-Case thermal resistance current @ V REF REF REF,MAX I RSL output high current @ (0dV OH I RSL I current @ V ALL RSL I current resolution step Dynamic output impedance @ V OUT I RSL I current @ V OL,NOM CMOS input leakage current @ (0dV ...
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... K4R271669F Timing Conditions Symbol t CTM and CFM cycle times (-800) CYCLE CTM and CFM input rise and fall times. Use the minimum value these parameters during testing CTM and CFM high and low times CH CL CTM-CFM differential (MSE/MS=0/0) ...
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... K4R271669F Symbol t Temperature control interval TEMP t TCE command to TCAL command TCEN t TCAL command to quiet window TCAL t Quiet window (no read data) TCQUIET t RDRAM device delay (no RSL operations allowed) PAUSE a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0. ...
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... K4R271669F Timing Characteristics Symbol t CTM-to-DQA/DQB output time @ DQA/DQB output rise and fall times SCK(neg)-to-SIO0 delay @ SCK(pos)-to-SIO0 delay @ SIO rise/fall @ C QR1 QF1 OUT LOAD,MAX t SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C PROP1 t NAP exit delay - phase A ...
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... K4R271669F Timing Parameters Parameter Row Cycle time of RDRAM banks -the interval between ROWA packets with ACT t RC commands to the same bank. RAS-asserted time of RDRAM bank - the interval between ROWA packet with t RAS ACT command and next ROWR packet with PRER Row Precharge time of RDRAM banks - the interval between ROWR packet with ...
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... K4R271669F Absolute Maximum Rating Symbol Parameter V Voltage applied to any RSL or CMOS pin with respect to Gnd I,ABS Voltage on VDD and VDDA with respect to Gnd DD,ABS DDA,ABS T Storage temperature STORE T Minimum operation temperature MIN Note*) Refer Supply Current Profile ...
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... K4R271669F Capacitance and Inductance Symbol Parameter and Conditions - RSL pins L RSL effective input inductance I Mutual inductance between any DQA or DQB RSL signals L 12 Mutual inductance between any ROW or COL RSL signals 'L Difference in L value between any RSL pins of a single device. ...
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... K4R271669F Center-Bonded Fanout Package (54 Balls) Figure 4 shows the form and dimensions of the recom- mended package for the center-bonded Fanout CSP device class Figure 4: Center-Bonded fanout CSP Package Table 19: Center-Bonded Fanout CSP Package Dimension Symbol ...