LH28F160S3NS-L10 Sharp, LH28F160S3NS-L10 Datasheet
LH28F160S3NS-L10
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LH28F160S3NS-L10 Summary of contents
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... P S RODUCT PECIFICATIONS LH28F160S3NS-L10 Flash Memory 16M (2MB × 8/1MB × 16) (Model No.: LHF16KA1) Issue Date: August 22, 2000 ® Spec No.: EL128039 Integrated Circuits Group ...
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... SHARP l Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions ...
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... SHARP I INTRODUCTION ...................................................... 1 .l Product Overview.. .............................................. ! PRINCIPLES OF OPERATION.. .............................. 2.1 Data Protection ................................................... I BUS OPERATION.. .................................................. 3.1 Read ................................................................... 3.2 Output Disable ..................................................... 3.3 Standby.. ............................................................. 3.4 Deep Power-Down .............................................. 3.5 Read Identifier Codes Operation.. ....................... 3.6 Query Operation.. ................................................ 3.7 Write.. .................................................................. COMMAND DEFINITIONS.. ..................................... 4.1 Read Array Command.. ..................................... 4.2 Read Identifier Codes Command.. .................... 4.3 Read Status Register Command.. ..................... 4.4 Clear Status Register Command.. ..................... ...
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... Ind extended cycling provide for highly flexible component :ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. iecure code storage applications, such as networking, downloaded to DRAM, the LH28F160S3NS-L10 SND, selective hardware block locking, or flexible software ultimate control of their code security needs. -he LH28F160S3NS-LlO ...
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... This datasheet contains LH28F160S3NS-LlO specifications. Section 1 provides a flash memory overview. Sections and 5 describe memory organization and functionality. covers electrical specifications. 1.1 Product Overview The LH28F160S3NS-LlO is a high-performance bit Smart 3 Flash memory 2MBx8/1MBxlG. The 2MB of data is arranged thirty-two 64K-byte blocks which erasable, lockable, and unlockable memory map is shown in Figure 3 ...
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... SHARP CE,,# :O A12 3 A13 4 A14 CEl A20 Ale 11 12 A17 46 13 vcc 14 GND 15 DQ6 16 17 DO14 DQ7 18 DQls 19 S-6 20 OE# 21 WE# 22 WP# 23 DQn 24 25 DQ5 26 DQ12 DQ4 ;3 vcc LHFlGKAl Figure 1. Block Diagram 56 LEAD SSOP PINOUT 1 ...
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... SHARP Type Symbol ADDRESS INPUTS: Inputs for addresses durinq read and write operations. Addresses are internally latched during a write cycle. Ao: Byte Select Address. Not used in x16 mode(can be floated). INPUT *o-*20 AI-AK Column Address. Selects bit lines. AsAls: Row Address. Selects 1 of 2048 word lines. ...
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... SHARP 2 PRINCIPLES OF OPERATION The LH28F160S3NSLlO Flash memory includes an on-chip WSM to manage block erase, full chip erase, write and (multi) word/byte configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies erase, full chip erase, (multi) word/byte block lock-bit configuration, and minimal processor overhead with RAM-Like interface timings ...
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... RP#-low STS remains low until the is required after RP# device important to flash memories provide status If a CPU reset occurs with no flash CPU initialization may not instead of array data. SHARP’s allow proper CPU initialization RP# is controlled by the 7 ...
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... SHARP ,5 Read Identifier Codes Operation ie read identifier codes operation anufacturer code, device code, block status codes r each block (see Figure 4). Using the manufacturer Id device codes, the system CPU can automatically atch the device with its proper algorithms. ock status codes identify locked or unlocked block ...
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... SHARP Mode 1 Notes 1 RP# Read Output Disable Standby IOTES: . Refer to DC Characteristics. When Vpp<VppLK, memory contents can be read, but not altered can be V,, or VrH for control pins and addresses, and V,,,, vPPLK and vPPHll~3 vohw- . STS is VoL (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase, (multi) word/byte write or block lock-bit configuration algorithms ...
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... Following the Third Bus Cycle, inputs the write address and write data of ‘N’ times. Finally, input the confirm command ‘DOH’. 3. Commands other than those shown above are reserved by SHARP for future device implementations should not be used. LHFlGKAl Table 4. ...
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SHARI= 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads ...
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... SHARP 4.5 Query Command Query database can be read by writing :ommand (98H). Following the command cycle from address shown in Table 7-l 1 retrieve the xitical information to write, erase :ontrol the flash component query address is ignored when X8 mode (BYTE#=V,,). 3uery data are always presented on the low-byte ...
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SHARI= 4.5.2 CFI Query Identification The Identification String provides specification. Additionally, it indicates which version of the spec and which Vendor-specified supported. Table 8. CFI Query Identification Offset Length (Word Address) 03H Query Unique ASCII string “QRY” lOH,l lH,12H 51 ...
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SHARI= 3.5.4 Device Geometry Definition rhis field provides critical details of the flash device geometry. Off set Length (Word Address) 27H OlH Device Size 15H (15H=21,221=20971 28H,29H 02H Flash Device interface description 02H,OOH (x8/x1 6 supports x8 and xl 6 ...
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... SHARP 4.6 Block Erase Command Block erase is executed one block at a time and initiated by a two-cycle command. setup is first written, followed by an block erase confirm. This command sequence appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH) ...
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... For additional multi word/byte write, write anothe multi word/byte write setup and check XSR.7. The Multi Word/Byte while WSM is busy as long as XSR.7 indicates because LH28F160S3NS-LlO when error occurs while writing, the device will stop writin{ and flush next multi word/byte write command are protected in multi word/byte write command ...
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SHARI= 4.10 Block Erase Suspend Command The Block Erase Suspend command erase interruption to read or (multi) word/byte-write data in another block of memory. Once the block- writing the erase process starts, Suspend command requests that the WSM suspend the ...
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... SHARP 4.12 Set Block Lock-Bit Command A flexible block locking and unlocking enabled via block lock-bits. The block lock-bits gate program and erase operations individual block lock-bits can be set using the Set Block Lock-Bit command. See Table summary of hardware and software write protection options ...
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SHARI= 4.14 STS Configuration Command The Status (STS) pin can be configured states using the STS Configuration command. the STS pin has been configured, it remains in that configuration until another configuration issued, the device is powered down or RP# ...
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... SHARP WSMS 1 1 ECBLBS BESS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS STATUS 1 = Error in Erase or Clear Bloc1 Lock-Bits 0 = Successful Erase or Clear Block Lock-Bits SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS ...
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SHARI= f Road Status Register FULL STATUS CHECK PROCEDURE (E) Block Erase Successful Figure 5. Automated LHFlGKAl Read Status DstalOH Rqster AddhX Read Status Re+ter Check SR.7 l-W.%4 Ready o=.wsM Busy Data-ZJH Etase Setup write AcklbWitim DaQDOH Writ.3 A&Jr-Withm Block ...
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... SHARP r !3arl * Wnta 70H + Read Status G-tack if Desired Complete FULL STATUS CHECK PROCEDURE Reed status RaglStw Data(Sw Above) Full Chip Erase SUCCWdlll Figure 6. Automated LHF16KAl Bm Commvld Opmaon Data70H Read Status Wrilo Register AddhX Status Register Data Read Check SR.7 l-W%4 Ready Slandbl OIWSM Busy Data& ...
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SHARI= Data and Addmss Complete FULLSTATUSCHECKPROCEDURE Read St&us Register Data(See Above) Figure 7. Automated I LHFlGKAl Bus Command OprdiOn Data-7OH Writ9 Addr-X Read Status Rogirter Data Check SR.7 l=WSM Redy Standby o=WSM susy Setup wordmyte Data-4OH or 10H Wlite Write ...
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... SHARP Full Status Check if Dewed Figure 8. Automated LHFlGKAl Command Write Multi Wordlsyte Write Read standby Write (Notal) Wflte (Note2.3) Wnte (Note4.5) write Read Standby 1. Byte or word count values on DO,,., are loaded into the count register. 2. Write Buffer contents mll be programmed at me start address. ...
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... SHARP FULL STATUS CHECIC PROCEDURE FOR MlLTl WORCMBYIE WRITE OPERATION Device Protect Error Figure 9. Full Status Check Procedure for Automated LHFlGKAl Bus Command opwalfon Check SR.3 l=Vpp Error Detect Check SR.1 1lDwico Pmtect Detect WP*IV,~.B!G~ only mquimd for syslams implementing lock-bit configuration Check SR.4.5 Both f-Command Check SR ...
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... SHARP O 1 c> SR.7P (Mulli) WorrUByte Write Loop Wnte DOH c I Figure 10. Block Erase Suspend/Resume LHFlGKAl Btm Commmd OpWliOn Writ0 Read stancby standby Ento Wti Rasuma Write FFH I Flowchart caatmanb Data-B0H AddhX Statur Rogistar Data AddhX Check SA.7 l.WSM Rae&j OIWSM Busy ChodcSR.0 11Btock Erase Surpw~Ied O-Block Erase Completed Da& ...
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... SHARP 0 %I.?= 1 + (Multi) wofcuByte write Completed Wtita FFH I Figure 11. (Multi) Word/Byte LHF16KAl Bus 0 Command I (Multi) Wad/Byte Wtite Data-SOH 1 wli(e 1 Suspend 1 Addh* chedc SR.2 l.(Multl) WordByte SMpWlded 0+4ulti) WordByte Completed i_ Data-FFH Write Read Array Ac!dr=X F Write Write Suspend/Resume Flowchart 27 Commenta write write ...
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... SHARP Resd Status Register t-’ 0 SIX?= 1 Check if Desired FULLSTATUSCHECKPROCEDtJRE Read Stah~o Register Data(see Abwe) Device Protect Ermr Set Block Lock-&t successful Figure 12. Set Block Lock-Bit Flowchart LHFlGKAl Bus Command Op&iOll Set Block DaradOH Write Leek-Bit Seh~p Addr=Slock Address Sat Block Data-01 H ...
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... SHARP SR.7 FULL STATUS CHECK PROCEDURE Read Status Register Data&See Above) I Device Protect Error Clear Block Lock-Bits Successful Figure 13. Clear Block Lock-Bits Flowchart LHFlGKAl Bus Cammmd Opdh Ckr Block Data&H Writ9 AddhX Lock-Sits Setup clear sbck Data-DOH Wlikl Lock-Sib Confirm Addr=X ...
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... SHARP 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control accommodate multiple memory connections. Line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’ ...
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... SHARP. 5.5 VcC, Vpp, RP# Transitions Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are not guaranteed V,, falls outside of a valid VPPHI12/s range, Vco falls outside of a valid VCCIR range, or RP#=V,,. If V,, error is detected, status register bit SR.3 is set to “1” ...
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... SHARP 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Erase, Write and Block Lock-Bit Configuration . . . . . . ..O”C to +7O”C(‘) Temperature under Bias . . . . . . . . . . . . . . . -10°C to +80X Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125”C Voltage On Any Pin (except V,,, V,,) . . . . . . . . . . . . . . . -0.5V to Vcc+0.5V(2) V,, Suply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to +7.ov(2) VP, Update Voltage during ...
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AC INPUT/OUTPUT TEST CONDITIONS AC test inputs are driven at 2.N for a Logic “1 ‘* and O.OV for a Logic Input rise and fall times (10% to 90%) Figure 14. Transient yi-~z+l-Lq~~ ‘AC test inputs are driven at ...
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SHARI= 5.2.3 DC CHARACTERISTICS Block Erase Full Chi LHFlGKAl DC Characteristics 34 Rev. 1.9 ...
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... SHARP Sym. Parameter VI, input Low Voltaae Input High Voltage VI, Output Low Voltage VOL Output High Voltage VoHr u-w Output High Voltage VOH2 (CMOS) VPPLK V,, Lockout Voltage during Normal Operations Vrqqrr V,, Voltage during Write or Erase Operations V,,H, V,, Voltage during Write or Erase Operations Vn,Hs V,, Voltage during Write or ...
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... SHARP 6.2.4 AC CHARACTERISTICS NOTE: See 3.3V V,, Read-Only Operations for notes 1 through 4. tELFL CE# Low to BYTE# High or Low tp, fz!+ JOTES: I. See AC input/Output Reference Waveform for maximum allowable input slew rate. !. OE# may be delayed up to tELQv-fGLQv after the falling edge of CE# without impact on tELQv. 5. Sampled, not 100% tested. ...
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... SHARP Address OE#(G) 1:: VIH WE#(W) VIL VOH HIGH Z DATA( D/Q) VOL 4 kc tPHOV NOTE: CE# is defined as the latter of CEo# and CE1# going Low or the first of CE# Figure 17. AC Waveform LHFlGKAl Device Selection Address Stable tGLa ...“‘- tELQv l * kLOX -* . kLOXb * ,,......11 tAVOV l or CE1# going ...
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... SHARP r Address VOH HIGH Z DATA( D/Q) PQe-DQd VOL NOTE: CE# is defined as the latter of CEo# and CE,# LHFlGKAl Device Data Valid Selection ,,,11..111 Address Stable going Low or the first of CEo# or CE# Figure 18. BYTE# Timing Waveforms 38 Z HIGH going High. Rev. 1.9 ...
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... SHARP 6.2.5 AC CHARACTERISTICS &,,,,,,, WE# Pulse Width High tlJ#q, WE# High to STS Going Low &&jr,, Write Recovery before Read VP,, Hold from Valid SRD, STS High Z JflWl WP# VI,, Hold from Valid SRD, STS High Z VSI NOTE: See 3.3V Vcc WE#-Controlled Writes for notes 1 through 5. Versiond5) Sym ...
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... SHARP -o---o hi ADDRESSES(A) VIL hi CE#(E) VS VIH OE#(G) VIL VIH WE#(W) VIL VIH DATA( D/Q) VIL High STS(R) VOL WP#(S) NOTES: 1. Vcc power-up and standby. 2. Write erase or write setup. 3. Write erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command ...
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SHARI= 6.2.6 ALTERNATIVE CE#-CONTROLLED Versions@) Sym. 1 Parameter I Data Setup to CE# Going High II tFHnv 1 Data Hold from CE# High NOTE: See 3.3V V,, Alternative CE#-Controlled I, tfw&y Address Hc tFHWH WE# Hold t&HF, CE# Pulse Width ...
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SHARI= ADDRESSES(A) NOTES: 1. Vcc power-up and standby. 2. Write erase or write setup. 3. Write erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. 7. ...
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... SHARP 6.2.7 RESET OPERATIONS High Z STS(R) VOL VIH RP#(P) WL High Z STS( R) VOL VIH RP#(P) VIL VIH RP#(P) VIL Figure 21. AC Waveform Symbol Parameter RP# Pulse Low Time tPLPH (If RP# is tied to Vco, this specification is not applicable) RP# Low to Reset during Block Erase, tPLRH Full Chip Erase, (Multi) Word/Byte Write ...
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SHARI= 5.2.8 BLOCK ERASE, FULL CHI LOCK-BIT CONFIGURATK Sym. Parameter Word/Bvte Write Time (using W/B write, in word mode) Word/Byte Write Time (using W/B write, in byte mode) Word/Bvte Write Time , (using multi word/byte write) Block Write Time (using ...
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... SHARP I Word/B Block Write Time (using W/B write, in word mode) Block Write Time (using W/B write, in byte mode) Block Write Time (using multi word/byte write) t b”, Block Erase Time wHQV* Full Chip Erase Time I twHQvs Set Block Lock-Bit Time t tFHO”d WHQV4 ...
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... P- Architecture S = Regular Block Power Supply Type 3 = Smart 3 Technology Operating Temperature Ii Blank = 0°C - +7O” -40°C - +85”C $tion Order Code 1 LH28F160S3NS-LlO LHFlGKAl U w Access Speed (ns) 10:lOOns (3.3V), 120ns (2.7V) 13: 130ns (3.3V), 150ns (2.7V) Package T = 56-Lead TSOP R = 56-Lead TSOP(Reverse Bend 56-Lead SSOP B = 64-Ball CSP D = 64-Lead SDIP ...
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... SHARP 8 Package and packing specification lAorage Conditions. I-1Storage conditions required before opening the dry packing. * Normal temperature : 5-40°C Normal humidity : 80% l 1-2.Storage conditions required In order to prevent moisture absorption after opening, ensure the following conditions apply: (1) Storage conditions for one-time soldering. (Convection reflow, IWConvection V.P.S., or Manual soldering. > ...
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... SHARP 2. Baking Condition. (1) Situations requiring baking before mounting. Storage conditions exceed the limits specified in Section l-2 or l-3. l Humidity indicator in the desiccant was already pink when opened Also for re-opening.) (2) Recommended baking conditions. Baking temperature l 120°C for 16-24 hours. * The above baking conditions apply since the trays are heat-resistant. ...
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... SHARP (2) Convection reflow or IFUConvection. * Temperature and period : Peak temperature Above 200°C for 50 sec. max. Preheat temperature Temperature increase rate of l-3”C/sec. - Measuring point : IC package surface. * Temperature profile : (3) V.P.S.( one-time soldering only > Temperature and period : l Peak temperature Preheat temperature Temperature increase rate of 1&4”C/sec. ...
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... SHARP (4) Manual soldering ( soldering iron ) ( one-time soldering only > Soldering iron should only touch the IC’s outer leads. - Temperature and period : 350°C max. for 3 sec. I pin max., or 260°C max. for 10 sec. I pin max. (Soldering iron should only touch the It’s outer leads.) Measuring point : Soldering iron tip ...
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... SHARP 5. Package outline spec.i&ation. Refer to the attached drawing. 6. Markings. 6-l.Marking details. (The information ( 1) Product name : LH28F160S3NS-L.10 (2) Company name : (3) Date code (Example (4) “JAPAN” indicates the country of origin. 6-2.Marking layout. The layout is shown in the attached drawing. (However, this layout does not specify the size of the marking LHFlGKAl on the package should be given as follows ...
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Sl-tARP DETAIL l\i9+% y, ‘J - F6EB@ ! LEAD FINISH i TIN-LEAD PLATING AME i SSOPO56-P-0600 I 0 *4il bRAWING NO. j AA2021 UNIT LH-FIGKAI f0. 15 & ‘I - FW@ ...
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... T-9 L-r79 bEI Marking layout LH28F160S3NS-LlO Pin SHARP JAPAN YYWW xxx ...
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... SHARP - 7.Packing Specifications (Dry packing for surface mount packages.) 7- l.Packing materials. Material name ) Material Inner carton 1 Cardboard I ! max. > nay f Conductive Upper cover tray j Conductive Laminated aluminum f Aluminum bag Desiccant j Silica gel Label 1 Paper PP band 1 Polypropylene Outer carton / Cardboard I I max Devices must be placed on the tray in the same direction.) 7-2 ...
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IS 18.4. h-%3- ...
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... SHARP l-L-f!% a%&& Packing specifications , I I &CL i UNIT i mm DRAWING NO. [ BJ433 \ Outer carton label Inner carton - Outer dimensions Outer carton - Outer dimensions *tkt%a%Q6~~7mosE3 #ii* XRBS;73~%&D%G. NOTE There is a possibility different specification when the number of shipments is fractions. 56 Two rows ...